Scalable Implementation of Hippocampal Network on Digital Neuromorphic System towards Brain-Inspired Intelligence
Abstract
:1. Introduction
2. The Hippocampal Neural Network Model
3. Digital Implementation
3.1. Network-On-Chip (NoC) Architecture
Algorithm 1: The HIP router for routing the packets in torus-based NoC |
loop if posedge clk then Δx1=XC-1; Δx2= WN-XC; //WN: Width of the NoC, XC: xcurrent Δy1=YC-1; Δy2= HN-YC; // HN: Height of the NoC, YC: ycurrent Δxsign <-((xdest-XC) > 0)?0:l Δysign <- ((ydest-YC) > 0)?0:l if Δxsign = 0 then Δx<- (xdest-XC); Δxreverse<- (WN -xdest) + XC; if Δx ≤ Δxreverse then Route the packet EAST; else Route the packet WEST; end if else {Δxsign != 0}; Δx<- (XC-xdest); Δxreverse<- (WN -XC) + xdest; if Δx ≤ Δxreverse then Route the packet WEST; else Route the packet EAST; end if end if if Δysign = 0 then Δy<- (ydest-YC); Δyreverse <- (HN -ydest) + YC; if Δy ≤ Δyreverse then Route the packet SOUTH; else Route the packet NORTH; end if else {Δysign != 0}; Δy<- (YC-ydest); /Δyreverse <- (HN -YC) + ydest; if Δy ≤ Δyreverse then Route the packet NORTH; else Route the packet SOUTH; end if end if if XC=1 or XC=WN or YC=1 or YC= HN then Route the packet UP; // The situation that the current node is the edge node elseif Δxl>=Δx2 then Route the packet West; else Route the packet East; end if end if end loop |
3.2. CORDIC-Based Neuron Design
3.3. Neuron Implementation
4. Experimental Results
5. Conclusions
Author Contributions
Funding
Conflicts of Interest
References
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Excitatory Neuron | Inhibitory Neuron | |
---|---|---|
a | 0.04 | 0.04 |
b | 5 | 5 |
c | 140 | 140 |
τu | 43 ± 4.3 | 100 ± 0 |
ku | 0.24 ± 0.02 | 0.25 ± 0 |
V0 | −65 ± 6.5 | −65 ± 0 |
ΔU | 10 ± 1 | 1 ± 0 |
Resources | Conventional | CORDIC-Based |
---|---|---|
Combinational ALUTs | 19,652/203,520 (10%) | 10,642/203,520 (5%) |
Memory ALUTs | 490/101,760 (<1%) | 712/101,760 (1%) |
Dedicated logic registers | 8924/203,520 (4%) | 11,546/203,520 (6%) |
Total block memory bits | 7,771,246/15,040,512 (52%) | 2106/15,040,512 (<1%) |
DSP block 18-bit elements | 2384/768 (310%) | 0/768 (0%) |
Total PLLs | 1/8 (13%) | 1/8 (13%) |
Work | Motivation | Network Structure | Hardware Architecture |
---|---|---|---|
[27] | Visual pathway-inspired | Feedforward | No NoC design |
[34] | Hippocampus-inspired | Feedforward | No NoC design |
[36] | CPG-inspired | CPG | No NoC design |
[37] | Purkinje-inspired | Recurrent | No NoC design |
[38] | Retina-inspired | Feedforward | No NoC design |
This study | Hippocampus-inspired | Recurrent | Torus-based NoC design |
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Sun, W.; Wang, J.; Zhang, N.; Yang, S. Scalable Implementation of Hippocampal Network on Digital Neuromorphic System towards Brain-Inspired Intelligence. Appl. Sci. 2020, 10, 2857. https://doi.org/10.3390/app10082857
Sun W, Wang J, Zhang N, Yang S. Scalable Implementation of Hippocampal Network on Digital Neuromorphic System towards Brain-Inspired Intelligence. Applied Sciences. 2020; 10(8):2857. https://doi.org/10.3390/app10082857
Chicago/Turabian StyleSun, Wei, Jiang Wang, Nan Zhang, and Shuangming Yang. 2020. "Scalable Implementation of Hippocampal Network on Digital Neuromorphic System towards Brain-Inspired Intelligence" Applied Sciences 10, no. 8: 2857. https://doi.org/10.3390/app10082857
APA StyleSun, W., Wang, J., Zhang, N., & Yang, S. (2020). Scalable Implementation of Hippocampal Network on Digital Neuromorphic System towards Brain-Inspired Intelligence. Applied Sciences, 10(8), 2857. https://doi.org/10.3390/app10082857