Dual Control Strategy for Non-Minimum Phase Behavior Mitigation in DC-DC Boost Converters Using Finite Control Set Model Predictive Control and Proportional–Integral Controllers

Featured Application

The proposed control strategy is specifically designed for applications with non-minimum phase behavior. It can be effectively applied to DC-DC boost converters, dual active bridge converters, and other topologies like buck-boost, Cuk, SEPIC, and ZETA converters, all of which commonly exhibit non-minimum phase characteristics.

Abstract

Model Predictive Control (MPC) has emerged as a promising alternative for controlling power converters, offering benefits such as flexibility, simplicity, and rapid control response, particularly when short-horizon algorithms are employed. This paper introduces a system using a short-horizon Finite Control Set MPC (FCS-MPC) strategy to specifically address the challenge of non-minimum phase behavior in boost converters. The non-minimum phase issue, which complicates the control process by introducing an initial inverse response, is effectively mitigated by the proposed method. A Proportional–Integral (PI) controller is integrated to dynamically adjust the reference current based on the output voltage error, thereby enhancing overall system stability and performance. Unlike conventional PI-MPC methods, where the PI controller has an influence on the system dynamics, the PI controller in this approach is solely used for tuning the reference current needed for the FCS-MPC controller. The PI controller addresses small deviations in output voltage, primarily due to model prediction inaccuracies, ensuring steady-state accuracy, while the FCS-MPC handles fast dynamic responses to adapt the controller’s behavior based on load conditions. This dual control strategy effectively balances the need for precise voltage regulation and rapid adaptation to varying load conditions. The proposed method’s effectiveness is validated through a multi-stage simulation test, demonstrating significant improvements in response time and stability compared to traditional control methods. Hardware-in-the-loop testing further confirms the system’s robustness and potential for real-time applications in power electronics.

1. Introduction

The integration of renewable energies, such as solar and wind power, into the electrical grid is revolutionizing the traditional paradigm of electricity generation. Unlike conventional thermal, nuclear, or hydraulic power plants that rely on electrical machines, renewable energy systems primarily use power electronic converters to interface with the grid. Among these, DC-DC converters, particularly boost converters, are crucial for stepping up voltage levels to meet grid requirements [1,2]. Traditionally, these converters have used Proportional–Integral (PI) controllers [3]. However, Model Predictive Control (MPC) is now recognized as a superior strategy due to its ability to handle fast dynamic behaviors in modern power converters. MPC predicts future system states and optimizes control inputs in real time, ensuring a rapid response to changes in operating conditions. This predictive capability allows MPC to manage various performance criteria, such as voltage regulation, current control, and efficiency optimization, simultaneously through a single cost function [4,5,6].

MPC is implemented in two main forms: Continuous Control Set (CCS) and Finite Control Set (FCS). CCS-MPC operates on a continuous range of control inputs, providing smooth control but requiring high computational power and complex algorithms, making it less suitable for fast dynamics and real-time applications [7,8]. In contrast, FCS-MPC uses a discrete set of control actions, significantly reducing computational demands and enabling quicker decision making [9,10]. However, FCS-MPC faces challenges, such as stability issues when the sampling step is relatively big and the difficulty of managing non-minimum phase behavior in systems like boost converters when the prediction horizon is short [11].

To address the non-minimum phase issue in boost converters, a long-horizon approach is presented by Gardezi et al. [12] that employs machine learning for the adaptive prediction horizon in FCS-MPC, but the method’s complexity can be a disadvantage in real-time applications. Among short-horizon solutions, Villarroel et al. [13] propose an input-state linearization method for FCS-MPC, transforming system dynamics to eliminate instability with a short prediction horizon. Another method presented by Villarroel et al. [14] designs a specific cost function within the FCS-MPC framework for stable and precise voltage tracking, minimizing the output voltage error and smoothing control actions. Similarly, Pérez et al. [15] address the issue in active front end rectifiers with a predictive control strategy based on output power and DC link capacitor energy, avoiding additional modulators and achieving a zero steady-state error. Karamanakos et al. [16] present a DMPCC strategy for DC-DC boost converters using a hybrid model for precise current regulation, reducing computational complexity. Firpo et al. [17] use a non-linear MPC method with a partially saturating ferrite core inductor model to manage magnetic saturation and losses, ensuring correct voltage regulation. All these methods require precise parameter estimation, with inaccuracies leading to suboptimal performance, and are affected by load and input condition variations, necessitating robust estimation and adjustment mechanisms.

Another approach is to control the inductor current with an FCS-MPC controller, where the reference for the controller is provided by a PI controller [18,19,20]. In this method, the PI controller generates the reference current for the FCS-MPC based on the output voltage error. While this hybrid approach aims to combine the strengths of both controllers—using the PI controller for steady-state accuracy and the FCS-MPC for handling fast dynamics—the overall speed is compromised. The PI controller’s slower response time can negate the advantage of the FCS-MPC’s rapid switching capability, potentially missing out on the primary benefit of using an FCS-MPC. This results in a less responsive system that may not fully leverage the fast dynamic response that FCS-MPC controllers are designed to provide.

This paper presents a significant contribution to the field of power electronics by presenting a novel application of FCS-MPC for DC-DC boost converters. It addresses the non-minimum phase issue, a common challenge in the control of boost converters, by incorporating a PI regulator to adapt the reference current. The proposed method distinguishes itself by employing the Ideal Reference Calculator (IRC) block, which generates the primary reference current for the system based on ideal conditions. This allows the PI controller to focus solely on making small corrections to the reference current in steady-state situations, rather than managing fast dynamic changes. By decoupling the PI controller from fast dynamics, the FCS-MPC, combined with the IRC block, takes full responsibility for real-time adjustments and load changes, ensuring a fast dynamic response. This dual approach leverages the strengths of both controllers—steady-state precision from the PI controller and rapid adaptation from the FCS-MPC combined with the IRC block. The effectiveness of the proposed method is validated through both simulation and experimental results by hardware-in-the-loop (HIL) tests, demonstrating its potential for real-time applications requiring optimal performance and rapid response.

The rest of the paper is organized as follows: In Section 2, the DC-DC boost converter and its discrete model are introduced, establishing the foundation for the control strategy. The FCS-MPC strategy is detailed in Section 3, including its implementation, the choice of prediction horizon, and the formulation of the cost function. Section 4 focuses on the development of the proposed dual control approach, in which a PI controller is integrated to dynamically adjust the reference current, addressing the non-minimum phase issue. In Section 5, the simulation and hardware-in-the-loop (HIL) test results are presented, vali-dating the proposed method, and demonstrating significant improvements in response time and stability compared to traditional control methods. Finally, Section 6 provides the conclusions, summarizing the findings.

2. Application Example

This paper focuses on the application example of a boost converter, although the idea can be adapted to other topologies that face non-minimum phase issues. The proposed method is necessary for boost converters because conventional FCS-MPC strategies struggle to manage the inherent non-minimum phase dynamics, which cause initial voltage undershoots when increasing the output voltage. This topology is also useful for understanding the non-minimum phase phenomena in power converters and FCS-MPC due to its simplicity. In a boost converter, the main objective is to have a higher output voltage than in the input; this means that there is an increment of the DC voltage. Between the elements composing this circuit, there is a DC input voltage source (Vin), an inductor to store energy, a power electronic switch (represented by the variable Q), a diode (D) to transfer the energy stored in the inductor to the load, and a capacitor to smooth the output voltage. While different types of power transistors, such as MOSFETs or IGBTs, can be used as the switch, MOSFETs are more suitable for the mid-high switching frequencies used in the experimental results. IGBTs, on the other hand, may limit the maximum attainable frequency. For this specific design, a MOSFET is used and shown in the figures and schematics.

When the converter works in Continuous Conduction Mode (CCM), there are two equivalent sub-circuits, shown in Figure 1: when the MOSFET is turned on and when it is turned off. When the MOSFET is on (Figure 1a), it creates a low-impedance path for the current, allowing the inductor to store energy from the input voltage. During this state, the diode is reverse-biased, preventing current from flowing to the output. When the MOSFET is turned off (Figure 1b), the inductor’s stored energy is released. The inductor generates a high voltage, which forward-biases the diode, allowing current to flow to the output and simultaneously charging the output capacitor. This process boosts the output voltage to a level higher than the input voltage, hence the name “boost converter”. The rapid switching between these two states ensures a continuous transfer of energy, maintaining a higher steady-state output voltage. In Discontinuous Conduction Mode (DCM), illustrated in Figure 1c, the inductor current falls to zero during the off state of the MOSFET. This introduces a third sub-circuit where the diode is off, and both the inductor and capacitor are disconnected from the input voltage. During this state, the inductor does not transfer energy, and the output voltage is maintained solely by the charge stored in the capacitor. This mode typically occurs under light load conditions when the energy demand is low, resulting in periods where no current flows through the inductor.

The discrete differential equations of the boost converter, as represented by Equations (1) and (2), are essential for accurately modeling the system’s dynamics and are crucial for the prediction block in FCS-MPC. These equations enable the controller to predict the future inductor current and capacitor voltage, allowing for precise switching decisions.

$$v_C\left(k+1\right) = v_C\left(k\right) + {\displaystyle \frac{\mathsf{\Delta }t}{C}} · i_C\left(k\right)$$

(1)

$$i_L\left(k+1\right) = i_L\left(k\right) + {\displaystyle \frac{\mathsf{\Delta }t}{L}} · v_L\left(k\right)$$

(2)

For the sake of clarity, i_L(k) and v_C(k) represent the current values of the inductor current and output voltage, respectively, while i_L(k + 1) and v_C(k + 1) denote their future values. These future values will be the predicted ones in the next section. There are two primary states, as shown in

Table 1. Summary of the state behaviors of a boost converter in different situations.

	Situation I	Situation II
Parameters	Q: on	Q: off
vL	$V_{in}$	$V_{in}-v_c$
ic	$-v_c/R$	$i_L-v_c/R$

, representing the possible decisions that the controller can make: switching the MOSFET on (situation I) or off (situation II). Table 1 also provides the inductor voltage (v_L) and the capacitor current (i_C) for these two states, which are needed for the prediction block Equations (1) and (2).

Once the equations are defined, the model can be implemented using different numeric representations, depending on the objectives. The selected data type determines the minimum time step achievable for executing the model equations in an FPGA, as well as the design effort and hardware resources required. The two main possibilities for numerical formats are floating-point and fixed-point formats. The floating-point format, represented by the IEEE-754 standard [21], offers high precision and a wide dynamic range, simplifying the design process but requiring more computational resources and higher power consumption. The fixed-point format, where the number of bits for each variable are specified and remain fixed, provides lower computational costs and reduced hardware complexity due to the smaller size and faster computation times. This makes the fixed-point format more efficient in terms of resource usage and power consumption, ideal for real-time FPGA applications. However, it demands higher design effort to balance accuracy and resource utilization. Given these considerations, the fixed-point numeric type is the best option for implementing a combination of the HIL system and MPC algorithm in an FPGA, offering the necessary balance of efficiency, speed, and resource utilization for real-time control applications.

3. FCS-MPC Algorithm for Boost Converters

The FCS-MPC algorithm simplifies the optimization problem by limiting the controller outputs to a finite set, significantly reducing computational complexity. This characteristic makes it highly suitable for applications requiring fast dynamic responses, such as DC-DC boost converters. The core of FCS-MPC lies in predicting the future behavior of the converter based on a discrete model and optimizing control actions to minimize a cost function that typically includes terms for tracking the reference voltage and minimizing inductor current deviation. The short-horizon FCS-MPC implementation discussed in this paper focuses on predicting future states and evaluating potential switching actions within a single timeframe, enhancing the controller’s responsiveness to dynamic changes. However, this approach introduces challenges, particularly in managing the non-minimum phase behavior characteristic of boost converters.

The general block diagram for the short-horizon FCS-MPC implementation is demonstrated in Figure 2. It consists of a capacitor voltage predictor and an inductor current predictor that forecast the future states of these variables based on the discrete Equations (1) and (2). A cost function calculator evaluates the performance of each possible switching state, and an optimum state finder identifies the control action that minimizes the cost function. Finally, a pulse generator translates the optimal control action into switching signals for the power converter without involving any PWM modulator. For each possible switching state, the predicted inductor current (i_LP) and capacitor voltage (v_CP) can be calculated as follows:

$$\begin{array}{l}{i}_{LP}=\left\{\begin{array}{l}{i}_L+{\displaystyle \frac{\mathsf{\Delta }t}{L}}. V_{in}\begin{array}{cc} & \begin{array}{cc} & State 1 (n=1)\end{array}\end{array}\\ \left\{\begin{array}{l}{i}_L+{\displaystyle \frac{\mathsf{\Delta }t}{L}}. (V_{in}-v_C)\begin{array}{ccc} & & if i_{LP} >0 \end{array}\\ 0 \begin{array}{ccc} & & if i_{LP} \le 0\end{array}\end{array}\right.\begin{array}{cc} & State 2 (n=2)\end{array}\end{array}\right.\\ \end{array}$$

(3)

$$v_{CP}=\left\{\begin{array}{l}{v}_C+{\displaystyle \frac{\mathsf{\Delta }t}{C}}. (- {\displaystyle \frac{v_C}{R}})\begin{array}{cc} & \begin{array}{c} State 1 (n=1)\end{array}\end{array}\\ v_C+{\displaystyle \frac{\mathsf{\Delta }t}{C}}. (i_L- {\displaystyle \frac{v_C}{R}})\begin{array}{cc} & State 2 (n=2)\end{array}\end{array}\right.$$

(4)

As can be seen in Equation (3), when the predicted inductor current (i_LP) becomes negative in State 2, the predictive value is adjusted to zero, which reflects the operation of the boost converter in DCM. The cost function CF(n) is designed to minimize the error between the predicted states and the desired reference values. For the boost converter, the cost function is formulated as follows:

$$CF(n)={(i_{L,ref}- i_{LP}(n))}^2+ \lambda · {(v_{C,ref}- v_{CP}(n))}^2$$

(5)

where v_C,ref is the reference output voltage, i_L,ref is the reference inductor current, and λ is a weighting factor that balances the importance of voltage and current control. The cost function controls both the output voltage and the inductor current simultaneously to ensure optimal performance. The voltage control ensures that the output voltage meets the desired setpoint, providing stability and efficiency in the power supply. Meanwhile, the current control prevents excessive current, which could lead to component stress, thermal issues, and potential damage. By balancing these two aspects, the MPC can achieve a harmonious operation, maintaining precise voltage regulation while protecting the system from overcurrent conditions, thereby enhancing the overall reliability and lifespan of the boost converter system.

In (5), the references can be constant or variable over time. For this study, the output voltage reference is assumed to be constant, while the reference current is dynamically updated by an external circuit that includes a PI controller and a load detector, as detailed in the next section. The discrete model of the converter and the FCS-MPC algorithm are implemented on an FPGA using MATLAB HDL Coder (MATLAB R2024a). This setup enables real-time emulation within a single FPGA, simplifying the system and avoiding clock mismatch issues between the controller and the converter model simulated in real time. Thanks to HDL Coder, the entire system is translated into a VHDL code for FPGA programming via the MATLAB tool without requiring deep knowledge of VHDL programming.

3.1. Non-Minimum Phase Issue in Boost Converters

A significant challenge in controlling boost converters is their inherent non-minimum phase behavior, where the initial response of the system deviates in the opposite direction of the desired outcome. For instance, in a boost converter, attempting to increase the output voltage results in an initial undershoot in the output before the desired voltage level is attained. This is due to the gain sign changing from a negative to a positive value after an initial transient. This non-minimum phase behavior complicates the control process, particularly when using an MPC with a short prediction horizon of one, as it fails to consider the system’s long-term behavior. In such cases, controlling the output voltage by FCS-MPC can exacerbate the problem, leading to instability and performance degradation.

In a boost converter, when the controller aims to increase the output voltage from the input voltage to a higher desired level, the non-minimum phase behavior leads to an initial undershoot. The FCS-MPC controller, using a short prediction horizon, evaluates two states: State 1, where the switch is closed and the inductor stores energy, and State 2, where the switch is open and the inductor releases energy to the load. Due to the non-minimum phase behavior, the controller predicts that closing the switch will initially cause the output voltage to drop, while opening the switch will cause a slight immediate increase. To minimize immediate error, the controller opts for State 2 to avoid the undershoot. However, this prevents the inductor from storing sufficient energy to achieve the higher desired output voltage. Consequently, the controller keeps selecting State 2, avoiding the necessary energy buildup, leading to instability and preventing the output voltage from reaching the desired higher level.

Despite these challenges, MPC with a horizon of one step is often preferred due to its simplicity. The short prediction horizon reduces computational complexity, making real-time implementation feasible in mid/high-frequency applications.

3.2. Solutions to the Non-Minimum Phase Issue

To enhance controller performance, additional measures must be incorporated to handle the non-minimum phase dynamics. One approach involves modifying the cost function to include terms that anticipate the initial undershoot and adjust the control actions accordingly. Apart from that, using long-horizon FCS-MPC can solve the non-minimum phase issue; however, this is not the focus of this study for two main reasons. First, it is difficult to determine the number of horizons needed to guarantee the stability of the controller, as it would vary with each application. Gardezi et al. [12] propose a machine learning-based algorithm to provide the needed horizon in each case. The other reason is the complexity of implementing long-horizon FCS-MPC algorithms.

Recognizing the limitations of direct voltage control, the focus shifted toward regulating the inductor current to improve the system’s response. A well-known method is to use a double-loop control strategy, integrating auxiliary controllers such as PI controllers to adapt the reference current for the MPC controller based on the error in the output voltage [18,19,20]. This approach allows the MPC controller to regulate only the inductor current, thus avoiding the non-minimum phase issue.

Figure 3 shows the block diagram of such a system. While this approach addresses the non-minimum phase issue in FCS-MPC, it introduces slowness due to the PI controller’s slower timescale for setting the reference current. This lag compromises the fast dynamic response of FCS-MPC, diminishing its quick decision making and adaptability, resulting in suboptimal performance in scenarios requiring rapid adaptation and precise voltage regulation.

3.3. Delay Compensation Consideration

In control applications with larger sampling steps (typically greater than 20 µs), delay compensation methods are often necessary to mitigate the negative impact of delays on controller performance [22,23]. However, in cases where smaller sampling steps are employed, such as the 5 µs step used in this work, the effects of delays are minimal. Introducing delay compensation in such cases would unnecessarily increase the system’s complexity without providing significant improvements in response. Therefore, to maintain clarity and simplicity in the control method, no explicit delay compensation techniques are applied in this implementation. The small sampling rate and real-time operation of the FCS-MPC algorithm are sufficient to ensure the system’s high performance without the need for additional delay handling mechanisms, as will be shown in Section 5. However, the proposed dual control technique would be applied in the same way if delay compensation were implemented.

4. Proposed Dual Control Strategy Based on Load Detector and Offset Corrector

This section introduces the proposed horizon one FCS-MPC controller strategy based on the load detector and offset corrector. The proposed method consists of an FCS-MPC controller only regulating the inductor current and a reference current calculator, involving two sensors, one for measuring the load current (i_Load) and the other one for the output voltage (v_C). The method is summarized in the block diagram shown in Figure 4.

The Ideal Reference Calculator (IRC) block computes the input reference current in an ideal scenario without considering the electrical losses of the switches or other components of the system. Its calculations are based on ensuring that the steady-state power at the input (P_in = V_in · i_L,ref) equals the power at the output of the boost converter (P_out = V²_C,ref/R). Consequently, the reference current is calculated as shown in Equation (6), where R is the output load resistance.

$$i_{L,ref}={\displaystyle \frac{ {(v_{C,ref})}^2}{R · V_{in}}}$$

(6)

By modifying Equation (6) with R = v_C/i_Load, the final reference current calculation results in Equation (7):

$$i_{L,ref}={\displaystyle \frac{ {(v_{C,ref})}^2· i_{Load}}{v_C · V_{in}}}$$

(7)

The calculated reference current is derived from ideal equations, which do not account for electrical losses and variations in component values due to inaccurate measurements or external factors such as temperature. These losses are especially unpredictable in conventional FCS-MPC, which does not control the switching frequency precisely, making real-time loss prediction challenging. To correct minor steady-state errors in the calculated reference current, the proposed dual control strategy for a DC-DC boost converter includes an offset tuning mechanism. The process begins by measuring the actual output voltage and comparing it with the reference output voltage. The difference between these two values represents the voltage error, which is then fed into a low-speed PI controller.

As shown in the flowchart in Figure 5, the control system is designed using a dual-loop configuration. The outer loop features a PI controller, which adjusts an offset based on the accumulated error between the actual and reference output voltages. This offset is added to the ideal reference current generated by the IRC block, which operates under ideal conditions and without delay. This setup ensures that the system compensates for minor deviations not accounted for by (7). The IRC block provides the primary reference current for the FCS-MPC, which can track this reference quickly due to its fast response capabilities. While the FCS-MPC ensures the rapid tracking of the reference current and real-time system adjustments, the IRC block itself is based on ideal conditions. To account for any steady-state errors in the output voltage caused by non-ideal factors, a slower offset tuner, managed by the PI controller, is used. The FCS-MPC handles the direct control of the inductor current by predicting future system states (using Equations (3) and (4)), evaluating possible switching actions (Equation (5)), and selecting the optimal action to minimize the cost function. This approach allows the FCS-MPC to quickly adapt to load changes detected by the IRC block. By decoupling the dynamic regulation from the PI controller, the FCS-MPC is fully responsible for fast real-time adjustments of the inductor current, without being slowed by the PI loop’s response. This combination allows the system to maintain fast dynamic responses while ensuring accurate steady-state performance.

Since the first loop generates the reference current, the second loop (FCS-MPC) only focuses on controlling the current, not the voltage. In fact, the voltage is controlled by the first loop. Therefore, the cost function of the FCS-MPC algorithm is simplified from (5) to the following:

$$CF(n)={(i_{L,ref}- i_{LP}(n))}^2$$

(8)

This eliminates the need for tuning the parameter λ, which is removed from the algorithm. Regarding the PI controller in the first loop, it can be designed with any classical techniques, such as Ziegler–Nichols tuning method, since its role is the standard one of adapting the reference current to control the output voltage. Given that the main component of the reference current is calculated by the IRC, which operates with fast dynamics, the PI controller plays a secondary role, handling only minor steady-state discrepancies. This allows for increasing the phase and gain margins without compromising the system’s dynamics. By increasing the phase and gain margins of the PI controller, the system becomes more robust, allowing for greater tolerance to variations in system parameters without compromising performance. Therefore, a fine-tuning method is used in this study to determine the proportional and integral gains. This fine-tuning is justified because the PI controller has a low-speed response, which leaves large phase and gain margins.

This dual approach optimizes the overall performance of the control system in both transient and steady-state conditions. However, a drawback of this method is the need for an extra sensor to measure the load current when the load is not known, which adds complexity and cost to the system. In the absence of a physical load sensor, observer-based methods offer an alternative for load current estimation, though they may introduce noise-related issues. Talbi et al. [24] demonstrated the effectiveness of an adaptive sliding mode observer (ASMO) for the sensorless control of DC-DC boost converters. The ASMO accurately estimated load resistance and output voltage using the system’s mathematical model, maintaining the controller performance even under load variations. However, this method can be sensitive to noise, which might affect the accuracy of the estimations, particularly in systems with a high switching frequency. Similarly, Heydari-doostabad and Ghazi [25] proposed a Luenberger observer for load current estimation in UPS systems, which replaces sensors with model-based estimations of the load current. While the Luenberger observer improves system reliability and reduces complexity, it is also prone to noise issues, especially during sudden load changes or in non-linear conditions. These observer-based approaches could be integrated into the proposed algorithm to estimate the load current without a dedicated load sensor, though noise mitigation strategies should be considered to ensure precise control and system performance, making the whole system more complex.

5. Results

This section presents simulation and experimental results validating the proposed method for addressing the non-minimum phase issue in the short-horizon FCS-MPC applied to a boost converter. The simulation setup is conducted on the MATLAB/Simulink platform, where the boost converter model and FCS-MPC algorithm are implemented and tested under various operating conditions to evaluate the performance of the proposed method. Scenarios with different load changes and input voltage variations are included to assess the controller’s ability to handle non-minimum phase behavior and maintain stable output voltage. Apart from the simulation verification, experimental tests are performed by implementing the proposed algorithm inside an FPGA board, specifically the Arty Z7, which is equipped with an XC7Z020-1CLG400C FPGA (AMD, Santa Clara, CA, USA). This FPGA-based implementation enables real-time control and testing, with the controller and the boost converter’s discretized model integrated into the same FPGA, ensuring synchronized operation and eliminating clock mismatch issues.

5.1. Simulation Results

Both simulation and experimental tests use the parameters in

Table 2. Parameter values used in the simulation and experimental tests.

Parameters	Symbol	Value	Unit
Input voltage	Vin	40	V
Output voltage reference	vC,ref	60	V
Inductor current reference	iL,ref	1.99	A
Load resistance	R1	45	Ω
Load resistance	R2	22.5	Ω
Capacitance	C	32	µF
Inductance	L	0.5	mH
Sampling time	∆t	5	µs

to validate the effectiveness of the proposed method and ensure consistency between the results. A 5 µs sampling step is used, which is smaller than the state-of-the-art sampling steps. Although the proposed method can achieve even smaller sampling steps, down to 50 ns, the 5 µs step is selected due to the limitations in the commutation frequency of power electronic switches. Achieving small sampling steps in FCS-MPC is crucial, as it allows for faster and more precise control, improving the dynamic response and stability of the system. Additionally, in high-frequency applications, reaching small sampling steps is necessary to accurately track and respond to rapid changes in the system.

Initially, the non-minimum phase issue in a traditional FCS-MPC algorithm is illustrated in Figure 6. In this test, the initial capacitor voltage is set to 40 V, i.e., the same as the input voltage, to focus on the behavior of the controller when it starts to reach an output voltage greater than the input. As can be seen, instead of closing the switch, the controller erroneously opens it (switch Q is off), preventing the output voltage from reaching the desired 60 V reference. This incorrect action is a direct consequence of the non-minimum phase behavior, where the system’s immediate response to the control action is opposite to the desired effect. Consequently, the output voltage fails to reach the target of 60 V, as shown in Figure 6.

Figure 7 illustrates the performance of the control strategy presented in Section 3.1 that uses a PI controller to calculate the reference current [18,19,20]. This hybrid approach contrasts with the proposal of this paper, highlighting the differences in response and performance. In this approach, the PI controller adjusts the reference current based on the output voltage error, and the FCS-MPC is used to control the inductor current. As shown in the figure, when the load resistance changes from R1 = 45 Ω to R2 = 22.5 Ω at 0.1 s, there is a noticeable voltage drop up to 25% with a settling time of 20 ms. This drop occurs because the PI controller’s slower dynamic response introduces a delay in adjusting the reference current to match the new load conditions. Consequently, the system takes longer to stabilize and return the output voltage to the desired level, affecting the overall speed and efficiency of the control system.

The aim of this study is to integrate a PI controller for correcting offset in steady-state performance, along with a sensor to measure load current and adjust the reference current according to Equation (7). To understand the role of the offset corrector block, the first simulation is conducted without incorporating this block, serving as a proof for verification of the IRC block. In this test, the controller updates the reference current without incorporating the offset corrector block. When subjected to a step change in the load, as shown in Figure 8, this method demonstrates an improved dynamic response. The system exhibits a significantly reduced undershoot in the output voltage and a much faster settling time compared to previous approaches. Specifically, the undershoot is limited to 3%, and the settling time is reduced to 4 ms. However, due to parasitic impedances, the system still shows a slight steady-state error, with the output voltage settling at 59 V instead of the targeted 60 V. In hardware tests, this error can be even more significant due to inaccuracies in the prediction model or discrepancies between the real parameters and those used for calculating the reference current (Equation (7)).

The proposed method combines the advantages of immediate inductor current control using Equation (7) with the steady-state stability provided by the PI controller used for the fine-tuning of the reference current, ensuring accurate and fast reference current adjustments. The IRC block ensures that the power input equals the power output under ideal conditions, while the PI regulator addresses any deviations caused by non-ideal components and external factors.

The simulation results, as depicted in Figure 9, demonstrate that the proposed method is faster than the one presented in [18,19,20]. The system effectively mitigates the non-minimum phase problem inherent in FCS-MPC applications. It maintains the desired output voltage of 60 V without deviation and quick recovery from load changes. Specifically, the system shows a settling time of 2 ms and an undershoot of 3.2%. Additionally, there is no offset error, and the method remains fast, as the PI controller is only involved for offset correction, not in the reference current calculation block. The presence of sub-harmonic oscillations in the results can be attributed to the low temporal resolution associated with a sampling step of 5 µs. Future work will explore the potential for improvement by reducing the sampling step.

In addition to the load resistor change results, two further simulations were conducted to validate the feasibility and robustness of the proposed converter under different dynamic conditions. The first simulation focuses on the startup behavior of the converter. As shown in Figure 10, the inductor current quickly increases to charge the capacitor to the desired voltage level of 60 V. The output voltage reaches its reference value within 3.5 ms with a small overshoot, demonstrating the effectiveness of the proposed control strategy in managing the initial charging process and achieving fast settling with minimal transient effects.

The second simulation illustrates the system’s response to an output voltage reference change, as depicted in Figure 11. At t = 0.1 s, a step-up change is applied to the output voltage reference, increasing it from 60 V to 80 V. Initially, the output voltage briefly decreases due to the non-minimum phase characteristic of the system, before it increases to reach the new reference value. The inductor current responds to the step change much faster, as seen in the simulation results. However, the dynamics of the boost converter cause the output voltage to respond more slowly. Despite this, the transition occurs without any significant overshoot, and the transient lasts for about 5 ms. This behavior demonstrates the ability of the proposed dual control strategy to handle non-minimum phase behavior while maintaining stable and accurate voltage regulation.

It is important to note that while the FCS-MPC algorithm can operate in both CCM and DCM, it faces specific challenges in DCM. This is because the cost function tends to favor maintaining the zero-current state, particularly under light load conditions, which can lead to the system remaining in this state longer than desired. As a result, the inductor current will not increase when needed, impacting voltage regulation. This issue is unique to conventional FCS-MPC, as other methods like CCS-MPC or those with fixed switching frequencies [16] do not encounter this problem. The focus of the work is on the combination of conventional FCS-MPCs with the IRC block and the offset tuner to mitigate the non-minimum phase issue. However, the limitations in DCM performance related to the FCS-MPC algorithm remain, and addressing these challenges is the focus of ongoing research aimed at improving future implementations. To address this issue, the possible solution under development involves modifying the cost function to focus on average values over a longer period, rather than relying solely on instantaneous values.

5.2. Experimental Results in FPGA

To validate the effectiveness of the proposed control strategy in a practical setting, FPGA-based experimental tests are conducted using the same parameters as in the simulation section. The experimental setup is illustrated in Figure 12, showing the Arty Z7 FPGA board connected to a PC for data acquisition and control implementation. The FPGA is programmed using HDL code generated from MATLAB HDL Coder. The FPGA implementation includes an Integrated Logic Analyzer (ILA) block to monitor internal signals, facilitating debugging and the validation of the control strategy. Notably, the tests utilize hardware-in-the-loop (HIL) techniques, with the entire system implemented within a single FPGA. This approach mitigates communication issues between the controller and converter model, and prevents clock mismatch problems, simplifying the hardware setup and reducing overall system complexity and cost.

The experimental results obtained using the Integrated Logic Analyzer (ILA) are depicted in Figure 13, illustrating the controller’s performance. In this test, the performance of the controller is evaluated by implementing a real-time model of the boost converter in the same FPGA. It is notable that the ILA records signals in integer form, necessitating that each signal amplitude be divided by $2^F$, where F represents the number of fractional bits defined in MATLAB HDL Coder. Additionally, each sample in the ILA corresponds to 8 ns, reflecting the internal clock period of the Arty Z7 FPGA board.

Due to the difficulty in discerning the details of the signals directly from the ILA, the data are extracted in .csv format and subsequently plotted in MATLAB, providing a clearer visualization of the results, as seen in Figure 13. Figure 13 demonstrates that the output voltage closely reaches the target of 60 V, exhibiting no deviation and a stable response. The ripple in the output voltage can be decreased by reducing the sampling step of the controller, depending on the practical limitations of the converter and the power rate. Additionally, the inductor current is maintained around 2 A, ensuring adequate power to sustain the output voltage at the desired 60 V. This precise current control enables the system to effectively adapt to the initial load of 45 Ω. Despite the clarity of steady-state performance, this figure does not capture the dynamic behavior of the controller, as it emphasizes steady-state rather than transient responses.

Figure 14 illustrates the performance of the controller under a step change in load resistance, where the load resistance is varied from 45 Ω to 22.5 Ω. This step change test further validates the proposed method’s capability to handle dynamic load variations. The output voltage remains stable at 60 V, with the inductor current adapting smoothly to the new load conditions. Notably, the undershoot in the voltage is about 3.3% similar to the simulation test, and the output voltage is restored to around 60 V in less than 4 ms. These experimental results closely match the simulation results shown in Figure 9, demonstrating the effectiveness of the controller in minimizing transient deviations and quickly stabilizing the output during sudden changes in load.

As shown in this section, the system response is consistent with simulation results, exhibiting a negligible undershoot and rapid settling time. This approach shows great potential for applications requiring precise voltage regulation and adaptability to changing load conditions. Moreover, it can be applied to any topology where the non-minimum phase issue makes it difficult to use horizon one FCS-MPC, enhancing control performance and stability. Future work will focus on optimizing the control algorithm and exploring its application to more complex power electronic systems.

The experimental results have shown the correct behavior of the controller with a passive load. To further validate the robustness of the proposed controller, additional results with an active load are included. Figure 15 illustrates the behavior of the proposed control method when applied to a boost converter connected to a single-phase H-bridge inverter, which powers a resistive-inductive (R-L) load (20 Ω and 20 mH) on the AC side. The H-bridge is controlled by a sinusoidal PWM modulator to provide a sinusoidal voltage waveform with an amplitude of 30 V. The controller maintains the input DC link voltage of the H-bridge around 60 V while effectively handling active loads, such as the inverter with a DC bus. Unlike passive resistor loads, the system dynamically adjusts the reference current to maintain the desired voltage across the DC link while compensating for the inductive effects on the load side. The 100 Hz component in the inductor current, shown in Figure 15, results from the AC-side power demand, where the H-bridge inverter converts the DC link voltage into a single-phase AC output. Since the output power is sinusoidal, corresponding to the AC-side frequency, the inductor current in the boost converter—responsible for supplying power to the inverter—also contains this 100 Hz frequency component. This occurs because the inductor current fluctuates to meet the alternating power demand of the R-L load on the AC side. While the DC link voltage remains steady at around 60 V, the current drawn by the inductor mirrors the sinusoidal nature of the load’s power consumption, oscillating at twice the AC mains frequency (100 Hz).

Figure 16 presents the experimental comparison of the capacitor voltage (a) and inductor current (b) between the proposed method and the PI-based MPC method from references [18,19,20], with results obtained using the ILA. In both cases, a sampling step of 5 µs is used. The system response to a step load change from 45 Ω to 22.5 Ω is shown. The proposed method demonstrates a significantly faster response, with the capacitor voltage stabilizing more quickly and with smaller overshoot, while the PI-based MPC method shows slower recovery. Similarly, the inductor current in the proposed method settles much faster than in the PI-based MPC approach, highlighting its superior dynamic performance. These experimental results closely match the simulation results previously obtained, confirming the proposed method’s performance in achieving faster voltage and current regulation during sudden load changes.

5.3. Discussion and Potential Applications

The proposed dual control strategy effectively addresses the non-minimum phase behavior in horizon-1 FCS-MPC for DC-DC boost converters by integrating a PI-based reference current offset tuner. In conventional PI-MPC methods, the PI controller is directly involved in generating the reference current and managing both dynamic and steady-state transitions, which often limits the fast response capabilities of the MPC due to the slower reaction time of the PI controller. In contrast, the proposed method decouples the roles of the PI controller and the FCS-MPC. The PI controller is only responsible for correcting small steady-state errors, while the FCS-MPC handles all fast dynamic responses, resulting in improved stability and faster voltage regulation without limiting the use of short-horizon FCS-MPC, even in applications with non-minimum phase issues. Moreover, the flexibility of the MPC control makes it applicable to a wide range of power electronic systems facing similar non-minimum phase challenges.

Table 3. Comparison of MPC-based control methods for boost converters.

Method	Response Time	Sensor/Observer	Complexity	Sampling Step
Long-Horizon FCS-MPC [26]	Fast	No	High	100 µs
Adaptive-Horizon FCS-MPC [12]	Fast	No	Very high	10 µs
PI-MPC [18,19,20]	Slow (20 ms)	No	Low	50, 12.5, 10 µs
Proposed Dual Control [PI + FCS]	Fast (2 ms)	Yes	Low	1 and 5 µs

summarizes the key performance characteristics of the proposed dual control strategy (PI + FCS-MPC) compared with other control methods such as Long-Horizon FCS-MPC [26], Adaptive-Horizon FCS-MPC [12], and conventional PI-MPC [18,19,20]. The comparison includes factors such as response time, the need for sensors or observers, system complexity, and the sampling step. The Long-Horizon FCS-MPC [26] offers a fast response but comes with significantly higher complexity due to the longer prediction horizon. Its ability to handle non-minimum phase behavior depends on the converter dynamics and the number of horizons considered, but it does not require observers or any extra sensors for detecting the load. The Adaptive-Horizon FCS-MPC [12] also provides a fast response. However, it demands very high complexity for implementation without requiring additional sensors. The PI-MPC method shows a slower response due to the nature of the PI control in comparison with Long/Adaptive-Horizon FCS-MPC. This method introduces low algorithm complexity without the need for additional sensors or observers. The proposed dual control strategy (PI + FCS-MPC) achieves a fast response time, similar to both long/adaptive-Horizon FCS-MPC, due to the isolation of the proposed PI controller from the dynamic response of the converter. The steady-state error is similar to other methods thanks to the offset tuning method. It effectively handles non-minimum phase behavior with relatively low complexity and achieves high performance with the additional help of a sensor or observer for correcting the reference current.

In FCS-MPC, reducing the sampling step has been shown to significantly improve controller performance. The proposed method’s 5 µs sampling rate offers precise and rapid control, especially when compared to the 10 µs step used in the adaptive-horizon method by Gardezi et al. [12] and the much longer 100 µs step in the long-horizon approach by Zafra et al. [26]. While the proposed method can achieve sampling steps as low as 100 ns, such high-frequency sampling introduces the risk of damaging power electronic switches due to the limited maximum switching frequency. To prevent this, applying a switching frequency control method, such as the Period Control Approach (PCA), is essential [27,28]. However, the focus of this paper is on the proposed control strategy rather than the impact of calculation resolution on switch performance. As demonstrated in Figure 17, reducing the sampling step from 5 µs to 1 µs leads to greater precision, effectively mitigating the low-frequency subharmonics observed in earlier tests with the sampling step of 5 µs. The smaller sampling period allows for more frequent updates to control inputs, improving prediction accuracy and reducing oscillations in the control response.

The correlation between the sampling step and harmonics spectrum is clearly illustrated in the spectra of the inductor current and output voltage in Figure 18. As shown in the subfigures, the amplitude of subharmonics is significantly larger when a sampling step of 5 µs is used compared to 1 µs. Increasing the Ts results in additional low-frequency subharmonics that may negatively affect system stability and performance. The maximum achievable switching frequency ($f_{sw,\max }$) is determined by the relationship given by (9); therefore, with Ts set to 5 µs, the $f_{sw,\max }$ is limited to 100 kHz. However, in this application, switching generally follows a pattern of one on-cycle followed by two off-cycles, a behavior attributed to the differing slopes of increasing and decreasing current, as described by (3). This results in a more commonly observed switching frequency of approximately 1/(3·Ts). Consequently, with Ts = 5 μs, the main harmonic appears at 67 kHz (displayed as 68 kHz due to resolution limitations), while reducing Ts to 1 µs shifts this primary harmonic to around 333 kHz (observed as 342 kHz). This shift to higher frequencies with reduced Ts allows for more effective filtering by the converter, enhancing performance by mitigating low-frequency subharmonics and stabilizing the system.

$$f_{sw,\max }={\displaystyle \frac{1}{2 · T_s}}$$

(9)

The integration of the MPC controller with a PI-based reference current offset tuner provides a versatile control mechanism that can be adapted to any non-minimum phase power converter. In such cases, the MPC controller may help simplify the regulator implementation, particularly when compared to linear controllers like PI or PID. This would be the case for boost-derived topologies, such as the buck-boost, four-switch buck-boost, Cuk, SEPIC, or ZETA converters, which are frequently used in low-power battery chargers (below 100 W). These converters, especially the Cuk topology, benefit from inherent current ripple reduction on one of their ports, making them ideal candidates for this control approach.

The extension to AC-DC single-phase active rectifiers would also offer potential advantages over traditional controllers, reducing the complexity of implementation. For example, flyback, flyboost [29], or boost AC-DC power factor correctors [30] could benefit from the MPC strategy. Additionally, some applications impose non-linear behaviors in the control stage, as seen in quadratic boost power converters [31], coupled inductor boost-derived topologies [32,33], Maximum Power Tracking strategies for photovoltaic panels [34], multi-port boost converters [35], or partially saturated inductor boost converters [36,37]. These non-linearities add complexity to the control stage beyond voltage or current regulation. In these cases, the proposed strategy could simplify implementation and reduce computational burdens compared to linear regulators.

6. Conclusions

This study presents a significant advancement in the control of DC-DC boost converters by effectively addressing the non-minimum phase behavior, a common challenge in such systems. The main contribution of this work is to examine the limitations of utilizing horizon-one FCS-MPC exhibiting non-minimum phase behavior and to propose a solution that addresses these issues without extending the prediction horizon. Unlike traditional PI-MPC approaches, where the PI controller manages both dynamic and steady-state transitions, the proposed method separates these roles. The FCS-MPC is solely responsible for a fast dynamic response, while the PI controller is only tasked with fine-tuning the reference current calculated by the IRC block, ensuring steady-state accuracy. This decoupling enables the system to handle dynamic load changes more efficiently and maintain high-speed operation, as the PI controller does not interfere with the fast responses of the FCS-MPC.

Simulation results show that the system effectively mitigates the non-minimum phase issue, maintaining the desired output voltage with minimal deviation and quick recovery from load changes. The method’s practical viability is demonstrated through comprehensive simulation and HIL experimental tests, showcasing its ability to handle real-world conditions effectively. In particular, the smaller sampling step (5 µs) achieved in this study significantly contributes to the faster response of the system compared to other FCS-MPC methods. Notably, in the HIL tests, both the controller and the converter’s discretized model are implemented inside the same FPGA. This integration eliminates clock mismatch issues and negates the need for additional blocks such as ADCs for interfacing between these components, thus simplifying the experimental setup.

The steady-state error is comparable to long-horizon FCS-MPC and conventional PI-MPC methods, but smaller compared to short-horizon FCS-MPC thanks to the offset tuning mechanism employed. With a negligible undershoot and rapid settling time, the system is suitable for industrial applications requiring precise voltage regulation and adaptability to changing load conditions. Furthermore, the proposed dual control strategy can be extended to other power electronic systems facing non-minimum phase issues, broadening its applicability. Future work will focus on optimizing the control algorithm and exploring its application to more complex power electronic systems.