Fabrication of Thermally Evaporated CuI_x Thin Films and Their Characteristics for Solar Cell Applications

Abstract

Carrier-selective contacts (CSCs) for high-efficiency heterojunction solar cells have been widely studied due to their advantages of processing at relatively low temperatures and simple fabrication processes. Transition metal oxide (TMO) (e.g., molybdenum oxide, vanadium oxide, and tungsten oxide) thin films are widely used as hole-selective contacts (HSCs, required work function for Si solar cells > 5.0 eV). However, when TMO thin films are used, difficulties are faced in uniform deposition. In this study, we fabricated a copper (I) iodide (CuI) thin film (work function > 5.0 eV) that remained relatively stable during atmospheric exposure compared with TMO thin films and employed it as an HSC layer in an n-type Si solar cell. To facilitate efficient hole collection, we conducted iodine annealing at temperatures of 100–180 °C to enhance the film’s electrical characteristics (carrier density and carrier mobility). Subsequently, we fabricated CSC Si solar cells using the annealed CuI_x layer, which achieved an efficiency of 6.42%.

1. Introduction

The best efficiency in the field of Si solar cells is usually achieved with n-type Si solar cells [1]. Carrier-selective contact (CSC) solar cells are one such high-efficiency option that utilizes n-type silicon. Ongoing research is being performed to explore the applications of various metal compounds [2]. High optical gains can be achieved using highly transparent and wide-bandgap semiconductor materials, such as molybdenum oxide (MoO_x) [3,4,5,6,7,8], vanadium oxide (VO_x) [4,7,9], tungsten oxide (WO_x) [4,7,10] and lithium fluoride (LiF_x) [8]. These materials exhibit distinctive p- or n-type characteristics and possess wide-ranging work functions, varying from 2 to 7 eV. These transition metal oxides (TMOs) (e.g., MoOx, VOx, and WOx) function as hole-selective contact (HSC) layers due to their electronic properties and large work functions (ΦTMO > 5.0 eV). When their Fermi levels align with that of n-Si (ΦSi ≈ 4.2 eV), a potential barrier (band bending) is induced [2,4]. Consequently, silicon solar cells incorporating such hole transport layers are referred to as CSC silicon solar cells. Copper (I) iodide (CuI), with a wide bandgap of 3.1 eV, exhibits three crystalline phases: α (above 392 °C), β (between 350 and 395 °C), and γ (below 350 °C) [11,12,13,14]. Among these, γ-CuI, which has a zinc blende (cubic) structure, functions as an HSC layer. It has been studied using various techniques, including spin coating [13,15,16], electrodeposition [17], chemical bath deposition [15], solution method [12,14,15,18,19], pulsed laser deposition [15,20,21] and thermal evaporation [11,14,15,22]. Considering previous results, pulsed laser deposition and thermal evaporation demonstrate superior properties for CuI_x thin films, such as high transmittance and low resistivity [11,20,21,22]. In addition, compared to TMO thin films, γ-CuI thin films show excellent stability in the atmosphere and do not undergo degradation. With these films, the hole concentration can be easily controlled through iodization at a temperature of 200 °C or lower [23,24]. Copper iodide exhibits changes in its electrical properties with variations in its composition ratio. With copper-poor and iodine-rich composition, the formation energy of the copper vacancy (V_cu) is lower than that with a copper-rich and iodine-poor composition. This lower formation energy allows for more holes to be generated at the valence band maximum through the thermal excitation of an electron to the defect (with energy ∼k_BT), thereby increasing conductivity. This also indicates that such p-type defects create delocalized charge density, facilitating high charge carrier mobility without an energetic barrier for the formation of localized charge density. [12,14] Moreover, the iodine vacancy (V_i) functions as a trap state and scatters holes, which can compensate for the acceptor, thereby reducing hole density and degrading hole transport properties accordingly [14].

LiF_x thin film and other similar alkali/alkaline earth compound (MgF_x, KF_x, and Cs₂CO₃) thin films have recently attracted attention as electron-selective contacts (ESCs) for n-Si solar cells [8,25,26,27]. With their insulating nature and very large bandgap energy exceeding 10 eV, these materials act as work function modifiers for the overlying metal (e.g., Al–LiF_x contact). An Al–LiFx contact decreases the metal work function by forming an interface dipole [28]. Consequently, the Schottky barrier between c-Si and the metal is either eliminated or becomes negative (i.e., n+ accumulation layers form), facilitating electron tunneling with extremely low contact resistivity in the order of 10¹ mΩ⋅cm². Comparable contact characteristics have also been documented for low-work-function alkali metals in indirect contact with passivation layers, such as Mg–a-Si:H (with ΦMg approximately 3.7 eV) [29] and Ca–TiO₂ (with ΦCa approximately 2.9 eV) [30]. This suggests a parallel mechanism in contact formation.

In this study, we aimed to fabricate a CuI_x layer with Φ > 5.0 eV and improve its electrical properties through iodization annealing. This CuI_x layer functions as an HSC layer when applied to n-type Si as a p-type semiconductor. The improved electrical properties (carrier density and carrier mobility) achieved through iodization annealing are expected to enhance the performance of CSC Si solar cells.

2. Experimental Procedure

2.1. Deposition of CuI_x Layers

Powder sources for CuI (Alfa Aesar, copper (I) iodide, 99.998%) were prepared for layer deposition. The CuI_x layers were deposited on three types of substrates. First, double-side-polished 280 µm n-type float-zone Si (~3 Ωcm, 100 orientation) wafers were immersed in a standard RCA process solution and 10% hydrofluoric acid solution for 1 min to remove native SiO₂. After cleaning, the CuI_x layers were deposited on a cleaned silicon wafer for morphological and work function measurements. Second, the double-side-polished 280 µm n-type wafers were etched in potassium hydroxide to obtain a random-pyramid surface texture. After chemical cleaning, the wafers were immersed in 10% hydrofluoric acid for 1 min to remove native SiO₂, followed by hydrated intrinsic amorphous silicon (a-Si:H(i)) thin film (~8 nm) deposition using plasma-enhanced chemical vapor deposition on both sides of the wafer for interface passivation. Thereafter, the CuI_x layers were deposited on the samples for solar cell fabrication. Finally, soda-lime glass substrates were cleaned ultrasonically with acetone, ethyl alcohol, and deionized water sequentially for 15 min each. Subsequently, the CuI_x layers were deposited on cleaned soda-lime glass for optical and sheet resistance measurements. The films were deposited by vacuum thermal evaporation from a tantalum boat at <6.7 × 10⁻⁴ Pa, which is a simple deposition process. The thickness up to which the deposition took place in these CuI_x layers was 40 nm considering the surface uniformity and transmittance of these films from previous results [31].

2.2. Iodization Annealing

Iodization annealing of the prepared CuI_x layers was performed using rapid thermal processing. The process was carried out within the graphite box and was performed for 10 min at 100–180 °C under N₂ gas condition (~6.67 × 10 Pa, base vacuum ≈ 5.0 × 10⁻³ Pa) with iodine metallic powder (0.2 g, 99.99% pure). The internal volume of the graphite box was approximately 64 cm³. The substrate with the deposited CuI_x layer and the iodine metallic powder were placed inside the graphite box without contact. The entire iodine metallic powder was confirmed to have evaporated after annealing.

2.3. Solar Cell Fabrication

The iodization-annealed CuI_x layers with various temperatures were applied as HSC layers in a front-side full-area configuration, and a LiF_x thin film was applied as an ESC layer in a rear-side full-area configuration, as shown in the solar cell structures in Figure 1. The LiF_x thin films were then deposited on the rear side of the Si substrate with an ESC layer using a thermal evaporation system. The details have been previously described, and LiF_x thin films were deposited at an optimized thickness of ~4 nm. Then, the aluminum metal contact was deposited at 1 μm thickness [32]. The aluminum rear contact was pre-deposited to serve as a capping layer and prevent the rear side pass of iodine during iodization annealing. Subsequently, indium tin oxide (ITO) layers were deposited on the front side using a radio frequency-magnetron sputtering system. The ITO layers were deposited under the process conditions of base vacuum (~6.7 × 10⁻⁴ Pa), working pressure (argon condition, ~1.33 × 10⁻¹ Pa) and RF power of 100 W (four-inch target). Thereafter, the metallic front electrodes were deposited with Ag metal using a thermal evaporation system at 1 μm thickness. The area of the CSC Si solar cell with the iodization-annealed CuI_x layer applied was 0.34 cm².

2.4. Analysis

The morphologies were observed via field-emission transmission electron microscopy (FE-TEM, JEM-2100F, JEOL, Akishima, Tokyo, Japan; sample preparation using focused ion beam method) at 200 kV and field-emission scanning electron microscopy (FE-SEM, JSM-6701F, JEOL, Akishima, Tokyo, Japan) at 10 kV. The sample preparation for FE-TEM was performed following a standard focused ion beam technique, and the thinning step for the sample was performed with a decreasing beam current to mitigate sample damage and improve the sputtering of the platinum target. The optical transmittance was determined through ultraviolet-visible spectroscopy (V-670, Jasco, Hachioji, Tokyo, Japan). To investigate the composition ratio and binding energy of the CuI_x layer, X-ray photoelectron spectroscopy (XPS, K-ALPAH+, Thermo Fisher Scientific, Waltham, MA, USA) was utilized. The electrical properties were measured using a Hall effect measurement system (M/N #7707_LVWR, Lake Shore Cryotronics, Westerville, OH, USA) with the van der Pauw configuration at room temperature. The current–voltage (I–V) measurement for the CuI_x films was conducted by depositing Au–Ni metal on a CuI_x–n-Si substrate for ohmic contacts. Au–Ni was deposited with masks placed over the CuI_x layer using thermal and e-beam evaporators (base vacuum ≈ 6.7 × 10⁻⁴ Pa). The surface work function was measured based on the contact potential difference method using a Kelvin probe (ASKP200200, KP technology, Wick, Caithness, UK) with a platinum probe tip (4.78 eV). Subrahmanyam and Kumar have described the relevant instrument setup and measurement techniques [33]. The effective minority carrier lifetime was determined through transient photoconductance measurements (WCT-120, Sinton Instruments, Boulder, CO, USA). The I–V parameter of the solar cell was measured under an AM 1.5 G solar spectrum at 25 °C using a solar simulator (WXS-155S-L2, Wacom, Fukaya, Saitama, Japan).

3. Results and Discussion

3.1. Improvement in Properties of CuI_x Layers with Iodization Annealing

The iodization annealing was performed to control and improve the properties of the CuI_x layers, and a detailed investigation of the layers was necessary to determine the effects of the composition ratio. Figure 2 shows the Cu 2p (a) and I 3d (b) XPS spectra for the CuI_x layers with increasing iodization-annealing temperature. No additional peaks were observed in the survey spectra compared with the reported XPS data of CuI_x layers, indicating that the films were in the pure phase [18,34]. Figure 2a shows that when the iodization-annealing temperature dropped below 100 °C, the peaks located at 932.5 eV and 952.5 eV were mainly consistent with Cu 2p_1/2 and Cu 2p_3/2, respectively. In addition, the peaks of Cu 2p_1/2 and Cu 2p_3/2 shifted to 931.5 eV and 951.5 eV, respectively, when the iodization-annealing temperature increased beyond 120 °C. Figure 2b shows that when the iodization-annealing temperature dropped below 100 °C. The peaks located at 620 eV and 631.5 eV were mainly consistent with I 3d_5/2 and I 3d_3/2, respectively. In addition, the peaks of I 3d_5/2 and I 3d_3/2 shifted to 619 eV and 630.5 eV, respectively, when the iodization-annealing temperature increased beyond 120 °C. The peak position shifted to a slightly lower binding energy when the iodization-annealing temperature exceeded 120 °C, indicating the iodization-induced formation of V_cu. Shifts to lower binding energies are generally associated with cation vacancies [34,35].

Table 1. Composition ratio of 40 nm CuI_x layers according to iodization-annealing temperature (quantitative XPS analysis).

	I/Cu (at %)
As deposited	0.916
100 °C N2	0.957
120 °C N2	1.001
140 °C N2	1.067
160 °C N2	1.032
180 °C N2	1.036

shows the composition ratio of the CuI_x layer as a function of the iodization-annealing temperature. The proportion of copper in the as-deposited condition and under 100 °C annealing was higher than that of iodine. However, at iodization-annealing temperatures above 120 °C, the iodine proportion exceeded that of copper. This ratio change is further explained by the Cu 2p and I 3d peaks in the XPS spectra shifting to lower binding energies.

Figure 3 shows the as-deposited c-Si/a-Si:H(i)/CuI_x interfaces. As seen in the TEM images, the a-Si:H(i) thin film and the CuI_x layer appeared to be ~7.8 nm thick and ~40 nm thick, respectively. No defects were observed in the TEM image.

Figure 4 shows the electrical characteristics of the CuI_x layers after iodization annealing. They demonstrated the best electrical properties at the iodization-annealing temperature of 140 °C. The hole density was 6.84 × 10¹⁹ cm⁻³, and the hall mobility of the hole was 8.2 cm²V⁻¹s⁻¹. The hole density increased as the iodization-annealing temperature increased to 140 °C, following which it tended to decrease. Moreover, the Hall mobility continued to increase with an increase in the annealing temperature. The sheet resistance of the iodization-annealed CuI_x layers tended to decrease to 3.54 kΩsq⁻¹ as the iodization-annealing temperature increased to 140 °C. Thereafter, it increased to 13.9 kΩsq⁻¹. The results showed a significant improvement in electrical properties, fulfilling the experimental goal of inducing V_cu formation through iodization annealing [12,14].

Figure 5a shows the transmittance plot in the 300–1100 nm range, corresponding to CuI_x layers with various iodization-annealing temperatures. The CuI_x layers exhibited transmittance values of 86.23–58.80% in the visible region (400–700 nm). Further, the transmittance tended to decrease with increasing annealing temperature, which is consistent with observations from previous studies [36,37]. As seen in Figure 5b, the bandgap energy of the annealed CuI_x layers ranged from 2.97 eV to 3.00 eV, showing no discernible trend with respect to the iodization-annealing temperature. The optical band energies were calculated using a Tauc plot, as follows:

$$\alpha ={\displaystyle \frac{1}{t}}\mathit{ln}[{\displaystyle \frac{{(1-R)}^2}{T}}],$$

(1)

where $\alpha$ is absorption coefficient, calculated as:

$$({\alpha hv)}^2=\beta (hv-E_g),$$

(2)

where t is the film thickness, T is the transmittance, and R is the reflectance, which can be neglected (R < 1). β is a constant called the band-tailing parameter.

Figure 6 shows the effective minority carrier lifetime (τ_eff) and illustrates the variation in the characteristics of the CuI_x–a-Si:H–n-Si structure with the iodization-annealing temperature. Before annealing, τ_eff was 1.5 ms, but as the iodization temperature increased, τ_eff gradually decreased, reaching 864 μs at 180 °C (at a carrier injection level of 5 × 10¹⁴ cm⁻³). The interfacial properties of the fabricated sample tended to degrade with increasing iodization-annealing temperature. This is because the passivation quality of the intrinsic amorphous silicon layer deposited for surface passivation of the n-type silicon substrate tends to degrade at annealing temperatures above 100 °C [38].

Table 2. Calculated work functions of iodization-annealed 40 nm CuI_x layers.

	Analyzed Average Φ (eV)	Correction Value (eV)	Calculated Average Φ (eV)
n-type Si	4.109	0.091	4.2 [4,38]
As deposited	4.981	0.091	5.072
100 °C N2	4.977	0.091	5.068
120 °C N2	4.972	0.091	5.063
140 °C N2	4.972	0.091	5.063
160 °C N2	4.948	0.091	5.039
180 °C N2	4.796	0.091	4.887

and Figure 7 show the work functions of the CuI_x layers with increasing the iodization-annealing temperature. Table 2 shows the relative work function values of the CuI_x layers measured using a platinum probe tip (4.78 eV), considering that n-type Si substrates generally exhibit a work function characteristic of approximately 4.2 eV [4,39]. Mapping analysis of the surface area (1 cm × 1 cm) of the iodization-annealed CuI_x layers revealed that the work function tended to decrease from 5.068 eV to 4.887 eV as the iodization-annealing temperature increased from 100 °C to 180 °C. While the work function is typically not known to decrease with increasing annealing temperature, a plausible explanation could be as follows: CuI shows changes in fermi energy level (E_F) according to the iodine ratio from a substoichiometric perspective. As the proportion of iodine increases, the E_F in the band structure shifts toward the conduction band, thereby reducing the work function [40]. The CuI_x layers without iodization annealing and those annealed at temperatures below 160 °C exhibited work functions greater than 5.0 eV, indicating Schottky contact with n-type Si, as shown in the I–V curves in Figure 8. In contrast, the CuI_x layers annealed at 180 °C exhibited work functions less than 5.0 eV, and the I–V curves in Figure 8 show linear characteristics, indicating ohmic contact. Thus, when the work function of a p-type semiconductor material is lower than 5.0 eV, it is difficult for the material to function as an HSC layer when applied to n-type Si.

3.2. Solar Cell Characteristics

The I–V curves and the corresponding results are depicted in Figure 8 and

Table 3. Cell parameters of the CuI_x–CSC solar cells with iodization annealing.

	Voc (mV)	Jsc (mA/cm2)	Fill Factor (%)	η (%)
RT	488	10.84	19.21	1.02
100 °C 40 nm	434	11.90	19.92	1.03
120 °C 40 nm	434	14.14	19.58	1.20
140 °C 40 nm	423	14.62	20.51	1.27
160 °C 40 nm	395	11.29	20.41	0.91
180 °C 40 nm	230	10.02	21.45	0.50

. In solar cell research, a standard formula is used for calculating efficiency to ensure consistent comparison among different solar cells. This standardized efficiency is known as the power conversion efficiency (PCE) and is calculated using the following equation:

$$\mathrm{P}\mathrm{C}\mathrm{E}(\eta )={\displaystyle \frac{P_{out}}{P_{in}}}={\displaystyle \frac{V_{OC}·J_{SC}·FF}{P_{in}}},$$

(3)

where P_in is the incident optical power (1000 W/m² for normalized AM 1.5 lighting), P_out is the electrical output power, V_oc is the open-circuit voltage, and J_sc is the short-circuit current. The fill factor (FF) in Equation (3) is the ratio of the maximum power (P_m) that can actually be obtained from the product of J_sc and V_oc:

$$\mathrm{F}\mathrm{F}={\displaystyle \frac{P_{in}}{V_{OC}·J_{SC}}}$$

(4)

The best conversion efficiency of CuI_x–CSC solar cells (CSC Si solar cell with CuI_x layer) was 1.27%, which was obtained from iodization annealing at 140 °C. The voltage tended to decrease with an increase in the iodization-annealing temperature. The electrical properties of the CuI_x layers improved significantly upon iodization annealing. However, increased annealing temperatures also compromised the performance of the hydrated intrinsic amorphous silicon layer at the interfaces. Considering both the improvement in the electrical properties of the CuI_x layers and the degradation in the interfacial properties, the CuI_x layers annealed at 140 °C achieved the best overall performance.

The CuI_x–CSC solar cell, which had the highest hole density of 6.84 × 10¹⁹ cm⁻³, had the highest short-circuit current density (J_sc) of 14.62 mA/cm². Both the hole density and hall mobility potentially had a combined effect on J_sc.

Figure 8. Current–voltage (I–V) curves of CuI_x–CSC solar cells (40 nm CuI_x layer) with iodization annealing.

Figure 8. Current–voltage (I–V) curves of CuI_x–CSC solar cells (40 nm CuI_x layer) with iodization annealing.

3.3. CuI_x–CSC Solar Cell Fabrication with Thickness-Controlled CuI_x Layers

When the voltage and J_sc values for a typical solar cell are low, it indicates that the p–n junction has not been properly formed in the device.

Previous studies have shown that when the thickness of CuI_x layers exceeds ~50 nm, the voltage of the fabricated solar cell tends to increase [18,41]. The low voltage value is attributed to the small thickness of the CuI_x layer. Thus, thick CuI_x layers were deposited at ~80 and ~120 nm to fabricate Si solar cells with the same structure as those of the previously constructed cells. Iodization annealing was carried out at 140 °C because the best cell properties were shown at this temperature. Figure 9 shows the cross-sectional SEM images of the CuI_x layer deposited on the Si substrate. It can be seen that there was no void between the Si substrate and the layers.

The I–V curves and the cell parameters are depicted in Figure 10 and Figure 11. The conversion efficiencies of the CuI_x–CSC solar cells with CuI_x layers of large thickness were 6.09% and 6.42%. All the parameters of the solar cell were improved. This indicates that to be used as HSC layers, CuI_x layers require a larger thickness than other TMO thin films (layer thickness < 30 nm) with similar properties. The voltage significantly increased to 535 mV and 550 mV at 79.6 nm and 118 nm, respectively (a 40 nm CuI_x layer resulted in 423 mV). Notably, J_sc increased more than twofold. However, while voltage and J_sc showed similar performances to a general solar cell, the FF had very low performance. The FF is primarily related to metal contact and needs to be improved.

4. Conclusions

In this study, we fabricated CuI_x layers with a work function greater than 5.0 eV, which are applicable as HSC layers for n-type Si, and improved their electrical properties through iodization annealing. The high carrier density and carrier mobility of the HSC layer are expected to facilitate hole collection. To enhance the function of the CuI_x layers as HSC layers, the composition ratio of iodine was increased via iodization annealing. When a CuI_x layer of 40 nm thickness was iodization annealed at 140 °C, it showed the highest I/Cu ratio and hole concentration values of 1.067 and 6.84 × 10¹⁹ cm⁻³. When the CSC Si solar cell was subjected to iodization annealing for a 118 nm-thick CuI_x layer, it achieved the best conversion efficiency of 6.42%. The electrical enhancement was realized by increasing the hole concentration and controlling the thickness of the HSC layer. The ~40 nm-thick CuI_x layer performed poorly as an HSC layer, while layers with thicknesses exceeding ~80 nm demonstrated relatively improved functionality as HSC layers. However, the efficiency was reduced compared with that of typical CSC Si solar cells, with the low voltage being the main cause. Effective band bending was not observed to occur when a p-type semiconductor with a work function of ~5.0 eV was applied to n-type silicon. The low voltage of the fabricated solar cells explains this observation, and even a slight decrease in work function below 5.0 eV was confirmed to impair the material’s functionality as an HSC layer. When the work function significantly exceeds 5.0 eV, effective band bending is expected to occur, leading to higher voltages. Thus, a work function significantly greater than 5.0 eV, a high hole concentration in the HSC layer, and the application of an ideal interface passivation material between the HSC layer and the n-Si together contribute to the development of high-efficiency CSC Si solar cells.