Design of an Ultra-Low Voltage Bias Current Generator Highly Immune to Electromagnetic Interference ^†

Abstract

The paper deals with the immunity to Electromagnetic Interference (EMI) of the current source for Ultra-Low-Voltage Integrated Circuits (ICs). Based on the properties of IC building blocks, such as the current-splitter and current correlator, a novel current generator is conceived. The proposed solution is suitable to provide currents to ICs operating in the sub-threshold region even in the presence of an electromagnetic polluted environment. The immunity to EMI of the proposed solution is compared with that of a conventional current mirror and evaluated by analytic means and with reference to the 180 nm CMOS technology process. The analysis highlights how the proposed solution generates currents down to nano-ampere intrinsically robust to the Radio Frequency (RF) interference affecting the input of the current generator, differently to what happens to the output current of a conventional mirror under the same conditions.

1. Introduction

Ubiquitous electronics systems require low power consumption to reduce the dependence on batteries through energy harvesting techniques [1,2]. Thus, the electronic circuits need to properly operate at an ultra-low supply voltage [3,4,5,6]. This reduces the logic threshold and the noise margin accordingly, making the Integrated Circuits (ICs) more vulnerable to Electromagnetic Interference (EMI) [7,8,9,10,11,12,13,14,15,16,17]. Thus, the robustness of Ultra-Low-Voltage (ULV) ICs in any electromagnetic-polluted environment is an even more demanding task to be guaranteed in a safety-critical device where the need for ultra-low power consumption merges with the request of properly operate in any condition [18,19,20].

ICs for implanted devices can include on-chip bias current generators operating in sub-threshold to improve current matching as well as allow easy bias current tuning [21,22]. For this reason, among the basic on-chip requirements, the current generation for ICs operating in sub-threshold in the presence of Radio Frequency Interference (RFI) is addressed in this paper.

To this purpose, the EMI robustness of conventional current mirrors operating in the saturation region is first briefly recalled in Section 2. Then, the properties of specific IC topologies operating in the sub-threshold region are summarized in Section 3. Based on such properties, a new current generator with an EMI immunity higher than those of existing current-mirror based schemes is proposed in Section 4. The respective EMI robustness is discussed and evaluated by means of time-domain computer simulations referring to the 180 nm technology process. The conclusions are finally drawn in Section 6.

2. RFI Effect on Current Mirrors

The susceptibility of current mirrors has been investigated, and some solutions to increase their EMI-robustness have been proposed in the literature [23,24,25,26,27,28,29,30]. The typical approach is based on capacitors properly placed to implement a filter and attenuate the EMI [23,24,25,26,27,28]. Anyhow, all these solutions refer to transistors nominally operating in the saturation region (above threshold).

Figure 1 represents the conventional N and P-type current mirrors. The input current $I_{\mathrm{IN}}$ is nominally translated into the output current $I_{\mathrm{OUT}}$ according to the ratio $K=\frac{{\left(\frac{W}{L}\right)}_1}{{\left(\frac{W}{L}\right)}_0}$. The presence of an EMI current $i_{\mathrm{emi}}$ superimposed on the input current $I_{\mathrm{IN}}$ affects the output current $I_{\mathrm{OUT}}$. A low-pass filter ($R_{\mathrm{F}}{C}_{\mathrm{F}}$) has been placed to highlight the EMI-induced (DC offset) current named $I_{{\mathrm{EMI}}_{\mathrm{OFFSET}\mathrm{n}}}$ and $I_{{\mathrm{EMI}}_{\mathrm{OFFSET}\mathrm{p}}}$ in Figure 1a,b respectively. Notice that along with the paper, the capitalization and lower cases used to name the currents refer to their DC and time-continuous signal values respectively.

In the presence of interference, the total current through the first branch of the current mirror can then be modeled as the sum of a Continuous Wave (CW) Radio Frequency (RF) current $i_{\mathrm{emi}}$ and the proper DC current $I_{\mathrm{IN}}$. This results in an output current affected by EMI $i_{{\mathrm{out}}_{\mathrm{emi}}}$ for an N-type mirror [28]:

$$i_{{\mathrm{out}}_{\mathrm{emi}}}=K\left[I_{\mathrm{IN}}-C_{\mathrm{F}}\sqrt{\frac{1}{\frac{\mu C_{\mathrm{ox}}}{2}·{\left(\frac{W}{L}\right)}_0}}·\frac{d}{dt}\left(\sqrt{I_{\mathrm{IN}}+i_{\mathrm{emi}}}\right)\right]$$

(1)

where $K=\frac{{\left(\frac{W}{L}\right)}_1}{{\left(\frac{W}{L}\right)}_0}$ is the ratio of the transistors’ size, $\mu$ is the charge-carrier effective mobility, and $C_{\mathrm{ox}}$ is the gate oxide capacitance per unit area.

Equation (1) shows that for an N-type mirror (P-type mirror), the DC level of the output current is lower (higher) than it should be, owing to the loading of the input node by capacitor $C_{\mathrm{F}}$. This means that, in turn, the output current $i_{{\mathrm{out}}_{\mathrm{emi}}}$ can be modeled as the sum of the desired DC current $I_{\mathrm{OUT}}$ and a negative (positive) current offset named as $-I_{\mathrm{EMI}-{\mathrm{OFFSET}}_{\mathrm{n}}}$ ($+I_{\mathrm{EMI}-{\mathrm{OFFSET}}_{\mathrm{p}}}$) as reported at the output branches of the current mirrors in Figure 1a,b. In other words, Equation (1) can be rewritten as

$$i_{{\mathrm{out}}_{\mathrm{emi}}}=I_{\mathrm{OUT}}+i_{\mathrm{error}}$$

(2)

where $I_{\mathrm{OUT}}=K·I_{\mathrm{IN}}$ is the nominal output current with no EMI presence and $i_{\mathrm{error}}$ represents the effect of the EMI on the output current.

Thus,

$$i_{\mathrm{error}}=i_{\mathrm{emi}-\mathrm{induced}}=K{C}_{\mathrm{F}}\sqrt{\frac{1}{\frac{\mu C_{\mathrm{ox}}}{2}·{\left(\frac{W}{L}\right)}_0}}·\frac{d}{dt}\left(\sqrt{I_{\mathrm{IN}}+i_{\mathrm{emi}}}\right)$$

(3)

which implies an EMI-induced offset on the output current $I_{\mathrm{EMI}-\mathrm{OFFSET}}=|i_{\mathrm{error}}|=|i_{\mathrm{emi}-\mathrm{induced}}|$ so that Equation (2) can be rewritten referring to the DC values as:

$$I_{{\mathrm{OUT}}_{\mathrm{EMI}}}=I_{\mathrm{OUT}}+I_{\mathrm{EMI}-\mathrm{OFFSET}}$$

(4)

These analytic results are valid under the assumption that in the N-type (P-type) current mirror both the transistors $M_{\mathrm{n}0}$ ($M_{\mathrm{p}0}$) and $M_{\mathrm{n}1}$ ($M_{\mathrm{p}1}$) operate in the saturation region.

3. Ultra-Low-Voltage Current Generators

To reduce the overall power consumption of any System-on-Chip, the trend in reducing the power supply moves towards ICs operating in sub-threshold and thus towards a range of current below micro-amperes. This means that the mirroring ratio K could convert currents in the range of micro-amperes into mirrored currents in the nano-amperes range.

To move towards Ultra-Low-Voltage current generators, the properties of transistors operating in sub-threshold [31] are explored to build an IC solution more robust to EMI. For this reason, the properties of the current-splitter [32,33] and the current-correlator [34] are summarized, respectively, in Section 3.1 and Section 3.2.

3.1. Current-Splitter

Figure 2 represents N- and P-type current-splitters (Figure 2a,b respectively). Such circuits are capable of providing sourced or sunk currents in the order of nano-amperes or even below through a splitting technique. The size ratio of the transistors Ma, Mb and Mf are ${(W/L)}_a=N-1$, ${(W/L)}_b=N/(N-1)$ and ${(W/L)}_f=1$ respectively [32]. The current provided by each output branch is progressively divided by a factor N [32]. In other words, the currents provided by each branch comes from a resistive-like partition of the reference current. Indeed, for N = 2 the current-splitter behaves like an M2M ladder network which can be controlled digitally by means of switches to produce any combination of binary-weighted currents. Differently, in the current-splitter, N can be chosen higher than two to rapidly scale down (with the factor N) the reference (input) current $I_{\mathrm{REF}}$. By lowering the operating currents, both noise and mismatch will remain constant and independent by the current level for the complete weak inversion regime [32].

Figure 3 compares how to scale a current $I_{\mathrm{IN}}$ with a current mirror by a factor $K_{\mathrm{M}}=\frac{{\left(\frac{W}{L}\right)}_0}{{\left(\frac{W}{L}\right)}_1}$ (see Figure 3a) and with a current-splitter by a factor $K_{\mathrm{CS}}$ = $N^2$ (see Figure 3b). Such a factor is originated by the sum of the N-weighted currents provided by the enabled branches of the current-splitters [32].

Based on these characteristics, the current-splitter perfectly matches the needs of current scaling to bias Ultra-Low-Voltage ICs. In fact, the current-splitter is already used in critical scenarios like neural implants where low power consumption and high reliability are tight constraints [22,35]. This makes further valuable the investigation of ULV current generators robust to EMI.

Referring to Figure 3, assuming $K_{\mathrm{M}}$ = $K_{\mathrm{CS}}$ = $N^2$ = 100 and accordingly to the sizing reported in

Table 1. Sizing of the transistor in Figure 3.

Parameter	Value	Units
${(W/L)}_0$	$100/1$	μm/μm
${(W/L)}_1$	$1/1$	μm/μm
${(W/L)}_{{\mathrm{a}}_{\mathrm{n},\mathrm{p}}}$	$9/1$	μm/μm
${(W/L)}_{{\mathrm{b}}_{\mathrm{n},\mathrm{p}}}$	$10/9$	μm/μm
${(W/L)}_{{\mathrm{f}}_{\mathrm{n},\mathrm{p}}}$	$1/1$	μm/μm

, the overall area of the proposed solution is 2.5× larger than that of the current mirror. Moreover, to properly set the M2M-ladder division, the current $I_{\mathrm{IN}}$ has to be mirrored. This results in doubled overall power consumption. Anyhow, such a current scaling joint with the current correlator properties (in Section 3.2) allows to dramatically increase the EMI robustness of current bias for ICs operating in sub-threshold solution without any additional (external) capacitance as shown in the following.

3.2. Current Correlator

Another valuable circuit topology that operates in the sub-threshold region is the current-correlator shown in Figure 4 [34]. This circuit computes a measure of the correlation between its two input currents named $I_{\mathrm{A}}$ and $I_{\mathrm{B}}$. More precisely, the output current $I_{\mathrm{OUT}}$ is proportional to the product of the two input currents, divided by the sum of the inputs:

$$I_{\mathrm{OUT}}=K_{\mathrm{CC}}·\frac{I_{\mathrm{A}}{I}_{\mathrm{B}}}{I_{\mathrm{A}}+I_{\mathrm{B}}}$$

(5)

where $K_{\mathrm{CC}}=\frac{{\left(\frac{W}{L}\right)}_{middle}}{{\left(\frac{W}{L}\right)}_{outer}}$.

To reduce the overall EMI-induced offset, in this topology $I_{\mathrm{A}}$ e $I_{\mathrm{B}}$ are considered to be, respectively, affected by the P- and N-type induced EMI offset:

$$\begin{array}{c}\hfill I_{\mathrm{A}}=I_{\mathrm{IN}}+I_{{\mathrm{EMI}}_{\mathrm{OFFSETp}}}\\ \hfill I_{\mathrm{B}}=I_{\mathrm{IN}}-I_{{\mathrm{EMI}}_{\mathrm{OFFSETn}}}\end{array}$$

(6)

Assuming $I_{{\mathrm{EMI}}_{\mathrm{OFFSETp}}}\approx I_{{\mathrm{EMI}}_{\mathrm{OFFSETn}}}=I_{{\mathrm{EMI}}_{\mathrm{OFFSET}}}$, Equation (5) can be rewritten as:

$$I_{{\mathrm{OUT}}_{\mathrm{emi}}}\approx K_{\mathrm{CC}}\left(\frac{I_{\mathrm{IN}}}{2}-\frac{I_{{\mathrm{EMI}}_{\mathrm{OFFSET}}}^2}{2I_{\mathrm{IN}}}\right)$$

(7)

The effect of the two different EMI offset contributions at the two input branches is compensated so that:

$$I_{{\mathrm{OUT}}_{\mathrm{emi}}}\approx I_{\mathrm{OUT}}-K_{\mathrm{CC}}·\left(\frac{I_{{\mathrm{EMI}}_{\mathrm{OFFSET}}}^2}{2I_{\mathrm{IN}}}\right)=I_{\mathrm{OUT}}-I_{\mathrm{ERROR}}$$

(8)

where

$$I_{\mathrm{ERROR}}=K_{\mathrm{CC}}·\left(\frac{I_{{\mathrm{EMI}}_{\mathrm{OFFSET}}}^2}{2I_{\mathrm{IN}}}\right)$$

(9)

Comparing Equations (9) with Equation (3), it can be noticed that the overall EMI-induced offset error $I_{\mathrm{ERROR}}$ is now much attenuated. In fact, in the practical case $I_{{\mathrm{EMI}}_{\mathrm{OFFSET}}}^2\ll I_{\mathrm{IN}}$ so that the error factor $K_{\mathrm{CC}}·\frac{I_{{\mathrm{EMI}}_{\mathrm{OFFSET}}}^2}{2I_{\mathrm{IN}}}$ is negligible and the output current is not strongly affected by the EMI:

$$I_{{\mathrm{OUT}}_{\mathrm{emi}}}\approx K_{\mathrm{CC}}·\frac{I_{\mathrm{IN}}}{2}=I_{\mathrm{OUT}}$$

(10)

Figure 5 represents how an EMI current $i_{\mathrm{emi}}$ generates an EMI-induced offset $I_{{\mathrm{EMI}}_{\mathrm{OFFSET}}}$ on a conventional current mirror while EMI currents superimposed with the opposite sign to the two branches of a current correlator do not affect its output current $I_{\mathrm{OUT}}$.

Notice that even if the EMI-induced offset currents $I_{{\mathrm{EMI}}_{\mathrm{OFFSETp}}}$ and $I_{{\mathrm{EMI}}_{\mathrm{OFFSETn}}}$ superimposed on the nominal current $I_{\mathrm{IN}}$ of the two input branches of the current correlator with opposite signs (as in Equation (6)) are not equal in amplitude ($I_{{\mathrm{EMI}}_{\mathrm{OFFSETp}}}\ne I_{{\mathrm{EMI}}_{\mathrm{OFFSETn}}}$) but in the same order of magnitude, the interference effect on the output current $I_{\mathrm{OUT}}$ is attenuated.

This characteristic will be exploited in the newly proposed solution and validated by means of simulation in Section 4.

4. A New Current Generator Robust to EMI

The above-described circuit topologies operating in sub-threshold are employed as building blocks of a new current biasing circuit sketched in Figure 6 in which the input current to be mirrored and scaled is affected by EMI.

The input current $I_{\mathrm{IN}}$ represents both the independent sourced ($I_{\mathrm{SOURCE}}$) and sunk ($I_{\mathrm{SINK}}$) currents ($I_{\mathrm{SOURCE}}=I_{\mathrm{SINK}}=I_{\mathrm{IN}}$) that come from reference currents (not reported in Figure 6. These reference currents are usually implemented using a voltage regulator and an operational amplifier to produce a current from the feedback of a small series resistance [36]. To not introduce any error, these building blocks should be designed according to the existing design guidelines to avoid any EMI-induced offset at their outputs [37,38,39,40]. In this way, the proper input DC current $I_{\mathrm{IN}}$ can be provided even if still affected by a superimposed EMI current $i_{\mathrm{emi}}$. Thus, for sake of simplicity and focusing on the current generator only, $I_{\mathrm{IN}}=I_{\mathrm{SOURCE}}=I_{\mathrm{SINK}}$ is considered. The same assumption is applied for the respective superimposed EMI currents ($i_{\mathrm{emi}}=i_{\mathrm{emi},\mathrm{source}}=i_{\mathrm{emi},\mathrm{sink}}$). Notice that the minimum difference in the inputs branches currents ($I_{\mathrm{SOURCE}}$ and $I_{\mathrm{SINK}}$) and in the respective superimposed EMI currents ($i_{\mathrm{emi},\mathrm{source}}$ and $i_{\mathrm{emi},\mathrm{sink}}$) do not affect the mathematical definition of the output current $I_{\mathrm{OUT}}$ much.

The input current $I_{\mathrm{IN}}$ is scaled down by a ratio factor $K_{\mathrm{CS}}$ through both P and N-type current-splitters. The presence of complementary current-splitters in the circuit in Figure 6 allows to rapidly scale the input current and benefit from the EMI-induced offset compensation based on an N-P offset compensation [40], which is performed through the current-correlator. The scaled currents coming from a P and N-type current-splitters flow to the respective current correlator that balances the opposite offset trend according to Equation (7). Assuming the aspect ratio of the current-correlator is equal to $K_{\mathrm{CC}}=2$:

$$I_{\mathrm{OUT}}\approx K_{\mathrm{CC}}\frac{I_{\mathrm{IN}}}{2K_{\mathrm{CS}}}=\frac{I_{\mathrm{IN}}}{K_{\mathrm{CS}}}$$

(11)

On this basis, the circuit in Figure 6 performs a current mirror-like function suitable for ICs operating in the nano-ampere range and highly immune to EMI.

5. Validation and Comparison

To verify the EMI robustness of the proposed circuit solution, time-domain simulations have been performed with reference to the 180 nm CMOS technology. Analyses have been carried out referring to a traditional current mirror in Figure 5a and the proposed solution in Figure 6. For both these current bias methods, the output current $I_{\mathrm{OUT}}=100$ nA originates from an input current $I_{\mathrm{IN}}=10$ μA affected by a CW RF current $i_{\mathrm{emi}}$. It means that $K_{\mathrm{M}}=K_{\mathrm{CS}}=100$. Thus, both the P- and N-type current-splitters divide the input current twice by a factor N = 10.

Table 2. Sizing of the transistor employed in the new current bias method proposed in Figure 6.

Parameter	Value	Units
${(W/L)}_{{\mathrm{a}}_{\mathrm{n},\mathrm{p}}}$	$9/1$	μm/μm
${(W/L)}_{{\mathrm{b}}_{\mathrm{n},\mathrm{p}}}$	$10/9$	μm/μm
${(W/L)}_{{\mathrm{f}}_{\mathrm{n},\mathrm{p}}}$	$1/1$	μm/μm
${(W/L)}_{\mathrm{middle}}$	$10/1$	μm/μm
${(W/L)}_{\mathrm{outer}}$	$10/1$	μm/μm
${(W/L)}_{\mathrm{n}}$	$10/1$	μm/μm
${(W/L)}_{\mathrm{p}}$	$10/1$	μm/μm

reports the transistors’ size for both the current-splitters and current correlator presented in Figure 6. On this basis, the overall area results to be 5× larger than that of a conventional current mirror with the same scaling factor.

The interference current $i_{\mathrm{emi}}$ is superimposed on the input current $I_{\mathrm{IN}}$ and the DC offset on the output current $I_{\mathrm{OUT}}$ is evaluated similarly to immunity tests [41]. Every simulation result refers to the average value assumed by the output current in steady-state conditions when the offset becomes constant and while the input is affected by a CW EMI. In addition, process corner variations have also been reported: ss (dashed) and ff (dotted-dashed) line. Such variations could vary the DC nominal output current $I_{\mathrm{OUT}}$ up to $10\%$ in the proposed solution but not its EMI robustness. Thus, if a precise output current value is needed, it can be reached through calibration keeping the EMI robustness capability.

In Figure 7 the EMI-induced offset on the current $I_{\mathrm{OUT}}=100$ nA versus the amplitude of the interference $i_{\mathrm{emi}}$ at 100 MHz is reported. A relevant gap between the two EMI-induced offsets on the output current can be highlighted. The newly proposed solution represented in Figure 6 shows an error on the output current below 5% for a CW RF interference current $i_{\mathrm{emi}}$ equal to $50$ μA. In the same condition, the conventional current mirror exhibits an error of 90% (from 100 to 10 nA).

Similarly, the amplitude of the interference is kept constant and equal to $i_{\mathrm{emi}}=50$ μA while its frequency is swept in the RF range in Figure 8. The proposed current generator shows higher robustness to EMI in a larger RF range.

Figure 9 represents the percentage variations of the output current ($I_{{\mathrm{OUT}}_{\mathrm{error}}}=\frac{I_{\mathrm{OUT}}-I_{{\mathrm{OUT}}_{\mathrm{emi}}}}{I_{\mathrm{OUT}}}$$·100$) due to the interference $i_{\mathrm{emi}}$ versus the value of the DC value itself $I_{\mathrm{OUT}}$ with no EMI presence. The sweep in the $I_{\mathrm{OUT}}$ has been obtained simply changing the input DC current $I_{\mathrm{IN}}$ and keeping the CW RF interference $i_{\mathrm{emi}}$ at 100 MHz, the same frequency of the amplitude sweep in Figure 7 and with the same amplitude of the frequency sweep in Figure 8 ($i_{\mathrm{emi}}=50$ μA). The lower the output current $I_{\mathrm{OUT}}$ to obtain, the higher the effectiveness of the proposed method in providing a current robust to EMI.

6. Conclusions

In this work, a new integrated method suitable to provide currents for ICs operating in sub-threshold and robust to EMI has been discussed. The EMI-induced offset on the output current of a conventional current mirror is first considered. Then, based on ICs building blocks operating in sub-threshold, a new current generator for ULV ICs has been proposed. Such an IC solution exploits the N-P offset compensation and the properties of the current-correlator to strongly attenuate the EMI-induced offset on the output current.

The mathematical results as well as the time domain simulations show that for different conditions of frequency and amplitude of the EMI, the newly proposed solution to generate currents for ICs operating in sub-threshold is highly immune to EMI and much more robust than conventional current mirrors. This is at the cost of 4× higher overall current consumption (2× for each current-splitter) and 5× larger area compared to the conventional current mirroring.