J. Low Power Electron. Appl. 2025, 15(1), 7; https://doi.org/10.3390/jlpea15010007 - 29 Jan 2025
Abstract
This paper presents a novel transistor-level design of a modified second-generation voltage conveyor (VCII), which incorporates two differential current inputs (Y+ and Y−) and gives a voltage output at terminal X that mirrors the sum of these currents. The circuit operation is based
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This paper presents a novel transistor-level design of a modified second-generation voltage conveyor (VCII), which incorporates two differential current inputs (Y+ and Y−) and gives a voltage output at terminal X that mirrors the sum of these currents. The circuit operation is based on current mirrors that maintain the X terminal in a stable “quiescent” state when no differential current is applied at Y+ and Y−. When a current flows into one of the two inputs, the sum is mirrored into X, providing a summed current measurement. This design, developed in a standard 0.35 μm CMOS transistors technology, ensures circuit high accuracy and robustness. The low power consumption of 24.6 μW makes it well-suited for portable biomedical applications as in environmental fields.
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