Journal of Low Power Electronics and Applications

19 pages, 835 KiB

Open AccessReview

Key Role of Cold-Start Circuits in Low-Power Energy Harvesting Systems: A Research Review

by Xiao Shi, Mengye Cai and Yanfeng Jiang

J. Low Power Electron. Appl. 2024, 14(4), 55; https://doi.org/10.3390/jlpea14040055 - 22 Nov 2024

The primary functions of an energy harvesting system include the harvesting, transformation, management, and storage of energy. Until now, various types of energy, with different power levels, have been harvested and stored by the energy harvesting system. In low-power scenarios, such as microwaves, [...] Read more.

The primary functions of an energy harvesting system include the harvesting, transformation, management, and storage of energy. Until now, various types of energy, with different power levels, have been harvested and stored by the energy harvesting system. In low-power scenarios, such as microwaves, sound, friction, and pressure, a specific low-power energy harvesting system is required. Due to the absence of an external power supply in such systems, cold-start circuits play a crucial role in igniting the low-power energy harvesting system, ensuring a reliable start-up from the initial state. This paper reviews the categorization and characteristics of energy harvesting systems, with a focus on the design and performance parameters of cold-start circuits. A tabular comparison of existing cold-start strategies is presented herein. The study demonstrates that resonance-based integrated cold-start methods offer significant advantages in terms of conversion efficiency and dynamic range, while ring oscillator-based integrated cold-start methods achieve the lowest start-up voltage. Additionally, the paper discusses the challenges of self-starting and future research directions, highlighting the potential role of emerging technologies, such as artificial intelligence (AI) and neural networks, in optimizing the design of energy harvesting systems. Full article

23 pages, 8197 KiB

Open AccessArticle

Multi-Timescale Energy Consumption Management in Smart Buildings Using Hybrid Deep Artificial Neural Networks

by Favour Ibude, Abayomi Otebolaku, Jude E. Ameh and Augustine Ikpehai

J. Low Power Electron. Appl. 2024, 14(4), 54; https://doi.org/10.3390/jlpea14040054 - 7 Nov 2024

Viewed by 747

Abstract

Demand side management is a critical issue in the energy sector. Recent events such as the global energy crisis, costs, the necessity to reduce greenhouse emissions, and extreme weather conditions have increased the need for energy efficiency. Thus, accurately predicting energy consumption is [...] Read more.

Demand side management is a critical issue in the energy sector. Recent events such as the global energy crisis, costs, the necessity to reduce greenhouse emissions, and extreme weather conditions have increased the need for energy efficiency. Thus, accurately predicting energy consumption is one of the key steps in addressing inefficiency in energy consumption and its optimization. In this regard, accurate predictions on a daily, hourly, and minute-by-minute basis would not only minimize wastage but would also help to save costs. In this article, we propose intelligent models using ensembles of convolutional neural network (CNN), long-short-term memory (LSTM), bi-directional LSTM and gated recurrent units (GRUs) neural network models for daily, hourly, and minute-by-minute predictions of energy consumptions in smart buildings. The proposed models outperform state-of-the-art deep neural network models for predicting minute-by-minute energy consumption, with a mean square error of 0.109. The evaluated hybrid models also capture more latent trends in the data than traditional single models. The results highlight the potential of using hybrid deep learning models for improved energy efficiency management in smart buildings. Full article

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16 pages, 3143 KiB

Open AccessArticle

A Low-Power 5-Bit Two-Step Flash Analog-to-Digital Converter with Double-Tail Dynamic Comparator in 90 nm Digital CMOS

by Reena George and Nagesh Ch

J. Low Power Electron. Appl. 2024, 14(4), 53; https://doi.org/10.3390/jlpea14040053 - 4 Nov 2024

Viewed by 613

Abstract

Low-power portable devices play a major role in IoT applications, where the analog-to-digital converters (ADCs) are very important components for the processing of analog signals. In this paper, a 5-bit two-step flash ADC with a low-power double-tail dynamic comparator (DTDC) using the control [...] Read more.

Low-power portable devices play a major role in IoT applications, where the analog-to-digital converters (ADCs) are very important components for the processing of analog signals. In this paper, a 5-bit two-step flash ADC with a low-power double-tail dynamic comparator (DTDC) using the control switching technique is presented. The most significant bit (MSB) in the proposed design is produced by only one low-power DTDC in the first stage, and the remaining bits are generated by the flash ADC in the second stage with the help of an auto-control circuit. A control circuit produced reference voltages with respect to the control input and mid-point voltage (

V_{k}

). The proposed design and simulations are carried out using 90 nm CMOS technology. The result shows that the peak differential non-linearity (DNL) and integral non-linearity (INL) are +0.60/−0.69 and +0.66/−0.40 LSB, respectively. The signal-to-noise and distortion ratio (SNDR) for an input signal having a frequency of 1.75 MHz is found to be 30.31 dB. The total power consumption of the proposed design is significantly reduced, which is 439.178

μ

W for a supply voltage of 1.2 V. The figure of merit (FOM) is about 0.054 pJ/conversion step at 250 MS/s. The present design provides low power consumption and occupies less area compared to the existing works. Full article

(This article belongs to the Special Issue Analog/Mixed-Signal Integrated Circuit Design)

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18 pages, 11691 KiB

Open AccessArticle

Characterization of the Power Distribution Network for Commercialized STM32s Using a Resonance Frequency Measurement Method

by Marie Peyrard, Gilles Jacquemod and Nicolas Froidevaux

J. Low Power Electron. Appl. 2024, 14(4), 52; https://doi.org/10.3390/jlpea14040052 - 1 Nov 2024

Viewed by 552

Abstract

Power integrity is a critical aspect of microcontroller (MCU) system design. The present tendency of increasing current density and operating frequency, along with decreasing operating voltage, significantly diminishes voltage margins. Given the cost efficiency required for MCU systems, this context places important constraints [...] Read more.

Power integrity is a critical aspect of microcontroller (MCU) system design. The present tendency of increasing current density and operating frequency, along with decreasing operating voltage, significantly diminishes voltage margins. Given the cost efficiency required for MCU systems, this context places important constraints on the design of the power distribution network (PDN), which directly impacts power supply noise. Therefore, characterizing the PDN is necessary. This paper introduces a cost-effective measurement and modeling method to estimate the die-package resonance frequency of the PDN, a major threat to power integrity. The method, applied to two 32-bit MCUs from STMicroelectronics with varying PDN configurations, enables the identification of the die-package resonance frequency. The results lead to the refinement of the die capacitance model for both cases, with a maximum relative error of less than 7%. The final objective is to implement the measurement system in the die in order to adjust the PDN if necessary. Full article

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11 pages, 3506 KiB

Open AccessArticle

Multichannel Sensor Array Design for Minimizing Detector Complexity and Power Consumption in Ionoacoustic Proton Beam Tomography

by Elia Arturo Vallicelli, Alessandro Michele Ferrara, Maurizio Marrale, Mattia Tambaro and Marcello De Matteis

J. Low Power Electron. Appl. 2024, 14(4), 51; https://doi.org/10.3390/jlpea14040051 - 30 Oct 2024

Viewed by 529

Abstract

Ionoacoustic tomography exploits the acoustic signal generated by the fast energy deposition along the path of pulsed particle beams to reconstruct with sub-mm precision the dose deposition, with promising envisioned applications in hadron therapy treatment monitoring. State-of-the-art ionoacoustic detectors mainly rely on single-channel [...] Read more.

Ionoacoustic tomography exploits the acoustic signal generated by the fast energy deposition along the path of pulsed particle beams to reconstruct with sub-mm precision the dose deposition, with promising envisioned applications in hadron therapy treatment monitoring. State-of-the-art ionoacoustic detectors mainly rely on single-channel sensors and time-of-flight measurements to provide 1D localization of the maximum dose deposition at the so-called Bragg peak. This work investigates the design challenges of multichannel sensors for ionoacoustic tomography in terms of their ability to accurately reconstruct the dose deposition of a 200 MeV clinical proton beam, highlighting the impact of the number of channels in the array and their directivity. A complete acoustic model of the sensors and environment has been developed and used to find an optimum tradeoff between accuracy, evaluated numerically through the gamma index, and hardware complexity due to higher channel numbers, thus minimizing the system-level power consumption of the detector. Full article

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12 pages, 3403 KiB

Open AccessArticle

Phase Change Memory Drift Compensation in Spiking Neural Networks Using a Non-Linear Current Scaling Strategy

by Joao Henrique Quintino Palhares, Nikhil Garg, Yann Beilliard, Lorena Anghel, Fabien Alibart, Dominique Drouin and Philippe Galy

J. Low Power Electron. Appl. 2024, 14(4), 50; https://doi.org/10.3390/jlpea14040050 - 22 Oct 2024

Viewed by 574

Abstract

The non-ideality aspects of phase change memory (PCM) such as drift and resistance variability can pose significant obstacles in neuromorphic hardware implementations. A unique drift and variability compensation strategy is demonstrated and implemented in an FD-SOI SNN hardware unit composed of embedded phase [...] Read more.

The non-ideality aspects of phase change memory (PCM) such as drift and resistance variability can pose significant obstacles in neuromorphic hardware implementations. A unique drift and variability compensation strategy is demonstrated and implemented in an FD-SOI SNN hardware unit composed of embedded phase change memories (ePCMs), current attenuators, and spiking neurons. The effect of drift and variability compensation on inference accuracy is tested on the MNIST dataset to show that our drift and variability mitigation strategy is effective in sustaining its accuracy over time. The variability is reduced by up to 5% while the drift coefficient is reduced by up to 57.8%. The drift is compensated and the SNN classification accuracy is sustained for up to 2 years with intrinsic control-free hardware that tracks the ePCM current over time and consumes less than 30 µW. The results are based on ePCM chip experimental data and pos-layout simulation of a test chip comprising the proposed circuit solution. Full article

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18 pages, 2349 KiB

Open AccessArticle

A High-Efficiency Piezoelectric Energy Harvesting and Management Circuit Based on Full-Bridge Rectification

by Shuhan Liu, Suhao Chen, Wei Gao, Jiabin Zhang, Dacheng Xu, Fang Chen, Zhenghao Lu and Xiaopeng Yu

J. Low Power Electron. Appl. 2024, 14(4), 49; https://doi.org/10.3390/jlpea14040049 - 8 Oct 2024

Viewed by 757

Abstract

This paper presents a high-efficiency piezoelectric energy harvesting and management circuit utilizing a full-bridge rectifier (FBR) designed for powering wireless sensor nodes. The circuit comprises a rectifier bridge, a fully CMOS-based reference source, and an energy management system. The rectifier bridge uses a [...] Read more.

This paper presents a high-efficiency piezoelectric energy harvesting and management circuit utilizing a full-bridge rectifier (FBR) designed for powering wireless sensor nodes. The circuit comprises a rectifier bridge, a fully CMOS-based reference source, and an energy management system. The rectifier bridge uses a PMOS cross-coupled structure to greatly reduce the conduction voltage drop. The CMOS reference source provides the necessary reference voltage and current. The energy management system delivers a stable 1.8 V to the load and controls its operation in intermittent bursts. Fabricated with a 110 nm CMOS process, the circuit occupies an area of 0.6 mm², and is housed in a QFN32 package. Test results indicate that under 40 Hz frequency and 4 g acceleration vibrations, the chip’s energy extraction power reaches 234

μ

W, with the load operating every 3 s at a supply voltage of 1.8 V. Thus, this FBR interface circuit efficiently harnesses the energy output from the piezoelectric energy harvester. Full article

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10 pages, 4646 KiB

Open AccessArticle

Energy Restoration in Data Drivers for Low-Power Digitally Driven OLEDoS Microdisplays

by Sheida Gohardehi and Manoj Sachdev

J. Low Power Electron. Appl. 2024, 14(4), 48; https://doi.org/10.3390/jlpea14040048 - 4 Oct 2024

Viewed by 677

Abstract

Microdisplays are widely used in near-to-eye (NTE) applications that operate with batteries, and reducing the power consumption of microdisplays is key to increasing their battery life. This paper proposes a digital data driver with a data energy recycling feature to reduce its dynamic [...] Read more.

Microdisplays are widely used in near-to-eye (NTE) applications that operate with batteries, and reducing the power consumption of microdisplays is key to increasing their battery life. This paper proposes a digital data driver with a data energy recycling feature to reduce its dynamic power consumption. According to the measurement results obtained from a proof-of-concept array fabricated using TSMC 65 nm technology, the power consumption of the display data driver demonstrates an average reduction of 16% when tested with 10 random black-and-white images or a 14.4% decrease when evaluated using four real-life test images. Full article

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17 pages, 5175 KiB

Open AccessArticle

Reliability Enhancement Methods for Relaxation Oscillator with Delay Time Cancellation

by Kunpeng Xu, Hongguang Dai, Zhanxia Wu, Zhibo Huang, Guoqiang Zhang, Xiaopeng Yu, Wechang Wang and Gang Xuan

J. Low Power Electron. Appl. 2024, 14(4), 47; https://doi.org/10.3390/jlpea14040047 - 26 Sep 2024

Viewed by 724

Abstract

Relaxation oscillators are preferred in low-frequency applications due to their lower power consumption and superior temperature stability. However, frequency errors arise from variations in the comparator’s offset voltage and delay time due to PVT changes. To address these issues, this paper proposes the [...] Read more.

Relaxation oscillators are preferred in low-frequency applications due to their lower power consumption and superior temperature stability. However, frequency errors arise from variations in the comparator’s offset voltage and delay time due to PVT changes. To address these issues, this paper proposes the low-power delay time cancellation (DTC) technique and several enhancement methods, including a novel offset trimming approach, an error state detection and recovery (ESDAR) circuit, and a specialized frequency-trimming method. Simulation results for an 8 MHz relaxation oscillator in a 40 nm CMOS process show that the proposed DTC technique and enhancements improve frequency variation due to power supply fluctuations to ±0.05% and reduce temperature-induced frequency variation to ±0.4%. Full article

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J. Low Power Electron. Appl., Volume 14, Issue 4 (December 2024) – 9 articles

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