Journal of Low Power Electronics and Applications

17 pages, 4715 KiB

Open AccessArticle

IoT-MFaceNet: Internet-of-Things-Based Face Recognition Using MobileNetV2 and FaceNet Deep-Learning Implementations on a Raspberry Pi-400

by Ahmad Saeed Mohammad, Thoalfeqar G. Jarullah, Musab T. S. Al-Kaltakchi, Jabir Alshehabi Al-Ani and Somdip Dey

J. Low Power Electron. Appl. 2024, 14(3), 46; https://doi.org/10.3390/jlpea14030046 - 5 Sep 2024

Viewed by 50952

Abstract

IoT applications revolutionize industries by enhancing operations, enabling data-driven decisions, and fostering innovation. This study explores the growing potential of IoT-based facial recognition for mobile devices, a technology rapidly advancing within the interconnected IoT landscape. The investigation proposes a framework called IoT-MFaceNet (Internet-of-Things-based [...] Read more.

IoT applications revolutionize industries by enhancing operations, enabling data-driven decisions, and fostering innovation. This study explores the growing potential of IoT-based facial recognition for mobile devices, a technology rapidly advancing within the interconnected IoT landscape. The investigation proposes a framework called IoT-MFaceNet (Internet-of-Things-based face recognition using MobileNetV2 and FaceNet deep-learning) utilizing pre-existing deep-learning methods, employing the MobileNetV2 and FaceNet algorithms on both ImageNet and FaceNet databases. Additionally, an in-house database is compiled, capturing data from 50 individuals via a web camera and 10 subjects through a smartphone camera. Pre-processing of the in-house database involves face detection using OpenCV’s Haar Cascade, Dlib’s CNN Face Detector, and Mediapipe’s Face. The resulting system demonstrates high accuracy in real-time and operates efficiently on low-powered devices like the Raspberry Pi 400. The evaluation involves the use of the multilayer perceptron (MLP) and support vector machine (SVM) classifiers. The system primarily functions as a closed set identification system within a computer engineering department at the College of Engineering, Mustansiriyah University, Iraq, allowing access exclusively to department staff for the department rapporteur room. The proposed system undergoes successful testing, achieving a maximum accuracy rate of 99.976%. Full article

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12 pages, 3997 KiB

Open AccessArticle

Split-Voltage Configuration Improves Integrated Amplifier Power-Efficiency

by Sebastian Simmich and Robert Rieger

J. Low Power Electron. Appl. 2024, 14(3), 45; https://doi.org/10.3390/jlpea14030045 - 4 Sep 2024

Viewed by 658

Abstract

A split-voltage amplifier architecture is proposed which improves the power efficiency compared to a conventional implementation. The approach is verified with a prototype fabricated in 0.35 µm CMOS technology using lateral bipolar input transistors. It achieves a measured DC gain of 105 V [...] Read more.

A split-voltage amplifier architecture is proposed which improves the power efficiency compared to a conventional implementation. The approach is verified with a prototype fabricated in 0.35 µm CMOS technology using lateral bipolar input transistors. It achieves a measured DC gain of 105 V/V, a differential AC gain of 40.3 dB with a bandwidth of 55 kHz, a CMRR of approximately 75 dB, and a PSRR of 55 dB. The input-referred noise is 7 nV/√Hz and 923 nVrms integrated from 100 Hz to 10 kHz, resulting in a Noise Efficiency Factor (NEF) of 2.84 and a Power Efficiency Factor (PEF) of 18.3. The split-voltage configuration improves power efficiency by nearly 25% compared to a full voltage supply and maintains a small area design. Action potentials of the medial and lateral giant fiber of an earthworm are recorded as an example application. Full article

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16 pages, 667 KiB

Open AccessArticle

Voltage Stacking: A First-Order Modelization of an m × n Asynchronous Array for Chip and Architectural Design Exploration

by Baudouin Chauviere and Kenneth S. Stevens

J. Low Power Electron. Appl. 2024, 14(3), 44; https://doi.org/10.3390/jlpea14030044 - 27 Aug 2024

Viewed by 736

Abstract

Voltage stacking is a technique in which multiple integrated circuits are stacked in series between the supply voltage instead of in parallel, thus improving the energy efficiency of the power distribution network. Unfortunately, voltage stacking presents stability challenges for integrated circuits within the [...] Read more.

Voltage stacking is a technique in which multiple integrated circuits are stacked in series between the supply voltage instead of in parallel, thus improving the energy efficiency of the power distribution network. Unfortunately, voltage stacking presents stability challenges for integrated circuits within the stack. A first-order model to quantify variability, stability, and power metrics for an array of voltage-stacked asynchronous integrated circuits is presented. Voltage variability and power consumption are accounted for and discussed. Limitations of the model are identified outside of the nominal behavior. The number of columns in the architecture, chip leakage, and supply voltage are shown to be the key contributors to the stability, performance, and energy efficiency of a system of voltage-stacked asynchronous processors. A higher leakage to active power ratio, though usually avoided by chip designers, is shown to improve stability and be key in designing stacks without external balancing. Outputs of the model enable system and chip designers to evaluate first-order trade-offs in energy efficiency, performance, and system cost. These fundamental data allow designers to make informed design and optimization trade-offs between asynchronous voltage-stacked architectures and the integrated circuits used therein. Analysis of this model shows that various voltage-stacked configurations, such as one with a 48 V supply using 100 rows and 11 columns, can be designed with less than 10% voltage variation per chip, mitigating the need for external voltage balancing. Full article

(This article belongs to the Special Issue Energy Aware Scientific Computing in Distributed Architectures, Low Power Processors and HPC Hybrid Systems)

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27 pages, 6837 KiB

Open AccessReview

Prospective Review of Magneto-Resistive Current Sensors with High Sensitivity and Wide Temperature Range

by Zicai Yang and Yanfeng Jiang

J. Low Power Electron. Appl. 2024, 14(3), 43; https://doi.org/10.3390/jlpea14030043 - 19 Aug 2024

Viewed by 989

Abstract

Current sensors play a vital role in power systems, industrial production, smart devices and other fields, which can provide critical current information in the systems for the safety and efficiency managements. The development of magneto-resistive effect technology in recent years expedites the research [...] Read more.

Current sensors play a vital role in power systems, industrial production, smart devices and other fields, which can provide critical current information in the systems for the safety and efficiency managements. The development of magneto-resistive effect technology in recent years expedites the research process of the current sensors in industrial-level applications. In the review, starting with the development status of the current sensors, the physical mechanisms of the relevant magneto-resistive effects and their early applications as the current sensors are introduced. Several design methods of the magnetic sensors, as well as their merits and shortcomings, are summarized. The performance parameters of the magnetic sensors based on AMR, GMR, TMR and Hall effects are reviewed, including the front-end amplification circuits and conditioning circuits. The industrial applications of the current sensors in the fields of automobiles and photovoltaic inverters are enumerated. The criterions for the current sensors to be used in different scenarios are discussed. In the future, it is imperative to continue the research and development of novel current sensors in order to satisfy the increasingly stringent demands of the industrial developments, in terms of the performance, cost and reliability of the current sensors. Full article

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19 pages, 6482 KiB

Open AccessArticle

Field-Programmable Gate Array Architecture for the Discrete Orthonormal Stockwell Transform (DOST) Hardware Implementation

by Martin Valtierra-Rodriguez, Jose-Luis Contreras-Hernandez, David Granados-Lieberman, Jesus Rooney Rivera-Guillen, Juan Pablo Amezquita-Sanchez and David Camarena-Martinez

J. Low Power Electron. Appl. 2024, 14(3), 42; https://doi.org/10.3390/jlpea14030042 - 7 Aug 2024

Viewed by 1238

Abstract

Time–frequency analysis is critical in studying linear and non-linear signals that exhibit variations across both time and frequency domains. Such analysis not only facilitates the identification of transient events and extraction of key features but also aids in displaying signal properties and pattern [...] Read more.

Time–frequency analysis is critical in studying linear and non-linear signals that exhibit variations across both time and frequency domains. Such analysis not only facilitates the identification of transient events and extraction of key features but also aids in displaying signal properties and pattern recognition. Recently, the Discrete Orthonormal Stockwell Transform (DOST) has become increasingly utilized in many specialized signal processing tasks. Given its growing importance, this work proposes a reconfigurable field-programmable gate array (FPGA) architecture designed to efficiently implement the DOST algorithm on cost-effective FPGA chips. An accompanying MATLAB app enables the automatic configuration of the DOST method for varying sizes (64, 128, 256, 512, and 1024 points). For the implementation, a Cyclone V series FPGA device from Intel Altera, featuring the 5CSEMA5F31C6N chip, is used. To provide a complete hardware solution, the proposed DOST core has been integrated into a hybrid ARM-HPS (Advanced RISC Machine–Hard Processor System) control unit, which allows the control of different peripherals, such as communication protocols and VGA-based displays. Results show that less than 5% of the chip’s resources are occupied, indicating a low-cost architecture that can be easily integrated into other FPGA structures or hardware systems for diverse applications. Moreover, the accuracy of the proposed FPGA-based implementation is underscored by a root mean squared error of 6.0155 × 10⁻³ when compared with results from floating-point processors, highlighting its accuracy. Full article

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15 pages, 4565 KiB

Open AccessArticle

A Gate-Level Power Estimation Approach with a Comprehensive Definition of Thresholds for Classification and Filtering of Inertial Glitch Pulses

by Benjamin Villegas and Ioannis Vourkas

J. Low Power Electron. Appl. 2024, 14(3), 41; https://doi.org/10.3390/jlpea14030041 - 5 Aug 2024

Viewed by 1055

Abstract

Estimation of power consumption in digital circuits is performed at gate-level simulation. Its accuracy depends on the models of gate delays that capture the effects of spurious signal transitions, called “glitches”. Electronic Design Automation (EDA) software considers inertial gate delays and represses a [...] Read more.

Estimation of power consumption in digital circuits is performed at gate-level simulation. Its accuracy depends on the models of gate delays that capture the effects of spurious signal transitions, called “glitches”. Electronic Design Automation (EDA) software considers inertial gate delays and represses a glitch in the cell’s output if its width is below a threshold. Selecting threshold values for the inertial glitch classification and filtering is crucial for precise power estimations. In this direction, we explore the effectiveness of automatically adjusting such thresholds on a cell-specific basis according to the local cell’s information. We used a commercial industry-standard gate-level power estimation tool and a 32 nm CMOS standard cell library. Via power measurements in circuit simulations, we created customized lookup tables for each library cell employed in the benchmark circuits. We compared the proposed approach’s performance with other methods for glitch threshold definition. Our method demonstrated good power estimation accuracy while presenting the lowest mean absolute error among all the cells of the circuits under test and the smallest standard deviation. The latter suggests that the proposed method achieves better cell-specific accuracy, which is expected to allow for more precise circuit-level power estimations in complex circuits with a large number of combinational cells. Full article

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17 pages, 6867 KiB

Open AccessArticle

A 0.5 V, 32 nW Compact Inverter-Based All-Filtering Response Modes Gm-C Filter for Bio-Signal Processing

by Ali Namdari, Orazio Aiello and Daniele D. Caviglia

J. Low Power Electron. Appl. 2024, 14(3), 40; https://doi.org/10.3390/jlpea14030040 - 4 Aug 2024

Viewed by 1082

Abstract

A low-power, low-voltage universal multi-mode Gm-C filter using a 180 nm TSMC technology node is presented in this paper. The proposed filter employs only three transconductance operational amplifiers (OTAs) operating in the sub-threshold region with a supply voltage of 0.5 V, resulting in [...] Read more.

A low-power, low-voltage universal multi-mode Gm-C filter using a 180 nm TSMC technology node is presented in this paper. The proposed filter employs only three transconductance operational amplifiers (OTAs) operating in the sub-threshold region with a supply voltage of 0.5 V, resulting in a power consumption of 32 nW. Moreover, without additional active elements, the proposed circuit can operate various functional modes, such as voltage, current, transconductance, and trans-resistance. The filter’s frequency, centered at 462 Hz, and a compact and low-power solution showing only 93.5 µVrms input-referred noise make the proposed filter highly suitable for bio-signal processing. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)

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14 pages, 706 KiB

Open AccessArticle

An Ultra-Low-Voltage Approach to Accurately Set the Quiescent Current of Digital Standard Cells Used for Analog Design and Its Application on an Inverter-Based Operational Transconductance Amplifier

by Riccardo Della Sala, Francesco Centurelli and Giuseppe Scotti

J. Low Power Electron. Appl. 2024, 14(3), 39; https://doi.org/10.3390/jlpea14030039 - 24 Jul 2024

Viewed by 1233

Abstract

An approach to design analog building blocks based on digital standard cells is presented in this work. By ensuring that every CMOS inverter from a standard-cell library operates with a well-defined quiescent current and output voltage, the suggested method makes it possible to [...] Read more.

An approach to design analog building blocks based on digital standard cells is presented in this work. By ensuring that every CMOS inverter from a standard-cell library operates with a well-defined quiescent current and output voltage, the suggested method makes it possible to construct analog circuits that are resistant against PVT variations. The method uses the local supply voltages connected to the source terminals of the p-channel and n-channel MOS transistors of the standard-cell inverters as control inputs. It is based on adaptive supply voltage generator (ASVG) reusable blocks, which are comparable to those used in digital applications to handle process variations. All of the standard-cell inverters used for analog functions receive the local supply voltages produced by the ASVGs, which enable setting each cell’s quiescent current to a multiple of a reference current and each cell’s static output voltage to an appropriate reference voltage. Both the complete custom design of the ASVG blocks and a theoretical study of the feedback loop of the ASVG are presented. An application example through the design of a fully synthesizable two-stage operational transconductance amplifier (OTA) is also provided. The TSMC 180 nm CMOS technology has been used to implement both the OTA and the ASV generators. Simulation results have demonstrated that the proposed approach allows to accurately set the quiescent current of standard-cell inverters, dramatically reducing the effect of PVT variations on the pmain performance parameters of the standard-cell-based two-stage OTA. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)

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20 pages, 8695 KiB

Open AccessArticle

A 0.064 mm² 16-Channel In-Pixel Neural Front End with Improved System Common-Mode Rejection Exploiting a Current-Mode Summing Approach

by Giovanni Nicolini, Alessandro Fava, Francesco Centurelli and Giuseppe Scotti

J. Low Power Electron. Appl. 2024, 14(3), 38; https://doi.org/10.3390/jlpea14030038 - 13 Jul 2024

Viewed by 916

Abstract

In this work, we introduce the design of a 16-channel in-pixel neural analog front end that employs a current-based summing approach to establish a common-mode feedback loop. The primary aim of this novel structure is to enhance both the system common-mode rejection ratio [...] Read more.

In this work, we introduce the design of a 16-channel in-pixel neural analog front end that employs a current-based summing approach to establish a common-mode feedback loop. The primary aim of this novel structure is to enhance both the system common-mode rejection ratio (SCMRR) and the common-mode interference (CMI) range. Compared to more conventional designs, the proposed front end utilizes DC-coupled inverter-based main amplifiers, which significantly reduce the occupied on-chip area. Additionally, the current-based implementation of the CMFB loop obviates the need for voltage buffers, replacing them with simple common-gate transistors, which, in turn, decreases both area occupancy and power consumption. The proposed architecture is further examined from an analytical standpoint, providing a comprehensive evaluation through design equations of its performance in terms of gain, common-mode rejection, and noise power. A 50

μ

m × 65

μ

m compact layout of the pixel amplifiers that make up the recording channels of the front end was designed using a 180 nm CMOS process. Simulations conducted in Cadence Virtuoso reveal an SCMRR of 80.5 dB and a PSRR of 72.58 dB, with a differential gain of 44 dB and a bandwidth that fully encompasses the frequency range of the bio-signals that can be theoretically captured by the neural probe. The noise integrated in the range between 1 Hz and 7.5 kHz results in an input-referred noise (IRN) of 4.04

μ V_{r m s}

. Power consumption is also tested, with a measured value of 3.77

μ

W per channel, corresponding to an overall consumption of about 60

μ

W. To test its robustness with respect to PVT and mismatch variations, the front end is evaluated through extensive parametric simulations and Monte Carlo simulations, revealing favorable results. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)

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14 pages, 7409 KiB

Open AccessArticle

A 1.87 µW Capacitively Coupled Chopper Instrumentation Amplifier with a 0.36 mV Output Ripple and a 1.8 GΩ Input Impedance for Biomedical Recording

by Xuan Phuong Tran, Xuan Thuc Kieu, Xuan Thanh Pham, Duy Phong Pham and Manh Kha Hoang

J. Low Power Electron. Appl. 2024, 14(3), 37; https://doi.org/10.3390/jlpea14030037 - 10 Jul 2024

Viewed by 1022

Abstract

Chopper and capacitively coupled techniques are employed in instrumentation amplifiers to create capacitively coupled chopper instrumentation amplifiers (CCIAs) that obtain a high noise power efficiency. However, the CCIA has some disadvantages due to the chopper technique, namely chopper ripple and a low input [...] Read more.

Chopper and capacitively coupled techniques are employed in instrumentation amplifiers to create capacitively coupled chopper instrumentation amplifiers (CCIAs) that obtain a high noise power efficiency. However, the CCIA has some disadvantages due to the chopper technique, namely chopper ripple and a low input impedance. The amplifier can easily saturate due to the chopper ripple of the CCIA, especially in extremely low noise problems. Therefore, ripple attenuation is required when designing CCIAs. To record biomedical information, a CCIA with a low power consumption and a low noise, low output ripple, and high input impedance (Z_in) is presented in this paper. By introducing a ripple attenuation loop (RAL) including the chopping offset amplifier and a low pass filter, the chopping ripple can be reduced to 0.36 mV. To increase the Z_in of the CCIA up to 1.8 GΩ, an impedance boost loop (IBL) is added. By using 180 nm CMOS technology, the 0.123 mm² CCIA consumes 1.87 µW at a supply voltage of 1 V. According to the simulation results using Cadance, the proposed CCIA architecture achieves a noise floor of 136 nV/√Hz, an input-referred noise (IRN) of 2.16 µV_rms, a closed-loop gain of 40 dB, a power supply rejection ratio (PSRR) of 108.6 dB, and a common-mode rejection ratio (CMRR) of 118.7 dB. The proposed CCIA is a helpful method for monitoring neural potentials. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)

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12 pages, 9693 KiB

Open AccessArticle

0.35 V Subthreshold Bulk-Driven CMOS Second-Generation Current Conveyor

by Muhammad Omer Shah, Manfredi Caruso and Salvatore Pennisi

J. Low Power Electron. Appl. 2024, 14(3), 36; https://doi.org/10.3390/jlpea14030036 - 7 Jul 2024

Viewed by 890

Abstract

This study describes a high-performance second-generation Current Conveyor (CCII) operating at 0.35 V and achieving rail-to-rail operation at the Y terminal and class AB current drive at the X and Z terminals. The solution utilizes a low-voltage subthreshold bulk-driven CMOS OTA that was [...] Read more.

This study describes a high-performance second-generation Current Conveyor (CCII) operating at 0.35 V and achieving rail-to-rail operation at the Y terminal and class AB current drive at the X and Z terminals. The solution utilizes a low-voltage subthreshold bulk-driven CMOS OTA that was experimentally developed earlier, making systematic use of body terminals to improve small-signal and large-signal performance. The circuit has a high open-loop voltage gain and uses cascoded current mirror topologies, resulting in precise voltage and current transfer with bandwidths of 1.33 MHz and 2.13 MHz, respectively. The CCII offers a linear current drive up to 2.5 µA while consuming a total quiescent current of 2.86 µA (758 nA in the output branches), displaying one the highest figures of merit in terms of current utilization for sub 1 V solutions. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)

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12 pages, 1048 KiB

Open AccessArticle

Spin–Orbit Coupling Free Nonlinear Spin Hall Effect in a Triangle-Unit Collinear Antiferromagnet with Magnetic Toroidal Dipole

by Satoru Hayami

J. Low Power Electron. Appl. 2024, 14(3), 35; https://doi.org/10.3390/jlpea14030035 - 3 Jul 2024

Viewed by 1045

Abstract

We investigate emergent conductive phenomena triggered by collinear antiferromagnetic orderings. We show that an up-down-zero spin configuration in a triangle cluster leads to linear and nonlinear spin conductivities even without the relativistic spin–orbit coupling; the linear spin conductivity is Drude-type, while the nonlinear [...] Read more.

We investigate emergent conductive phenomena triggered by collinear antiferromagnetic orderings. We show that an up-down-zero spin configuration in a triangle cluster leads to linear and nonlinear spin conductivities even without the relativistic spin–orbit coupling; the linear spin conductivity is Drude-type, while the nonlinear spin conductivity has Hall-type characterization. We demonstrate the emergence of both spin conductivities in a breathing kagome system consisting of a triangle cluster. The nonlinear spin conductivity becomes larger than the linear one when the Fermi level lies near the region where a small partial band gap opens. Our results indicate that collinear antiferromagnets with triangular geometry give rise to rich spin conductive phenomena. Full article

(This article belongs to the Special Issue Recent Advances in Spintronics)

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10 pages, 2548 KiB

Open AccessArticle

Design and Analysis of Self-Tanked Stepwise Charging Circuit for Four-Phase Adiabatic Logic

by William Morell and Jin-Woo Choi

J. Low Power Electron. Appl. 2024, 14(3), 34; https://doi.org/10.3390/jlpea14030034 - 27 Jun 2024

Viewed by 920

Abstract

Adiabatic logic has been proposed as a method for drastically reducing power consumption in specialized low-power circuits. They often require specialized clock drivers that also function as the main power supply, in contrast to standard CMOS logic, and these power clocks are often [...] Read more.

Adiabatic logic has been proposed as a method for drastically reducing power consumption in specialized low-power circuits. They often require specialized clock drivers that also function as the main power supply, in contrast to standard CMOS logic, and these power clocks are often a point of difficulty in the design process. A novel, stepwise charging driver circuit for four-phase adiabatic logic is proposed and validated through a simulation study. The proposed circuit consists of two identical driver circuits each driving two opposite adiabatic logic phases. Its performance relative to ideal step-charging and a standard CMOS across mismatched phase loads is analyzed, and new best practices are established. It is compared to a reference circuit consisting of one driver circuit for each phase along with a paired on-chip tank capacitor. The proposed driver uses opposite logic phases to act as the tank capacitor for each other in a “self-tanked” fashion. Each circuit was simulated in 15 nm FinFET across a variety of frequencies for an arbitrary logic operation. Both circuits showed comparable power consumption at all frequencies tested, yet the proposed driver uses fewer transistors and control signals and eliminates the explicit tank capacitors entirely, vastly reducing circuit area, complexity, and development time. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)

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J. Low Power Electron. Appl., Volume 14, Issue 3 (September 2024) – 13 articles

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