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Ultra-Low-Power ICs for the Internet of Things Vol. 2

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A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: 30 November 2024 | Viewed by 23087

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Dr. Orazio Aiello

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Department of Electrical, Electronic, Telecommunications Engineering and Naval Architecture (DITEN), University of Genoa, Via Opera Pia 11a, I-16145 Genova, Italy
Interests: energy-efficient integrated circuit design; mostly digital/synthesizable interfaces; ultra-low-power ICs for the Internet of Things (IoT); ultra-low-voltage and voltage scalable ICs
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Dear Colleagues,

Ultra-low-voltage/power analog and digital ICs, powered by energy harvesters, face the challenges of small area occupation, low design effort, and technology/design portability, which are needed in this Internet-of-Things (IoT) era, which, in itself, has experienced exponential growth in relation to interconnected sensor nodes.

In this framework, the aim of this Special Issue is to attract original research articles related to the design and application of ultra-low-voltage/power, digital-based, and fully synthesizable ICs.

The topics of this Special Issue include but are not limited to

Ultra-low-power interfaces for the Internet of Things: energy-efficient and power/voltage scalable, analog, and mixed-signal IC;
Inverter- and digital-based design methodologies of ultra-low power ICs;
IC solution for ultra-low-voltage, energy and standby power consumption systems;
Automated design methodology to decrease the time-to-market;
Energy harvesting and power management circuit for IoT devices;
Ultra-low-power/voltage ICs for instrumentation and communication applications.

Dr. Orazio Aiello
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

ultra-low-power/voltage ICs for IoT applications
advancements in energy-aware design techniques
ultra-low-power front-end electronics
energy-efficient ICs
digital-based design methodologies
ultra-low-power sensors and energy-neutral devices
energy harvesting and power management circuit

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Related Special Issue

Ultra-Low-Power ICs for the Internet of Things in Journal of Low Power Electronics and Applications (15 articles)

Published Papers (12 papers)

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Research

Jump to: Review

17 pages, 6867 KiB

Open AccessArticle

A 0.5 V, 32 nW Compact Inverter-Based All-Filtering Response Modes Gm-C Filter for Bio-Signal Processing

by Ali Namdari, Orazio Aiello and Daniele D. Caviglia

J. Low Power Electron. Appl. 2024, 14(3), 40; https://doi.org/10.3390/jlpea14030040 - 4 Aug 2024

Viewed by 1092

Abstract

A low-power, low-voltage universal multi-mode Gm-C filter using a 180 nm TSMC technology node is presented in this paper. The proposed filter employs only three transconductance operational amplifiers (OTAs) operating in the sub-threshold region with a supply voltage of 0.5 V, resulting in a power consumption of 32 nW. Moreover, without additional active elements, the proposed circuit can operate various functional modes, such as voltage, current, transconductance, and trans-resistance. The filter’s frequency, centered at 462 Hz, and a compact and low-power solution showing only 93.5 µVrms input-referred noise make the proposed filter highly suitable for bio-signal processing. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)

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14 pages, 706 KiB

Open AccessArticle

An Ultra-Low-Voltage Approach to Accurately Set the Quiescent Current of Digital Standard Cells Used for Analog Design and Its Application on an Inverter-Based Operational Transconductance Amplifier

by Riccardo Della Sala, Francesco Centurelli and Giuseppe Scotti

J. Low Power Electron. Appl. 2024, 14(3), 39; https://doi.org/10.3390/jlpea14030039 - 24 Jul 2024

Viewed by 1251

Abstract

An approach to design analog building blocks based on digital standard cells is presented in this work. By ensuring that every CMOS inverter from a standard-cell library operates with a well-defined quiescent current and output voltage, the suggested method makes it possible to construct analog circuits that are resistant against PVT variations. The method uses the local supply voltages connected to the source terminals of the p-channel and n-channel MOS transistors of the standard-cell inverters as control inputs. It is based on adaptive supply voltage generator (ASVG) reusable blocks, which are comparable to those used in digital applications to handle process variations. All of the standard-cell inverters used for analog functions receive the local supply voltages produced by the ASVGs, which enable setting each cell’s quiescent current to a multiple of a reference current and each cell’s static output voltage to an appropriate reference voltage. Both the complete custom design of the ASVG blocks and a theoretical study of the feedback loop of the ASVG are presented. An application example through the design of a fully synthesizable two-stage operational transconductance amplifier (OTA) is also provided. The TSMC 180 nm CMOS technology has been used to implement both the OTA and the ASV generators. Simulation results have demonstrated that the proposed approach allows to accurately set the quiescent current of standard-cell inverters, dramatically reducing the effect of PVT variations on the pmain performance parameters of the standard-cell-based two-stage OTA. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)

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20 pages, 8695 KiB

Open AccessArticle

A 0.064 mm² 16-Channel In-Pixel Neural Front End with Improved System Common-Mode Rejection Exploiting a Current-Mode Summing Approach

by Giovanni Nicolini, Alessandro Fava, Francesco Centurelli and Giuseppe Scotti

J. Low Power Electron. Appl. 2024, 14(3), 38; https://doi.org/10.3390/jlpea14030038 - 13 Jul 2024

Viewed by 928

Abstract

In this work, we introduce the design of a 16-channel in-pixel neural analog front end that employs a current-based summing approach to establish a common-mode feedback loop. The primary aim of this novel structure is to enhance both the system common-mode rejection ratio (SCMRR) and the common-mode interference (CMI) range. Compared to more conventional designs, the proposed front end utilizes DC-coupled inverter-based main amplifiers, which significantly reduce the occupied on-chip area. Additionally, the current-based implementation of the CMFB loop obviates the need for voltage buffers, replacing them with simple common-gate transistors, which, in turn, decreases both area occupancy and power consumption. The proposed architecture is further examined from an analytical standpoint, providing a comprehensive evaluation through design equations of its performance in terms of gain, common-mode rejection, and noise power. A 50

μ

m × 65

μ

m compact layout of the pixel amplifiers that make up the recording channels of the front end was designed using a 180 nm CMOS process. Simulations conducted in Cadence Virtuoso reveal an SCMRR of 80.5 dB and a PSRR of 72.58 dB, with a differential gain of 44 dB and a bandwidth that fully encompasses the frequency range of the bio-signals that can be theoretically captured by the neural probe. The noise integrated in the range between 1 Hz and 7.5 kHz results in an input-referred noise (IRN) of 4.04

μ V_{r m s}

. Power consumption is also tested, with a measured value of 3.77

μ

W per channel, corresponding to an overall consumption of about 60

μ

W. To test its robustness with respect to PVT and mismatch variations, the front end is evaluated through extensive parametric simulations and Monte Carlo simulations, revealing favorable results. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)

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14 pages, 7409 KiB

Open AccessArticle

A 1.87 µW Capacitively Coupled Chopper Instrumentation Amplifier with a 0.36 mV Output Ripple and a 1.8 GΩ Input Impedance for Biomedical Recording

by Xuan Phuong Tran, Xuan Thuc Kieu, Xuan Thanh Pham, Duy Phong Pham and Manh Kha Hoang

J. Low Power Electron. Appl. 2024, 14(3), 37; https://doi.org/10.3390/jlpea14030037 - 10 Jul 2024

Viewed by 1034

Abstract

Chopper and capacitively coupled techniques are employed in instrumentation amplifiers to create capacitively coupled chopper instrumentation amplifiers (CCIAs) that obtain a high noise power efficiency. However, the CCIA has some disadvantages due to the chopper technique, namely chopper ripple and a low input impedance. The amplifier can easily saturate due to the chopper ripple of the CCIA, especially in extremely low noise problems. Therefore, ripple attenuation is required when designing CCIAs. To record biomedical information, a CCIA with a low power consumption and a low noise, low output ripple, and high input impedance (Z_in) is presented in this paper. By introducing a ripple attenuation loop (RAL) including the chopping offset amplifier and a low pass filter, the chopping ripple can be reduced to 0.36 mV. To increase the Z_in of the CCIA up to 1.8 GΩ, an impedance boost loop (IBL) is added. By using 180 nm CMOS technology, the 0.123 mm² CCIA consumes 1.87 µW at a supply voltage of 1 V. According to the simulation results using Cadance, the proposed CCIA architecture achieves a noise floor of 136 nV/√Hz, an input-referred noise (IRN) of 2.16 µV_rms, a closed-loop gain of 40 dB, a power supply rejection ratio (PSRR) of 108.6 dB, and a common-mode rejection ratio (CMRR) of 118.7 dB. The proposed CCIA is a helpful method for monitoring neural potentials. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)

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12 pages, 9693 KiB

Open AccessArticle

0.35 V Subthreshold Bulk-Driven CMOS Second-Generation Current Conveyor

by Muhammad Omer Shah, Manfredi Caruso and Salvatore Pennisi

J. Low Power Electron. Appl. 2024, 14(3), 36; https://doi.org/10.3390/jlpea14030036 - 7 Jul 2024

Viewed by 902

Abstract

This study describes a high-performance second-generation Current Conveyor (CCII) operating at 0.35 V and achieving rail-to-rail operation at the Y terminal and class AB current drive at the X and Z terminals. The solution utilizes a low-voltage subthreshold bulk-driven CMOS OTA that was experimentally developed earlier, making systematic use of body terminals to improve small-signal and large-signal performance. The circuit has a high open-loop voltage gain and uses cascoded current mirror topologies, resulting in precise voltage and current transfer with bandwidths of 1.33 MHz and 2.13 MHz, respectively. The CCII offers a linear current drive up to 2.5 µA while consuming a total quiescent current of 2.86 µA (758 nA in the output branches), displaying one the highest figures of merit in terms of current utilization for sub 1 V solutions. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)

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10 pages, 2548 KiB

Open AccessArticle

Design and Analysis of Self-Tanked Stepwise Charging Circuit for Four-Phase Adiabatic Logic

by William Morell and Jin-Woo Choi

J. Low Power Electron. Appl. 2024, 14(3), 34; https://doi.org/10.3390/jlpea14030034 - 27 Jun 2024

Viewed by 928

Abstract

Adiabatic logic has been proposed as a method for drastically reducing power consumption in specialized low-power circuits. They often require specialized clock drivers that also function as the main power supply, in contrast to standard CMOS logic, and these power clocks are often a point of difficulty in the design process. A novel, stepwise charging driver circuit for four-phase adiabatic logic is proposed and validated through a simulation study. The proposed circuit consists of two identical driver circuits each driving two opposite adiabatic logic phases. Its performance relative to ideal step-charging and a standard CMOS across mismatched phase loads is analyzed, and new best practices are established. It is compared to a reference circuit consisting of one driver circuit for each phase along with a paired on-chip tank capacitor. The proposed driver uses opposite logic phases to act as the tank capacitor for each other in a “self-tanked” fashion. Each circuit was simulated in 15 nm FinFET across a variety of frequencies for an arbitrary logic operation. Both circuits showed comparable power consumption at all frequencies tested, yet the proposed driver uses fewer transistors and control signals and eliminates the explicit tank capacitors entirely, vastly reducing circuit area, complexity, and development time. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)

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17 pages, 2747 KiB

Open AccessArticle

A Sub-1-V Nanopower MOS-Only Voltage Reference

by Siqi Wang, Zhenghao Lu, Kunpeng Xu, Hongguang Dai, Zhanxia Wu and Xiaopeng Yu

J. Low Power Electron. Appl. 2024, 14(1), 13; https://doi.org/10.3390/jlpea14010013 - 29 Feb 2024

Viewed by 2347

Abstract

A novel low-power MOS-only voltage reference is presented. The Enz–Krummenacher–Vittoz (EKV) model is adopted to provide a new perspective on the operating principle. The normalized charge density, introduced as a new variable, serves as an indicator when trimming the output temperature coefficient. The proposed voltage reference consists of a specific current generator and a 5-bit trimmable load. Thanks to the good match between the current source stage and the output stage, the nonlinear temperature dependence of carrier mobility is automatically canceled out. The circuit is designed using 55 nm COMS technology. The operating temperature ranges from −40

°

C to 120

°

C. The average temperature coefficient of the output voltage can be reduced to 21.7 ppm/

°

C by trimming. The power consumption is only 23.2 nW with a supply voltage of 0.8 V. The line sensitivity and the power supply rejection ratio at 100 Hz are 0.011 %/V and −89 dB, respectively. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)

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9 pages, 3852 KiB

Open AccessCommunication

Design of a Low-Power Delay-Locked Loop-Based 8× Frequency Multiplier in 22 nm FDSOI

by Naveed and Jeff Dix

J. Low Power Electron. Appl. 2023, 13(4), 64; https://doi.org/10.3390/jlpea13040064 - 12 Dec 2023

Cited by 1 | Viewed by 2335

Abstract

A low-power delay-locked loop (DLL)-based frequency multiplier is presented. The multiplier is designed in 22 nm FDSOI and achieves 8× multiplication. The proposed DLL uses a new simple duty cycle correction circuit and is XOR logic-based for frequency multiplication. Current starved delay cells are used to make the circuit power efficient. The circuit uses three 2× stages instead of an edge combiner to achieve 8× multiplication, thus requiring far less power and chip area as compared to conventional phase-locked loop (PLL) circuits. The proposed 8× multiplier occupies an active area of 0.09 mm². The measurement result shows ultra-low power consumption of 130 µW at 0.8 V supply. The post-layout simulation shows a timing jitter of 24 ps (pk-pk) at 2.44 GHz. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)

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21 pages, 4797 KiB

Open AccessArticle

Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology

by Muhammad Faisal Siddiqui, Mukesh Kumar Maheshwari, Muhammad Raza and Aurangzeb Rashid Masud

J. Low Power Electron. Appl. 2023, 13(4), 54; https://doi.org/10.3390/jlpea13040054 - 7 Oct 2023

Cited by 2 | Viewed by 3508

Abstract

This article presents the design and optimization of a tunable quadrature differential LC CMOS voltage-controlled oscillator (VCO) with a D flip-flop (DFF) frequency divider. The VCO is designed for the low-power and low-phase-noise applications of 2.4 GHz IoT/BLE receivers and wireless sensor devices. The proposed design comprises the proper stacking of an LC VCO and a DFF frequency divider and is simulated using a TSMC 65 nm CMOS technology, and it has a tuning range of 4.4 to 5.7 GHz. The voltage headroom is preserved using a high-impedance on-chip passive inductor at the tail for filtering and enabling true differential operation. The VCO and frequency divider consume as low as 2.02 mW altogether, with the VCO section consuming only 0.47 mW. The active area of the chip including the pads is only 0.47 mm². The designed VCO achieved a much better phase noise of −118.36 dBc/Hz at a 1 MHz offset frequency with 1.2 V supply voltages. The design produced a much better FoM of −196.44 dBc/Hz compared to other related research. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)

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15 pages, 10415 KiB

Open AccessArticle

A Power-Gated 8-Transistor Physically Unclonable Function Accelerates Evaluation Speeds

by Yujin Zheng, Alex Yakovlev and Alex Bystrov

J. Low Power Electron. Appl. 2023, 13(4), 53; https://doi.org/10.3390/jlpea13040053 - 29 Sep 2023

Cited by 1 | Viewed by 1890

Abstract

The proposed 8-Transistor (8T) Physically Unclonable Function (PUF), in conjunction with the power gating technique, can significantly accelerate a single evaluation cycle more than 100,000 times faster than a 6-Transistor (6T) Static Random-Access Memory (SRAM) PUF. The 8T PUF is built to swiftly eliminate data remanence and maximise physical mismatch. Moreover, a two-phase power gating module is devised to provide controllable power on/off cycles for the chosen PUF clusters in order to facilitate fast statistical measurements and curb the in-rush current. The architecture and hardware implementation of the power-gated PUF are developed to accommodate fast multiple evaluations of PUF Responses. The fast speed enables a new data processing method, which coordinates Dark-bit masking and Multiple Temporal Majority Voting (TMV) in different Process, Voltage and Temperature (PVT) corners or during field usage, hence greatly reducing the Bit Error Rate (BER) and the hardware penalty for error correction. The designs are based on the UMC 65 nm technology and aim to tape out an Application-Specific Integrated Circuit (ASIC) chip. Post-layout Monte Carlo (MC) simulations are performed with Cadence, and the extracted PUF Responses are processed with Matlab to evaluate the 8T PUF performance and statistical metrics for subsequent inclusion in PUF Responses, which comprise the novelty of this approach. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)

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12 pages, 5396 KiB

Open AccessArticle

Ultra-Low Power Programmable Bandwidth Capacitively-Coupled Chopper Instrumentation Amplifier Using 0.2 V Supply for Biomedical Applications

by Xuan Thanh Pham, Xuan Thuc Kieu and Manh Kha Hoang

J. Low Power Electron. Appl. 2023, 13(2), 37; https://doi.org/10.3390/jlpea13020037 - 24 May 2023

Cited by 3 | Viewed by 2268

Abstract

This paper presents a capacitively coupled chopper instrumentation amplifier (CCIA) with ultra-low power consumption and programmable bandwidth for biomedical applications. To achieve a flexible bandwidth from 0.2 to 10 kHz without additional power consumption, a programmable Miller compensation technique was proposed and used in the CCIA. By using a Squeezed inverter amplifier (SQI) that employs a 0.2-V supply, the proposed CCIA addresses the primary noise source in the first stage, resulting in high noise power efficiency. The proposed CCIA is designed using a 0.18 µm CMOS technology process and has a chip area of 0.083 mm². With a power consumption of 0.47 µW at 0.2 and 0.8 V supply, the proposed amplifier architecture achieves a thermal noise of 28 nV/√Hz, an input-related noise (IRN) of 0.9 µV_rms, a closed-loop gain (A_V) of 40 dB, a power supply rejection ratio (PSRR) of 87.6 dB, and a common-mode rejection ratio (CMRR) of 117.7 dB according to post-simulation data. The proposed CCIA achieves a noise efficiency factor (NEF) of 1.47 and a power efficiency factor (PEF) of 0.56, which allows comparison with the latest research results. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)

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Review

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20 pages, 377 KiB

Open AccessReview

A Survey of Short-Range Wireless Communication for Ultra-Low-Power Embedded Systems

by Billy Baker, John Woods, Martin J. Reed and Martin Afford

J. Low Power Electron. Appl. 2024, 14(2), 27; https://doi.org/10.3390/jlpea14020027 - 14 May 2024

Cited by 1 | Viewed by 2713

Abstract

Wireless short-range communication has become widespread in the modern era, partly due to the advancement of the Internet of Things (IoT) and smart technology. This technology is now utilized in various sectors, including lighting, medical, and industrial applications. This article aims to examine the historical, present, and forthcoming advancements in wireless short-range communication. Additionally, the review will analyze the modifications made to communication protocols, such as Bluetooth, RFID and NFC, in order to better accommodate modern applications. Batteryless technology, particularly batteryless NFC, is an emerging development in short-range wireless communication that combines power and data transmission into a single carrier. This modification will significantly influence the trajectory of short-range communication and its applications. The foundation of most low-power, short-range communication applications relies on an ultra-low-power microcontroller. Therefore, this study will encompass an analysis of ultra-low-power microcontrollers and an investigation into the potential limitations they might encounter in the future. In addition to offering a thorough examination of current Wireless short-range communication, this article will also attempt to forecast future patterns and identify possible obstacles that future research may address. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)

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