Evaluation of the Efficiency Performance of 3-Phase, 6-Switch PFC Circuit Based on the Used 1.2 kV SiC Transistor

Abstract

This paper evaluates the performance of the high-voltage wide-band gap SiC power transistors equipped within 3-phase bridgeless 3 kW PFC circuit. The main aim of the study is the experimental evaluation of the dynamic properties and driving power requirements of the transistors, for which the parameters are similar. These are competing products from different manufacturers, while the selection criterion was the same type of package technology (7 pin D2PAK). Second, the effect of the transistor type was analysed in terms of the performance efficiency of the PFC circuit. Within the analysis, the driver circuit was constructed first, and adapted to high voltage transistor driving. During individual measurements, the driver remained the same, while gate-driver losses were analysed for individual transistors. The obtained results reveal differences related to requirements on driving power, as well as to the dynamics of transistors themselves. At the end of the paper, the evaluation of efficiency for different operating conditions of a constructed PFC converter is realized. The obtained results provide a more detailed overview of the dynamic properties of transistors and their impact on the resulting efficiency of the main circuit also in terms of driving requirements.

1. Introduction

The huge growth of ICT, electromobility, renewables, industrial technologies, data centers and data storage increases the daily demands on the electricity supply. In connection with the increase in the level of electronics in all consumer and industrial sectors, alongside the demand for electricity, the phenomenon concerning its quality is important. At present, due to the availability of electricity, the 1-phase or three-phase distribution network distribution is mainly used. However, most electrical equipment requires one-way distribution, which must be adapted accordingly. For this reason, most devices are equipped with an AC/DC converter that allows the devices to connect directly to the network. High efficiency and power factor are important features of these converters [1,2,3,4,5].

If we focus on the power supply concept of most industrial or consumer devices, it can be block-arranged in the configuration shown in Figure 1. In general, the description of this structure can be divided into a filter, a rectifier and a power factor correction circuit also providing a constant voltage in the DC circuit. After the PFC converters, there are then additional DC/DC stages providing the required voltage levels for the connected devices. However, the above-mentioned power supply concept (Figure 1) currently represents a solution that has been known for decades. However, it should be noted that the research of circuit topologies of individual stages of the mentioned concept is constantly improving and being perfected. Our discussion concerns a circuit solution, but also a technological one, specifically in terms of the production of semiconductor elements or magnetic components [6,7,8,9].

If we now focus specifically on circuit solutions, we will deal in more detail with the possibilities of solving the input element, i.e., the PFC converter. For the past few decades, various bridgeless boost PFC converters have been proposed. Many topologies based on basic bridgeless PFC have a common mode (CM) noise problem due to the floating input voltage. Dual-boost bridgeless PFC with the returned diode can avoid the CM noise problem. Totem-pole bridgeless boost PFC has a smaller CM noise than other bridgeless topologies, because the input is clamped to the output by diodes during each half-line cycle. Additionally, it has a small number of circuit elements. However, due to the poor reverse recovery characteristic of intrinsic body diode in general MOSFET switch, the use of the totem-pole bridgeless boost PFC has been limited to continuous conduction mode (CCM) operations. Depending on the application, devices might be rated from a few Watts to megawatts of power. Standard IEC 61000-3-2 defines the harmonic limits for the equipment input current up to 16 A per phase, i.e., for up to 10 kW of power for a three-phase equipment. When solving the main circuit of 3-phase connections of PFC converters, we also come across various configurations [10,11]. A long-known solution is the standard PFC boost connection in cooperation with a 3-phase rectifier. A potential improvement in the properties of this standard PFC converter lies in the so-called interleaved solution. With the advent of single-phase bridgeless topologies, a similar phenomenon can be registered in three-phase connections. The most widespread and most used solution is the so-called 6-switch 3-phase PFC converter in bridge connection, thanks to the development and advent of new generations of SiC transistors [12,13,14,15,16,17,18].

Considering the technological development of wide-bandgap components, it can be noted that SiC technology has held a relatively stable place in terms of the choice of semiconductor components in high-performance electronic systems. Manufacturers have a wide portfolio of these elements, while the differences in electrical properties are mainly due to technological know-how [19,20,21].

In this paper, the main research focus is on the analysis of the operational performance of selected SiC transistors within the main circuit of a 6-switch 3-phase PFC converter. Parameters of transistors are similar, including type of the package, so here we conduct an evaluation of competing products from different manufacturers. Similar studies have not been conducted, while the evaluation of the performance between Si, SiC and GaN type semiconductors has been provided [22,23,24,25]. The requirements for driving power as well as for the evaluation of loss ratios of selected transistor structures are evaluated. At the end of the article, attention is paid to the analysis of the efficiency of the proposed PFC converter, for different variants of the transistors used.

2. 3-Phase Bridgeless PFC Converter

A conventional 3-phase 6-switch PFC converter is depicted on Figure 2. The circuit schematic here also consists of additional circuits such as:

• EMI line filter, which is responsible for EMC compatibility relates to connected devices on the DC side of the converter.
• Damping circuit composed of shunt resistors and compensation capacitors connected to the EMI line filter.
• PFC boost inductor also forming part of the sinusoidal LCL filter together with previously described components.
• Main circuit of 6-switch 3-phase PFC converter together with DC-link filtering capacitor.
• Sensing devices for monitoring the values of voltages and currents withing the main circuit.
• Control unit with Gate drive circuits.

Nominal operational input/output parameters of PFC converter subjected to evaluation of SiC transistors performance are as follows:

• Input voltage = 3 × 230 Vac RMS Vdc
• Output voltage = 400 Vdc/800 Vdc
• Nominal power = 3 kW

For above mentioned parameters, the required main circuit components have been calculated and selected as well. Here, we are discussing about input PFC inductors, and output capacitor filters.

• The value of DC link capacitor = 1 mF
• PFC inductance = 670 μH

The physical prototype of experimental sample of proposed PFC converter is shown on Figure 3.

Driver Selection and Circuit Configuration

The UCC21521 is an isolated dual-channel gate driver with a 4-A source and 6-A sink peak current (Figure 4). It is designed to drive power MOSFETs, IGBTs, and SiC MOSFETs up to 5-MHz with an optimal propagation delay and pulse-width distortion. It uses a 5.7 kV isolation capacitive driver, which is one of the conditional features of a driving circuit for the defined operational conditions of the proposed 3-phase PFC converter.

Figure 5 presents the circuit schematic of the output stage of the utilized driver for one leg/phase of the PFC converter. The additional circuitry connected to the pins VDDA, OUTA, VSSA and VDDB, OUTB and VSSB, respectively, is responsible for formation of the −3V up to +13V of the driving V_GS signal. The required voltage supply for the driver ICs is realized with the use of independent DC/DC galvanically isolated converters.

Figure 6 displays a physical prototype of the driving board for the proposed 3-phase PFC converter, listing the identification of the main operational parts of this driving board.

3. Configuration of Experimental Set-Up

The procedure for testing was performed under laboratory conditions (Figure 7). Experimental measurements were performed with calibrated laboratory equipment from renowned manufacturers such as Tektronix, Elektro-Automatik, Zimmer and Chroma. A block diagram of the experimental test-bench is shown on Figure 8.

The 3-phase programmable AC source Chroma 61,505 was used as an input source of the tested power converter. The change of the output power was performed by electronic load EA-ELR 91000-30 3U. Measurements related to the efficiency evaluation were obtained via the evaluation of effective values of the input (Zimmer LMG 500) and output variables, i.e., voltages and currents. This was performed by Fluke 45 (output ammeter) and Agilent 34401A (output voltmeter). The base accuracy of LMG 500 is 0.015% of the reading and has a 0.01% range, thus the total measuring error is 0.025%. This allows for a correct measurement of the very low currents in the 32A range. Agilent 34,401 has basic accuracy on the level of 0.0035%, while Fluke 45 reaches an accuracy 0.2% of the measurements within the DC current range of 10 A.

Time waveforms were recorded with the use of the oscilloscope Textronix MDO3034 equipped with voltage and current probes from Tektronix (TM503 + A6302, P5200A). List of used laboratory equipment is given in

Table 1. Type designation of used laboratory equipment.

Laboratory Equipment	Part Number
Power supply	Chroma 61505
Electronic load	EA-ELR 91000-30 3U
Input power meter	Zimmer LMG500
Output ammeter	Fluke 45
Output voltmeter	Agilent 34401A
Osciloscope	MDO3034

.

4. Selection Criterions on Power Transistor

The right selection of semiconductor devices in power converters is an essential design issue for proper operation. Nowadays, there are many varieties to choose the right semiconductor technology from, so as to obtain optimal characteristic parameters for target application. The design of the power converter is a complex process, but some widely used design techniques are commonly known. Within the first design steps, it is necessary to evaluate all aspects of the final electronic device, such as the expected performance, voltages, currents and, to assess the economical and size aspects to choose optimal semiconductor technology. Furthermore, the design process starts with the selection of optimal semiconductor technology, which is necessary for the requested parameters of converter system.

Since the designed converter will be supplied with middle type voltages AC 3 × 230 V and the output of the converter is 400–800 Vdc with a middle range of power output (3 kW), the semiconductor technologies from right side of flowchart seems to be optimal for this design (Figure 9). Additional PFC converter properties are related to reliability and favourable power density, while the low-cost aspects should be considered [26,27]. Due to flowchart and assumed requirements, the SiC semiconductor technology is selected as the proposed PFC converter. This technology offers very good static and dynamic parameters since middle and high switching frequencies can be used. Overall, a power converter design equipped with SiC technology will offer excellent parameters with preservation of small dimensions, small magnetics sizes and friendly economical aspects.

Looking at the commercially available SiC power transistor structures, the selection criterion is determined by the target application of proposed PFC converter. This is related to voltage blocking capability, while proposed PFC converter is expected to source 800 Vdc at DC link side. Therefore, 1.2 kV transistor types have been selected from several manufacturers.

Table 2. Basic parameters of selected SiC transistors.

	SiC v1	SiC v2	SiC v3	SiC v4
Parameters
RDS(ON) [mΩ]	60	28	21	100
ID [A]	36	98	91	36
VGS [V]	−7 ÷ 23	−15 ÷ 25	−10 ÷ 22	−10 ÷ 22
CISS [pF] (VDD = 800 V)	1060	2943	3540	1233
COSS [pF] (VDD = 800 V)	58	258	176	56
QG(tot) [nC] (VDD = 800 V)	31	220	150	61
td(on) [ns]	5.7	22	16	13.4
trise [ns]	7	20	9.5	10.3
td(off) [ns]	13	42	37	22
tfall [ns]	12	9	22	7.9

lists selected types together with the main electrical parameters of the transistors. Because this study is not a presentation or advertisement for specific type of transistor, or manufacturer, the type designations are not provided.

As can be seen in the table, alternatives with lower and higher current capabilities have been selected. Both alternatives are suitable if the nominal parameters of the proposed PFC converter are considered. However, it must be noted here that the current rating capability is in direct relationship to the value of resistance of the conduction channel. This is reflected in the values of conduction losses. On the other side, transistors with low R_DS(ON) are specified with a higher value of output capacitance C_OSS, for which the value is the main parameter affecting switching losses. Therefore, these variations are experimentally evaluated in the way of evaluation of efficiency performance of the PFC converter, so as to assess which element of the loss is most dominant.

5. Experimental Measurement Results

During experimental testing, several key operational performances were evaluated during transistors operation. At first, the gate-source voltage transient during the turn-on process was observed. From the dynamic point of view, the switching times were evaluated, i.e., the fall and rise time were of the nominal operational conditions proposed for the PFC converter. Consequently, requirements on the driver, i.e., driving current and power for individual transistors was evaluated. Finally, the efficiency performance of the PFC converter operated under nominal conditions was also measured.

5.1. Dynamic Performance Evaluation

The first measurement of the dynamic transients related to the gate-source driving voltage was realized for transistor SiC v1. The evaluation was realized using time waveforms recorded by oscilloscope Tektronix MDO3034, while the rise time from a non-conducting state (0 V) to a fully opened transistor (10–11 V) was measured. The recorded time waveforms for selected transistor structures are shown on Figure 10, Figure 11, Figure 12 and Figure 13. Graphical interpretation of received results are consequently provided in Figure 14. From the measurements it can be seen that the fastest turn-on transient can be observed for the transistors with the lowest values of input capacitances, i.e., for SiC v1 and SiC v4. On the other side, better performance for SiC v3 was observed compared to SiC v2, where even the C_ISS of SiC v2 is smaller, but the reason here of the worse dynamic performance is the higher demand on the Q_G of SiC v2.

The second evaluation of the dynamic performance of selected SiC transistors was related to the evaluation of turn-on and turn-off times during switching operation. These measurements were performed similarly to the instructions provided by the transistor manufacturers (Figure 15). Here, it must be stated that t_on = t_d(on) + t_r, and t_off = t_d(off) + t_f, while measurements identify total turn-on and turn-off times without identifying delays or rise/fall times.

The values of the switching time transients is dependent on the values of operational conditions of the converter/transistor itself. Therefore, the evaluation of switching times was realized for two values of operational voltage, i.e., 400 Vdc and 800 Vdc at the DC link of converter (Figure 2). The results received from the experimental measurements are listed in Figure 16 for both turn-on and turn-off switching transients. For both values of voltage DC-link, the power delivery of the converter was set to 3 kW.

As was observed from measurements, and based on description given in previous chapters, the choice of the right semiconductor device is a complex decision-making process, and many parameters must be considered. Figure 17 summarizes the achieved results, while the dependencies of some static and dynamic parameters were graphically interpreted to simplify the selection criterions on power transistor for their specific design.

With an increase in the switching frequency, the parasitic capacitances and dynamic parameters of the semiconductor devices worsened, thus it results in an increase in switching losses. On the other side, an increase in switching frequency has a positive effect on the reduction of the magnetics size, but the opposite effect is the increase in magnetisation losses in magnetic material due to a higher frequency. Due to these facts, the high switching frequency with low magnetics sizes are used with advantages in small power converters with low output-power delivery.

If the requirement of heavy power converter comes with high power and current values, the semiconductor switches with low conduction parasitics, together with a combination of low switching frequency, are used to achieve high efficiency. However, the consequence is that magnetic component should also be big and heavy.

For the designed PFC converter, the selection of proper components is a compromise between optimal values of static parameters (affects conduction losses) and parasitic capacitances (affect the switching losses). As is shown in Figure 17, the design constraints of a PFC converter are located within the optimal region defined by the cross section of static and dynamic losses.

5.2. Evaluation of the Power Consumption and Efficiency Performance

As was mentioned within the introduction of this study, efficiency, or power consumption is one of the most important qualitative indicators of switched-mode power supplies. Therefore, at this point, an evaluation of the requirements on the driving power during turn-on transient and a measurement of the gate-sink current were performed (Figure 18). Based on the values from Table 2, it can be expected that the transistor with the highest input capacitance would have the highest demands on driving power. This is also confirmed by the measurements, presented in the graphical comparison in Figure 18.

An evaluation of the efficiency performance was realized under operational conditions, with the DC link voltage initially set to 400 Vdc and consequently to 800 Vdc. For both cases, the output power was maintained at 3 kW (

Table 3. Efficiency measurement results.

Parameters	Output Voltage = 400 Vdc				Output Voltage = 800 Vdc
	SiC v1	SiC v2	SiC v3	SiC v4	SiC v1	SiC v2	SiC v3	SiC v4
PIN(RMS) [W]	3044.23	3041.23	3028.76	3058.21	3026.12	3040.54	3038.76	3010.25
VOUT [V]	499.10	498.70	499.80	497.50	798.70	799.50	799.00	799.80
IOUT [A]	6.01	6.02	6.01	6.03	3.76	3.75	3.76	3.75
POUT(RMS) [W]	3001	3002	3001.5	2999.8	3001	3002	3001.5	2999.8
η [%]	98.58	98.71	99.10	98.09	99.17	98.73	98.77	99.65

).

The graphical interpretations of the results of the efficiency are shown on Figure 19. From the presented values, it is seen that for transistors V2 and V3, the difference of the efficiency for 400 Vdc and 800 Vdc of output voltage is negligible. This difference varies on the level of the measuring error of the laboratory equipment. On the other side, transistors V1 and V4 show a higher difference when comparing the situation for 400 Vdc and 800 Vdc. It is clear that better efficiency is achieved for a higher output voltage value. This fact could be affected by the parasitic capacities’ nonlinear voltage dependency, while for lower voltages the higher value exists, thus decreasing the dynamic performance of the transistor structure.

6. Discussion

Based on the experimental measurements, it is useful to identify whether the parameters for transistor characterization and their associated performances are in conflict with each other. For this purpose, a correlation analysis was performed [28], while the following characteristic parameters were evaluated:

• Total gate charge—Q_G(tot)
• Fall and rise time of gate voltage—t_rise, t_fall
• Input and output capacitance—C_ISS, C_OSS
• Efficiency—η

Based on correlation analysis of the selected parameters, for which the values were selected based on Table 2, it can be concluded that there are very statistically significant relationships between them. The following results were observed:

• As the overall gate charge of the transistor increases, its input and output capacities increase modestly, but its resistance of the conduction channel decreases.
• The decreasing resistance of the transistor increases the efficiency of the system.
• The rise and fall time are related, which is logical because a slower transistor has longer and better shape of driving signal.
• With increasing input capacitance, the transistor also has an increased output capacitance, and a very strong correlation was found in that if the input capacitance increases with the transistor, the resistance of the conduction channel decreases.

The most significant correlations are highlighted in

Table 4. Correlation analysis of characterization parameters.

Correlations
		η [%]	tfall [ns]	trise [ns]	CISS [nC]	COSS [nC]	Rdson Mohm
QG(tot) [nC]	r	0.554	0.387	0.323	0.850 **	0.993 **	−0.874 **
	p	0.154	0.344	0.436	0.008 *	0.000 *	0.005 *
η [%]	r		0.191	0.371	0.841	0.616	−0.857 **
	p		0.650	0.366	0.059	0.104	0.007
tfall [ns]	r			0.844 **	0.311	0.384	−0.322
	p			0.008	0.454	0.348	0.437
trise [ns]	r				0.357	0.345	−0.372
	p				0.386	0.403	0.365
CISS [nC]	r					0.855 **	−0.995 **
	p					0.007 *	0.000 *
COSS [nC]	r						−0.887 **
	p						0.003 *

*. Correlation is significant at the 0.05 level (2-tailed). **. Correlation is significant at the 0.01 level (2-tailed). p = Significance. r = Correlation.

.

7. Conclusions

In this study, the investigation of the influence of power-transistor selection on the operational efficiency of PFC was evaluated, together with an experimental analysis of the dynamic performance and driving requirements of selected transistor structures. For the designed PFC converter, the selection of proper components is a compromise between optimal values of static parameters (affects conduction losses) and parasitic capacitances (affect the switching losses). When selecting the appropriate type of transistor for a three-phase PFC, four types from three manufacturers of SiC transistors were selected. Individual transistors differ mainly in the value of drain current, while high current (app. 90 A) and middle current capability (app. 30A) transistors were evaluated. This essential property has a direct influence on the other performance, i.e., on the dynamic behaviour and gate-drive requirements. Based on these differences, the evaluation of operational performance of individual transistors has been realized, while the impact of this was reflected in the efficiency performance of the proposed PFC converter. From the measurements, we observed that the fastest turn-on transient is valid for transistors with the lowest values of input capacitances. On the other side, even C_ISS is hypothetically low, and the worst dynamic performance is reached when a higher demand on the Q_G is simultaneously required.

The efficiencies at a DC link voltage of 400V and 800V with 3 kW of power delivery were compared. The efficiencies ranged from around 98.5 to 99.6 percent according to the transistor manufacturer and measurements. The worst dynamic performance of the selected types was observed for the transistor with the highest required gate charge. On the other side, this transistor represents a robust solution because of the low R_DS(ON) and thus, the high current capability. This was reflected in particularly low conduction losses because the total efficiency of the evaluated PFC with this type of transistor reached overall comparable results to the much faster types selected.