A 1 Gbps Chaos-Based Stream Cipher Implemented in 0.18 μm CMOS Technology
Abstract
:1. Introduction
2. Proposed Stream Cipher
2.1. Skew Tent Map
2.2. Dynamics Degradation Due to Digitization
2.3. Encryption Algorithm
3. Implementation Results
4. Cryptanalysis
5. Conclusions
Author Contributions
Funding
Conflicts of Interest
References
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Parameter | Value |
---|---|
Technology (nm) | 180 |
Area (mm2) | 0.19682 |
Gate equivalent (2-NAND) | 19682 |
Maximum frequency (MHz) | 125 |
bits/cycle | 8 |
Maximum throughput (Gbps) | 1 |
Throughput/gate (kbps/gate) | 50.8 |
Power at 125 MHz (mW) | 24.1 |
Energy/bit (pJ/bit) | 24.1 |
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Garcia-Bosque, M.; Díez-Señorans, G.; Pérez-Resa, A.; Sánchez-Azqueta, C.; Aldea, C.; Celma, S. A 1 Gbps Chaos-Based Stream Cipher Implemented in 0.18 μm CMOS Technology. Electronics 2019, 8, 623. https://doi.org/10.3390/electronics8060623
Garcia-Bosque M, Díez-Señorans G, Pérez-Resa A, Sánchez-Azqueta C, Aldea C, Celma S. A 1 Gbps Chaos-Based Stream Cipher Implemented in 0.18 μm CMOS Technology. Electronics. 2019; 8(6):623. https://doi.org/10.3390/electronics8060623
Chicago/Turabian StyleGarcia-Bosque, Miguel, Guillermo Díez-Señorans, Adrián Pérez-Resa, Carlos Sánchez-Azqueta, Concepción Aldea, and Santiago Celma. 2019. "A 1 Gbps Chaos-Based Stream Cipher Implemented in 0.18 μm CMOS Technology" Electronics 8, no. 6: 623. https://doi.org/10.3390/electronics8060623
APA StyleGarcia-Bosque, M., Díez-Señorans, G., Pérez-Resa, A., Sánchez-Azqueta, C., Aldea, C., & Celma, S. (2019). A 1 Gbps Chaos-Based Stream Cipher Implemented in 0.18 μm CMOS Technology. Electronics, 8(6), 623. https://doi.org/10.3390/electronics8060623