Electric Double Layer Field-Effect Transistors Using Two-Dimensional (2D) Layers of Copper Indium Selenide (CuIn₇Se₁₁)

Abstract

Innovations in the design of field-effect transistor (FET) devices will be the key to future application development related to ultrathin and low-power device technologies. In order to boost the current semiconductor device industry, new device architectures based on novel materials and system need to be envisioned. Here we report the fabrication of electric double layer field-effect transistors (EDL-FET) with two-dimensional (2D) layers of copper indium selenide (CuIn₇Se₁₁) as the channel material and an ionic liquid electrolyte (1-Butyl-3-methylimidazolium hexafluorophosphate (BMIM-PF₆)) as the gate terminal. We found one order of magnitude improvement in the on-off ratio, a five- to six-times increase in the field-effect mobility, and two orders of magnitude in the improvement in the subthreshold swing for ionic liquid gated devices as compared to silicon dioxide (SiO₂) back gates. We also show that the performance of EDL-FETs can be enhanced by operating them under dual (top and back) gate conditions. Our investigations suggest that the performance of CuIn₇Se₁₁ FETs can be significantly improved when BMIM-PF₆ is used as a top gate material (in both single and dual gate geometry) instead of the conventional dielectric layer of the SiO₂ gate. These investigations show the potential of 2D material-based EDL-FETs in developing active components of future electronics needed for low-power applications.

1. Introduction

Since the discovery of single Molybdenum Disulphide (MoS₂) layer as an active channel component in field-effect transistors (FETs) [1], research on 2D materials for electronics and optoelectronics has gained massive momentum. Over a short period of time, various new classes of 2D materials [2,3], e.g., transition metal dichalcogenides (TMDs), group III-VI layered materials, MXenes, etc., have emerged as potential future candidates for post-silicon electronics. However, most of the work performed on 2D material-based FETs focused on the conventional back gate approach where the use of SiO₂ as the gate dielectric is typical. Some of the advantages of SiO₂ back gate includes their natural availability, simpler device fabrication, and easier modulation of gate thickness. However, a low dielectric constant of SiO₂ (κ = 3.9) results in low capacitances and, therefore, the need for high threshold voltages for device operations [4]. Higher operating voltages imply higher operating cost for integrated circuit chips. High-κ dielectric materials, such as inorganic, polymer, and electrolyte dielectrics, have been incorporated into FETs depending on cost, durability, operation speed, and transconductance for better performance of FETs, as well as potential applications in flexible and stretchable electronics [4,5]. In this regard, ionic liquids have emerged as promising dielectric gate materials in FETs [6,7,8]. Electric double layers (EDL) formed by ionic liquid result in higher capacitance due to their atomically thin charge layer. The charge accumulated (Q) by a capacitor is given by Q = C × V, where C is the capacitance and V is the applied voltage. The higher capacitance in the EDL yield in higher electrostatic charge carrier doping in the semiconductor channel ultimately results in high on-state current and lower threshold and operational voltages. Further, it has been shown through other different applications, such as batteries, capacitors, fuel cells, solar cells, and actuators, that ionic liquids have exceptional and stable chemical properties [8,9,10,11,12].

Recently, ionic liquids have been integrated with two-dimensional (2D) material-based FETs, which has resulted in various fascinating applications [13,14,15,16,17,18,19,20]. For example, studies have indicated that superconductivity can be induced in atomically thin layers of ZrNCl-based FETs at T = 15.2 K by using ionic liquid DEME-TFSI as the gate [13], ambipolar metal-insulator transition can be induced in thin flakes of black phosphorus-based FETs with DEME-TFSI as the gate dielectric [14], and ferromagnetism can be induced in cobalt (Co)-doped titanium dioxide (TiO₂) in EDL-FETs with DEME-TFSI as the gate [15]. Lastly, device performance can be substantially improved in few-layered MoS₂-based ambipolar FETs, where it was shown that by using DEME-TFSI as the EDL gate, mobilities of ~60 cm² V⁻¹ s⁻¹ and on-off ratios of ~10⁷ with the subthreshold swing reaching near the ideal value of ≈50 mV/dec [16] can be achieved. Even though 2D materials have shown great potential, a great deal of investigation needs to be carried out to match the performance of silicon-based devices. So far binary 2D materials, such as MoS₂, WSe₂, InSe, In₂Se₃, etc. have been the main focus of investigations [21,22,23]. Lately, however, multi-component derivatives (via doping or alloying) and heterostructures of this binary compounds have attracted attention due to tunable electronic properties [24,25]. Bulk copper indium selenide (CIS) has been widely used in optoelectronics research and industry as a new-generation material for ultra-thin flexible solar cells due to its high photoresponsivity and wide spectral range [26]. When the copper-to-indium ratio lies between 1:5 and 1:9, CIS forms a γ-phase with hexagonal stacking of close-packed selenium anions, thus yielding a layered structure [26]. Such a layered structure, therefore, can be exfoliated into ultra-thin conductive channel materials (not possible for extensively investigated thin films). For example, a 2D-layered structure of ternary copper indium selenide (CIS)—specifically, CuIn₇Se₁₁ (γ-phase of CIS)—has shown to have excellent electronic and optoelectronic properties with field-effect mobility reaching ~37 cm² V⁻¹ s⁻¹ along with photo-responsivity of ~32 A W⁻¹ and a response time ~9 μs [27,28]. However, most of these materials are investigated in the light of FET-based devices with conventional SiO₂ gates.

Here, we show that by constructing an electric double layer field-effect transistor (EDL-FET) using CuIn₇Se₁₁ as the channel material and an ionic liquid electrolyte (1-butyl-3-methylimidazolium hexafluorophosphate (BMIM-PF₆)) as the gate terminal can provide FET devices with further tunability. The reason for choosing BMIM-PF₆ is as follows: It has been shown that mobility (μ) is higher for BMIM-PF₆-based FETs compared to other ionic liquids [29]. Our investigations show that field-effect mobility of μ_FE ≈ 21.84 cm² V⁻¹ s⁻¹ can be achieved with a BMIM-PF₆ ionic liquid top gate which is a 5.4 times improvement from the corresponding value μ_FE ≈ 4.04 cm² V⁻¹ s⁻¹ of the same device with a conventional SiO₂ back gate. One order of magnitude increase in the on-off ratio > 10⁴ with the ionic liquid gate as compared to the SiO₂ gate was also observed. We further demonstrate two orders of magnitude improvement in the subthreshold swing with a subthreshold swing (SS) of ~0.3 V/dec with the ionic liquid gate (which was ~9.6 V/dec with the SiO₂ gate). Although ionic liquids (IL) show improved device performances, water absorption by the IL degrades performance over time and mechanical properties of the liquid restrict their utilization for practical application [4]. Such drawbacks can be avoided by using ionic gel polymers. Ion-gel overcomes these issues by incorporating/physical cross-linking ionic liquid in a block of the polymer [4]. Ion-gel combines ion mobility of IL with mechanically stable solid films of the polymer [4]. Therefore, we investigated FET performance with an ion-gel (BMIM-PF₆/PEO) top gate (on a different device) which shows an improvement in the performance with the ion-gel gate (μ_FE ≈ 0.42 cm² V⁻¹ s⁻¹, on/off ratio ~ 10³, and SS ~ 0.81 V/dev) compared to the SiO₂ gate (μ_FE of 0.23 cm² V⁻¹ s⁻¹, on/off ratio of ~10⁰, and SS of 107 V/dev). We also show that device parameters (for example, the field effect mobility) can be further improved by operating the device in a dual gate mode (with BMIM-PF₆/PEO as a top gate and SiO₂ as a back gate).

2. Materials and Methods

A detailed synthesis of CuIn₇Se₁₁ has been reported elsewhere [27]. In a nutshell, single crystals of CuIn₇Se₁₁ were grown via a typical melting and recrystallization process with Cu₂Se and In₂Se₃ as precursors. The mixture in a 1:7 ratio (Cu₂Se:In₂Se₃) was ground in a mortar and transferred to a quartz ampoule (at a pressure of < 10⁻³ torr along with argon flushing). The ampoule was heated in a furnace at 950 ℃ for five hours followed by slow cooling to 700 ℃ and natural cooling thereafter. An optical image of the as-synthesized single crystal of CuIn₇Se₁₁ (black mica-like texture) is shown in the inset of Figure 1a. The energy-dispersive X-ray spectrum of the CuIn₇Se₁₁ flake is shown in Figure 1a and it indicates Cu:In:Se in a 1:7:11 ratio. The strong peak at 1.74 keV corresponds to the underlying silicon substrate. Detailed structural characterization (SEM, HRTEM, EDX and XRD) revealed the two-dimensional layers of CuIn₇Se₁₁ [27,28].

Using Scotch tape-assisted mechanical exfoliation, a few layers of CuIn₇Se₁₁ flakes were exfoliated from the as-grown crystals on SiO₂/Si substrate with a 1000 nm SiO₂ layer. Surface roughness (root mean square) of the exfoliated flake was found to be 0.2 nm. As-exfoliated flakes were contacted via chromium, Cr (~20 nm, deposition rate ~ 0.009–0.011 nm/s) and gold, Au (~200 nm, deposition rate ~ 0.13–0.22 nm/s), and deposited by using a shadow mask in a home-built thermal evaporation system. The low deposition rate rules out the possibility of burning channel layers. An optical image of the flake which contacts with the Au/Cr pads is shown in the inset of Figure 1c. As contacted flakes were transferred on the chip holder (CSB02842, Spectrum Semiconductor, San Jose, CA, USA) and gold wire was used to connect chip holder pins to the metal contacts. The exfoliated flakes and the as-fabricated devices were not treated with any other technique, such as annealing, before measurements. The chip holder was mounted on the cold head of the cryostat (RDK-101D, SHI Cryogenics Group, Elk Grove Village (Chicago), IL, USA). Four terminal (source, drain, back gate, and top gate) FET measurements were performed using Keithley 2400-series source meters. The underlying SiO₂ was used as the back gate terminal. A small and continuous drop of 1-butyl-3-methylimidazolium hexafluorophosphate (BMIM-PF₆, CAS No.: 174501-64-5, ACROS Organics, Geel, Belgium) was used as the top gate terminal. The electronic measurements with an ionic liquid top gate that are reported here were taken once the drain current in the device was stabilized (typically 5–7 days). For ionic liquid-based gel polymer electrolyte, we have used poly (ethylene oxide) (PEO, average M_v 100,000, CAS No.: 25322-68-3, Sigma-Aldrich, St. Louis, MO, USA) as a polymer matrix. A monomer of poly (ethylene oxide) was self-assembled into a physically cross-linked network with BMIM-PF₆ to form an ion-gel electrolyte. Ion-gel was prepared by mixing BMIM-PF₆ (10% by weight) and PEO (90% by weight) in methanol (as a solvent) and the mixture was heated to 50 ℃ before drop casting a small drop of the mixture onto the device.

3. Results and Discussion

3.1. Electronic Transport with Dielectric Gate

Electronic transport measurements of CuIn₇Se₁₁ FET (Device I) using dielectric (SiO₂) as the back gate are shown in Figure 1. Figure 1b shows transfer characteristics (drain current I_d vs. gate voltage V_g) between a gate voltage of −60 V and +60 V and at a constant drain voltage of V_d = 1 V. A typical n-type behavior was observed and it indicates the In-rich nature of the semiconducting channel. On-set voltage was found to be V_on ~ −15 V, which differentiates from the on-state of the FET from the off-state of the FET. Hysteresis was observed with the cycling of the back gate voltage, which indicates charge trapping at the CuIn₇Se₁₁ and SiO₂ interface and/or defects/trap states in the conduction channel. The figure of merit associated with FETs were calculated using the forward cycle of transfer characteristics, as shown in Figure 1c. In the off-state of FET (V_bg < −20 V), the drain current was found to be I_off ~ 0.5–0.7 nA. As the gate voltage is increased, the channel starts conducting (on-state) and the maximum drain current was observed to be I_on ~ 353 nA at V_bg = 60 V. Thus, the on-off ratio was estimated to be ~10³. Field-effect mobility is the average drift speed of charge carriers under a unit electric field. Field-effect mobility (μ_FE) was estimated from Equation (1):

$${\mathsf{\mu }}_{\mathrm{FE}}=\frac{\mathrm{L}}{\mathrm{W}{\mathrm{C}}_{\mathrm{g}}{\mathrm{V}}_{\mathrm{d}}}\frac{\partial {\mathrm{I}}_{\mathrm{d}}}{\partial {\mathrm{V}}_{\mathrm{bg}}}$$

(1)

where L ~ 10 μm and W ~ 9 μm corresponds to the length and the width of the device, respectively. The oxide capacitance (C_ox = 3.45 × 10⁻⁹ F cm⁻²) was calculated by using the formula C_ox = ε₀ × ε_r/d_ox, where, ε_r = 3.9 and d_ox = 1000 nm are the relative permittivity and thickness of the SiO₂, respectively. Transconductance, g_m = ∂I_d/∂V_bg ~ 1.06 × 10⁻⁸ S, was calculated for +40 V ≤ V_bg ≤ +60 V and it is shown by a black dashed line in Figure 1c. Field-effect mobility was estimated to be μ_FE ≈ 4.04 cm² V⁻¹ s⁻¹. This estimated mobility is almost order of magnitude lower than previously reported values for CuIn₇Se₁₁ FET [28], which might be due to the difference in channel thickness, as seen previously in other 2D materials [30,31,32]. These values of mobilities are comparable with other Se-based FETs, In₂Se₃ (μ_FE ~ 30 cm² V⁻¹ s⁻¹) [33], In₂Se₃ (μ_FE ~ 2.5 cm² V⁻¹ s⁻¹) [34], InSe (μ_FE ~ 0.1 cm² V⁻¹ s⁻¹) [35], InSe (μ_FE ~ 32.6 cm² V⁻¹ s⁻¹) [36], GaSe (μ_FE ~ 0.1 cm² V⁻¹ s⁻¹) [37], and WSe₂ (μ_FE ~ 80 cm² V⁻¹ s⁻¹) [23].

The subthreshold swing is the gate voltage required for increasing drain current by an order of magnitude in the subthreshold region. Subthreshold swing (SS) was calculated using Equation (2):

$$\mathrm{SS}={\left({\left|\frac{\partial \log ({\mathrm{I}}_{\mathrm{d}})}{\partial {\mathrm{V}}_{\mathrm{g}}}\right|}_{\max }\right)}^{-1}$$

(2)

The subthreshold slope (∂log(I_d)/∂V_g) was calculated in the subthreshold region by plotting the transfer curve in the semi-log scale (blue curve in Figure 1c) and it is shown by the yellow dashed line in Figure 1c. SS was estimated to be 9.6 V/dec and it is a substantially different from the ideal SS (~ 60 mV/dec). This deviation could be due to either a depletion layer formed due to trap states [38] and/or higher thickness (1000 nm) of the SiO₂ layer. SS, field-effect mobility, and other device parameters are closely related quantities and they are governed by the capacitance of the FET [39]. A further understanding of device performance is needed, however, such analysis will not add to the core findings of the current article. We plan to perform the analysis presented in [39] in our future work.

Output characteristic (drain current I_d vs. drain voltage V_d) under different gate voltages (0 V ≤ V_bg ≤ +60 V) is shown in Figure 1d. Output characteristics show an almost linear current-voltage response for low voltage bias, known as the linear region. Linear current-voltage response implies ohmic-like contacts and barrier effects can be neglected. As the drain voltage is increased, the FET goes into saturation mode and it behaves as the constant current source which can be used for voltage amplification. As seen from Figure 1d, applied back gate voltage determines the level of constant current through the channel. It has to be noted that the drain current in output characteristics (~ 2.9 nA at V_d = 1 V and V_g = 60 V) is significantly lower than the drain current in transfer characteristics (~ 353 nA at V_d = 1 V and V_g = 60 V). This could be due to the transient nature of the drain current in the presence of constant applied gate voltage, as seen previously in MoS₂ FETs [40].

3.2. Electronic Transport with an Electric Double Layer Gate

Electronic transport measurements of CuIn₇Se₁₁ FET (Device I) using an electric double layer (BMIM-PF₆) as the top gate are shown in Figure 2. Transfer characteristics with the electric double layer gate are shown in Figure 2a. Similar to back gate transport, n-type conduction was observed with V_on ~ 0.8 V. Off-state I_d was found to ~1–2 nA, whereas the on-state I_d was found to be ~57 μA at V_tg = +3 V. Thus, the on/off ratio was estimated to be >10⁴, which shows one order of magnitude improvement from the corresponding value of the back gate (~10³). Using Equation (1), mobility was estimated to be μ_FE ≈ 21.84 cm² V⁻¹ s⁻¹ where g_m ~ 4.47 × 10⁻⁵ S (black dashed line in Figure 2b), was calculated for 2 V ≤ V_tg ≤ 3 V. Here we have used C_g ~ 2.5 μF cm⁻², estimated from the Mott-Schottky method (discussed later in this section). Mobility shows an almost 5.4 times improvement from the corresponding value of the back gate. It is crucial to estimate the EDL capacitance at the electrolyte-semiconductor interface as capacitance is found to vary with the interface. The capacitance of the EDL depends on ionic liquid-semiconductor interface.For example, the capacitance of DEME-TFSI was found to vary as C_EDL ≈ 9.2 μF cm⁻² for ZrNCl [13], C_EDL ≈ 7.2 μF cm⁻² (electron) and ≈ 4.7 μF cm⁻² (hole) for MoS₂ [41], C_EDL ≈ 34 μF cm⁻² for ZnO [42] and C_EDL ≈ 20 μF cm⁻² for VO₂ [43]. Several techniques have been used to estimate capacitance directly at the ionic liquid-semiconductor interface. For example, electrochemical impedance spectroscopy (EIS) was used in a ZnO thin film transistor [44], Hall-effect measurement was used in MoS₂ thin flake transistors [41], the interconnection between an SiO₂ back gate and ionic liquid top gate (change in threshold voltage of EDL-FET with application of back gate voltage) in dual gating FET [16] and the Mott-Schottky method was used for organometal perovskite solar cells [45]. We have used the Mott-Schottky method to estimate the EDL capacitance which we used for the mobility calculation.

Ionic liquid (BMIM-PF₆) forms a different type of EDL with a gold pad and CuIn₇Se₁₁. A schematic of two different EDL capacitances (C₁ with BMIM-PF₆: CuIn₇Se₁₁ and C₂ with BMIM-PF₆: Au) is shown in the Figure 2c. These capacitors are connected in parallel and the total capacitance of the IL will be the sum of the individual capacitance, C_tot = ΣC_i. For the Mott-Schottky method, source and drain terminals were connected together (shorted) to form a single electrode. Using the Mott-Schottky method, (1/C_IL)² was estimated as a function of voltage. A plot of C_IL as a function of voltage is shown in Figure 2d. Total capacitance was found not to vary a great deal as a function of the voltage and its value is C_tot ~ 25 μF cm⁻². EDL capacitance of BMIM-PF₆: Au has been previously reported as C₂ ~ 7.5 μF cm⁻² [46]. Thus, EDL capacitance of BMIM-PF₆: CuIn₇Se₁₁ can be estimated as C₁ ~ 2.5 μF cm⁻². Our estimated value of capacitance is comparable with the previously reported capacitance of BMIM-PF₆: semiconductor interface [29]. We have used this value of capacitance to evaluate the performance of electric double layer gated FETs.

The subthreshold swing was improved by two orders of magnitude, SS ~ 0.3 V/dec (yellow dashed line in Figure 2b), which indicates the lower number of trap states for the EDL gate compared to trap states for the dielectric gate. The subthreshold swing of a FET device can be given by Equation (3) [47]:

$$\mathrm{SS}=\ln (10)\frac{\mathrm{k}\mathrm{T}}{\mathrm{e}}\left(1+\frac{{\mathrm{C}}_{\mathrm{d}}}{{\mathrm{C}}_{\mathrm{ox}}}\right)$$

(3)

where e is an electronic charge, k is Boltzmann’s constant, T is the temperature, C_d is the depletion layer capacitance and C_ox is the oxide capacitance. A minimum limit of SS (~60 mV/dec at T = 300 K) can be found by letting C_d/C_ox → 0. Physically, it means the effect of the depletion layer formed by the p-n junction is minimum/negligible. We believe that the two orders of change in SS seen in our device imply that C_d/C_ox is lower for the ionic top gate compared to that of the SiO₂ back gate. This is further evident in reduced hysteresis upon cycling of the top gate voltage, indicating lower trap states at the BMIM-PF₆-CuIn₇Se₁₁ interface compared to trap states at the CuIn₇Se₁₁-SiO₂ interface. Further, it is to be noted that SS does not match with the ideal SS and this could be due to a depletion layer formed by bulk trap states originating from defeats in the channel, as well as interface trap states at the BMIM-PF₆-CuIn₇Se₁₁ interface. Improved performance of the FET by the EDL gate could be due to many reasons: lower interface traps and/or higher electrostatic doping and/or reduction in the Schottky barrier thickness due to the ultra-thin dielectric [16]. The figures of merit from the back gate FET and top gate FET are summarized in

Table 1. Key parameters of CuIn₇Se₁₁-based electric double layer field-effect transistors (EDL-FET). Here, V_d = 1 V (Device I) and V_d = 0.1 V (Device II and III), SiO₂ thickness = 1000 nm, V_d: Drain-source voltage, μ_FE: Field-effect mobility, SS: Subthreshold swing, BG: Back gate (dielectric, SiO₂), TG: Top gate (electric double layer, BMIM-PF₆).

Device #	μFE (cm2 V−1 s−1)		SS (V/dec)		on/off ratio
	BG	TG	BG	TG	BG	TG
Device I	4.04	21.84	9.6	0.30	~103	~104
Device II	2.66	17.73	29.8	0.19	~102	~104
† Device III	0.23	0.42	107	0.81	~100	~103

^† A device with ion-gel electrolyte using BMIM-PF₆ and PEO at top gate.

.

Output characteristics under different top gate voltages (0 V ≤ V_tg ≤ +3 V) are shown in Figure 2e. Linear current-voltage at low voltage bias (linear region) was observed as seen in the back gate characteristics. As voltage is increased, the current becomes constant as the FET goes into the saturation region. It is to be noted that the contact current in the saturation region is rather in obvious with EDL gate than dielectric gate (Figure 2e vs. Figure 1d). Similar to dielectric gate, the drain current in output characteristics is significantly lower than the drain current in transfer characteristics owing to the transient nature of the drain current in the presence of constant applied gate voltage [40].

Similar improvement in the performance of the FET was also observed in another device (Device II) and it is summarized in Table 1. For Device II, a negligible hysteresis was observed, which indicated a almost trap-free BMIM-PF₆-CuIn₇Se₁₁ interface. Output characteristics and transfer characteristics with the dielectric gate indicate similar device performance as that of Device I. For the dielectric gate, the figures of merit were estimated to be μ_FE ~ 2.66 cm² V⁻¹ s⁻¹, on/off ratio ~ 10², SS ~ 29.8 V/dev. Output characteristics and transfer characteristics with the electric double layer gate show an improvement in performance. For the electric double layer gate, the figures of merit were estimated to be μ_FE ~ 17.73 cm² V⁻¹ s⁻¹, on/off ratio ~ 10³, SS ~ 0.19 V/dev. Mobility shows an almost 6.6 times improvement for the top gate (17.73 cm² V⁻¹ s⁻¹) as compared to the corresponding value for the back gate (2.66 cm² V⁻¹ s⁻¹). Similarly, improvement in the subthreshold swing, as well as on/off ratio, was seen for the top gate.

3.3. Electronic Transport with Ion-Gel Gate

As a potential application of the EDL-FET in the solid-state flexible device, we have used an ionic liquid based gel polymer electrolyte as a gate. Performance of the FET with an SiO₂ back gate estimates the figures of merit to be μ_FE of 0.23 cm² V⁻¹ s⁻¹, on/off ratio of ~10⁰, and SS of 107 V/dev. This performance of Device III was orders of magnitude lower than the other device presented owing to the bulk nature of the channel. It has been previously reported in the case of MoS₂ that the mobility of 2D FETs decreases drastically with channel thickness [30,31,32]. Figure 3 shows the electronic transport of CuIn₇Se₁₁ FET (Device III) with the ion-gel gate.

Figure 3a shows the transfer characteristics for the ion-gel top gate. Higher hysteresis was observed owing to the rough interface between the semiconductor channel and the polymer gate. The forward cycle in the linear scale (red) and semi-log scale (blue) of the transfer characteristics are shown in Figure 3b. Figures of merit were estimated to be μ_FE ~ 0.42 cm² V⁻¹ s⁻¹, on/off ratio ~ 10³, and SS ~ 0.81 V/dev. Gate capacitance was estimated to be C_g ≈ 3.36 μF cm⁻² by interconnection between the back gate and the top gate, as discussed in following section. Mobility shows an almost 1.8 times improvement from the corresponding value of the back gate. Mobility for the top gate can be further improved upon the application of back gate voltage. Figure 3c shows the output characteristics under different ion-gel top gate voltages (0 V ≤ V_tg ≤ +2 V) which shows a linear region for low voltage bias and a saturation region for high voltage bias.

3.4. Electronic Transport with a Dual Gate

Multiple gates in FETs can lead to versatility in the application where properties due to one gate can be modulated by other gates [48,49,50]. Several past investigations have shown that a great level of tunability in device properties can be achieved through a top and bottom dual gate geometry [16,51,52]. For example, an investigation of bilayer graphene with dual (top and bottom) gating indicates an opening of the band gap as well as improvement in general electronic transport behavior due to the screening of disorder potential [52]. In order to test such effects for CuIn₇Se₁₁ FETs, we investigated one such device in dual gate operation mode with a SiO₂ dielectric back gate and a BMIM-PF₆: PEO ion-gel top gate. Figure 4a shows the schematic of a dual gate FET. Figure 4b shows forward cycle of transfer characteristics for the ion-gel top gate with different back gate voltages. It is to be noted that the on-state current was increased upon application of the back gate voltage. Particularly, on-state I_d at V_tg = +2.5 V was increased from ~1.08 μA at V_bg = 0 V to ~1.26 μA at V_bg = 60 V which is an almost 1.16 times increase. Dual gating enables an estimation of EDL capacitance of ion-gel by interconnection between the SiO₂ back gate and the ion-gel top gate [16]. In dual gating FETs, the application of back gate voltage will change the threshold voltage of the top gate [16]. EDL capacitance was estimated from the change in the threshold voltage (ΔV_th) in response to the change in the back gate voltage (ΔV_bg) by using Equation (4) [16]:

$${\mathrm{C}}_{\mathrm{tg}}=\frac{\Delta {\mathrm{V}}_{\mathrm{bg}}}{\Delta {\mathrm{V}}_{\mathrm{th}}}\times {\mathrm{C}}_{\mathrm{bg}}$$

(4)

where C_bg = 3.45 × 10⁻⁹ F cm⁻² is SiO₂ back gate capacitance. For ΔV_bg = 40 V, ΔV_th was observed to be ~41 mV (Figure 4c), which corresponds to C_tg ≈ 3.36 μF cm⁻². The estimated capacitance is higher than the capacitance of IL-based EDL capacitance in the previous section. This could be due to the different dielectric nature of PEO compared to BMIM-PF₆ or geometrically different EDL formation. This value of capacitance is used to evaluate the performance of the ion-gel gated FET.

Field-effect mobility due to the ion-gel gate as a function of the back gate voltage is shown in Figure 4d. Mobility, μ_FE, was found to be 0.56 cm² V⁻¹ s⁻¹ in the dual gate configuration with constant V_bg = 60 V. Mobility shows an almost 2.4 times improvement from the corresponding value of the back gate. An increase in mobility could be due to an increase in the charge carrier density and/or additional electric field which results in the increased screening of disorder potentials [52]. Dual gating with the ion-gel and the dielectric gate opens the door for tunable and stable performance of a flexible FET.

4. Conclusions

In conclusion, EDL-FETs were fabricated using a few layers of layered CuIn₇Se₁₁ flakes. We have successfully incorporated the ionic liquid BMIM-PF₆ as a top gate in FETs and the performance was found to be improved compared to that of SiO₂ as a back gate. Hysteresis in the transfer characteristics was found to be significantly lower when BMIM-PF₆ is used as a top gate, thus indicating lower charge trap states at the CuIn₇Se₁₁ and BMIM-PF₆ interface. Several parameters that define transistor performance, such as field effect mobility, on-off ratio, and subthreshold swing, were calculated and a comparison between dielectric and electric double-layer gates was demonstrated. The investigation presented here indicated CuIn₇Se₁₁ as a potential candidate for the future electronic and optoelectronic industry.