Analysis of a PWM Converter with Less Current Ripple, Wide Voltage Operation and Zero-Voltage Switching

Abstract

This paper studies and implements a power converter to have less current ripple output and wide voltage input operation. A three-leg converter with different primary turns is presented on its high-voltage side to extend the input voltage range. The current doubler rectification circuit is adopted on the output side to have low current ripple capability. From the switching states of the three-leg converter, the presented circuit has two equivalent sub-circuits under different input voltage ranges (V_in = 120–270 V or 270–600 V). The general phase-shift pulse-width modulation is employed to control the presented converter so that power devices can be turned on at zero voltage in order to reduce switching loss. Compared to two-stage circuit topologies with a wide voltage input operation, the presented converter has the benefits of simple circuit structure, easy control algorithm using a general integrated circuit or digital controller, and less components. The performance of the presented circuit is confirmed and validated by an 800 W laboratory prototype.

1. Introduction

For the past decade, clean energy sources have brought attention to the depletion of fossil fuel demand due to the rising demand for electric power. Fuel cell stacks, wind energy, and photovoltaic (PV) are the most attractive renewable energy sources [1,2,3,4,5,6]. However, the output voltage of dc wind power and PV panels is unstable and widely varies. High-frequency dc-link converters can convert an unstable dc voltage to a constant dc voltage by using duty cycle control [7,8,9] or pulse frequency modulation (PFM) [10,11,12]. In duty cycle control, the turn-on time of the power switch is related to input voltage under the constantly switching frequency. Therefore, the load terminal is regulated at the command voltage. In the PFM approach, the switching frequency is variable and related to input voltage. Thus, the input impedance of the resonant tank is variable to change voltage gain and regulate load voltage. For dc wind energy and PV power, the solar intensity and wind speed have a wide deviation. Therefore, the output voltage of PV panels and wind generators is variable in a wide voltage range. In conventional isolated dc converters, the maximum and minimum effective duty cycles are related to input voltage, d_eff,max/d_eff,min = V_in,max/V_in,min. In phase-shift pulse-width modulation (PWM) converters, the maximum (or minimum) effective duty cycle or duty ratio is normally less (or greater) than 0.45 (or 0.15). Then, the available input voltage variation range V_in,max/V_in,min is less than 3. However, the output voltage variation of some dc wind power and PV panels may be greater than 4. To overcome this problem, dc converters with a cascaded structure [13,14,15] have been studied which have a wide input voltage variation. The problem with the cascaded structure converters is low efficiency. The dc converters with duty cycle control were studied in [16,17,18] to achieve wide voltage operation and low switching loss. However, the control algorithm is too complicated for using a general-purpose integrated circuit. Full-bridge converters with wide input voltage range that have PWM or PFM schemes have been presented in [19,20]. The input voltage variation range in [20] with two transformers and one ac switch structure could achieve V_in,max/V_in,min = 4. Four equivalent circuits could be operated in [14] to realize wide voltage operation. However, the control scheme is more complicated when using a general-purpose integrated circuit. In [21], a hybrid dc–dc converter is presented to have wide voltage operation between V_in = 120 V and 600 V. However, this converter has more ripple current on the output inductor and more passive components on the secondary side. In [22], a wide voltage resonant converter was discussed and implemented to be operated between V_in = 10 V and 160 V for low-power applications. However, the circuit topology was still a cascaded dc–dc converter.

In the present work, a three-leg structure phase-shift PWM converter is studied and implemented to have a wide voltage input operation and a wide load range of zero-voltage turn-on operation. Two sub-circuits with different voltage gains can be operated in the presented converter according to input voltage ranges. Hence, the presented converter can accomplish wide input voltage operation. The phase-shift PWM approach is used to control the gating signals of power devices. Then, the zero-voltage switching (ZVS) operation for the three-leg converter can be easily achieved. The current doubler rectification circuit is operated on the load terminal. Therefore, the current ripple on the output terminal is decreased. A Schmitt voltage comparator is used in the control circuit to select the proper sub-circuit, having a high voltage gain under a low voltage input range or a low voltage gain under ahigh voltage input range. The reference voltage of the voltage comparator is equal to 270 V. The presented circuit is designed to be operated under V_in = 120~600 V. Compared to the conventional cascaded structure converter in [13,14,15,16,17,18], the studied converter has an easy control algorithm and a simple circuit structure. Compared to conventional converters with a wide voltage operation [19,20,21,22], the proposed converter has fewer active switches and a wider voltage deviation region. The effectiveness and benefits of the presented circuit are verified by theoretical analysis and experimental verifications with an 800 W prototype.

2. Proposed Converter

Figure 1a gives the circuit schematic of the presented converter. It can be observed that the three-leg circuit structure is operated on the primary side and a current doubler rectification structure is adopted on the secondary side. An isolation transformer with two sets of primary-turn n_p and one set of secondary-turn n_s is selected in the converter. The ac switch Q is realized by two power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) with a back-to-back connection. According to low voltage or high voltage input conditions, Q is controlled to be OFF or ON. Therefore, two equivalent sub-circuits are worked in the presented converter. For a low voltage input region (e.g., V_in,L = V_in,min~2.3V_in,min), Q, S₁, and S₂ are OFF, and the two-leg PWM converter shown in Figure 1b with active switches S₃–S₆ is operated to regulate the load voltage. The duty cycle control is selected to generate the necessary gate signals of active switches S₃–S₆. Thus, the ZVS operation of S₃–S₆ is achieved. The output voltage can be estimated as $V_o=n_s{V}_{in,L}{d}_{eff}/n_p-V_D$, where d_eff is an effective duty cycle and V_D is the voltage drop on D₁ or D₂. The output voltage can be kept stable and constant by the regulation of the effective duty ratio d_eff. The minimum effective duty ratio d_min,min happens at the maximum input voltage case V_in,L,max under the low voltage input range. On the other hand, the minimum input voltage V_in,L,min will result in the maximum effective duty ratio d_eff,max when the converter is operated in the low voltage input range. The voltage gain of the converter in the low voltage input range is G_dc-L = V_o/V_in,L ≈ d_eff/N_L, where N_L = n_p/n_s. For the high voltage input region (e.g., V_in,H = 2.3V_in,min~5V_in,min), Q is ON and S₃ and S₄ are OFF. The two-leg PWM converter shown in Figure 1c with active switches S₁, S₂, S₅, and S₆ is operated to regulate the output voltage. S₁ and S₂ (S₅ and S₆) are active devices on the leading leg (lagging leg) of the phase-shift PWM converter. As can be noted in Figure 1c, the transformer turns ratio is N_H = 2n_p/n_s instead of n_p/n_s. Under the high voltage input condition, the output voltage is expressed as $V_o=n_s{V}_{in,H}{d}_{eff}/(2n_p)-V_D$ and the voltage gain becomes G_dc-H = V_o/V_in,H ≈ d_eff/N_H. From the circuit operation in the previous statements, the presented circuit can achieve ZVS operation and a wide voltage input operation with about V_in,min − 5V_in,min input voltage variation by the proper switching of Q and S₁–S₆.

3. Principle of Operation

The converter has two sub-circuits shown in Figure 1b,c for low voltage input V_in,L and high voltage input V_in,H operations. For the low voltage input region (V_in,min ≤ V_in,L < 2.3V_in,min) in Figure 1b, Q, S₂ and S₁ are turned OFF and S₃–S₆ are active with duty cycle control. The transformer turns ratio is N_L = n_p/n_s. The corresponding PWM waveforms are provided in Figure 2a. For the high voltage input region (2.3V_in,min ≤ V_in,H < 5V_in,min) in Figure 1c, Q is ON and S₃ and S₄ are OFF. S₁, S₂, S₅, and S₆ are active with duty cycle control. The transformer turns ratio is N_H = 2n_p/n_s. It is assumed the magnetizing inductances L_m1 = L_m2 = L_m >> L_r1 = L_r2 = L_r and the output capacitances C_S1 = ... = C_S6 = C_oss. The PWM waveforms under the high voltage input condition are given in Figure 2b.

According to the PWM waveforms of S₃–S₆ and the conducting states of D₁ and D₂, ten operating steps can be observed in Figure 2a under the low voltage input case. As can be observed, the PWM waveforms are symmetric for each half cycle. Thus, only the first five operating steps are explained briefly, and the corresponding step circuits are given in Figure 3.

Step 1 [t₀, t₁]: At t₀, i_D1 = 0. S₃ and S₆ are active in this step. The leg voltage is v_bc = V_in, v_Lo1 = V_in/N_L − V_o, and v_Lo2 = −V_o. Therefore, i_Lo1 will increase and i_Lo2 will decrease in this step. The primary and secondary inductor currents are given in Equations (1)–(3).

$$i_{Lr1}(t)\approx i_{Lr1}(t_0)+\frac{V_{in}-N_L{V}_o}{N_L^2{L}_{o1}}(t-t_0)$$

(1)

$$i_{Lo1}(t)\approx i_{Lo1}(t_0)+\frac{V_{in}/N_L-V_o}{L_{o1}}(t-t_0)$$

(2)

$$i_{Lo2}(t)\approx i_{Lo2}(t_0)-\frac{V_o}{L_{o2}}(t-t_0)$$

(3)

Step2 [t₁, t₂]:S₃ turns OFF at time t₁. i_Lr1(t₁) is positive and C_S4 is discharged. C_S4 can be discharged to zero at t₂ if Equation (4) is satisfied. Therefore, the ZVS operation of S₄ is achieved.

$$(L_r+N_L^2{L}_o)i_{Lr1}^2(t_1)\ge 2C_{oss}{V}_{in}^2$$

(4)

The time Δt₁₂ in this step is expressed in Equation (5).

$$\Delta t_{12}\approx 2V_{in}{C}_{oss}{N}_L/i_{Lo1}(t_1)$$

(5)

where $i_{Lo1}(t_1)\approx i_{Lo1}(t_0)+(V_{in}/N_L-V_o)d_{eff}{T}_{sw}/L_{o1}$.

Step 3 [t₂, t₃]: At t₂, v_CS4 = 0 and D_S4 is conducting due to i_Lr1 > 0. Thus, the ZVS turn-on operation of S₄ can be naturally realized. Due to leg voltage v_bc = 0, D₁ and D₂ are both conducting. It can be observed that v_Lo1 = v_Lo2 = −V_o and v_Lr1 = -v_S4,dp − v_S6,dp, where v_S4,dp and v_S6,dp are voltage drops on S₄ and S₆. In step 3, i_Lo1, i_Lo2 and i_Lr1 all decrease, i_D1 increases and i_D2 decreases.

Step4 [t₃, t₄]: At t₃, S₆ is turned off. i_Lr1 will charge C_S6 and discharge C_S5. The ZVS turn-on condition of S₅ is given in Equation (6).

$$L_r{i}_{Lr1}^2(t_3)\ge 2C_{oss}{V}_{in}^2$$

(6)

Step 4 ends at t₄ when v_CS5 = 0. The time Δt₃₄ in this step can be obtained in Equation (7).

$$\Delta t_{34}\approx 2V_{in}{C}_{oss}/i_{Lr1}(t_3)$$

(7)

Step 5 [t₄, t₅]: At t₄, v_CS5 = 0. Then D_S5 is conducting due to i_Lr1(t₄) > 0. The ZVS operation of S₅ is naturally realized. In step 5, the leg voltage v_bc = −V_in and D₁ and D₂ are still conducting. The inductor voltage v_Lr1 = −V_in. The output filter inductor voltages v_Lo1 = v_Lo2 = -V_o. Therefore, inductor currents i_Lo1, i_Lo2, and i_Lr1 all decrease. Step 5 ends at t₅ when i_D2 = 0. The time duration Δt₄₅ is derived as Equation (8):

$$\Delta t_{45}\approx (I_o{L}_r)/(V_{in}{N}_L)$$

(8)

The duty loss in this step can be derived in Equation (9).

$$d_5\approx (I_o{L}_r{f}_{sw})/(V_{in}{N}_L)$$

(9)

where f_sw is the switching frequency. Then, the circuit operation will go to next half switching cycle at time t₅.

For high voltage input operation (2.3V_in,min ≤ V_in,H < 5V_in,min), ac switch Q is ON and active devices S₄ and S₃ are OFF. Then, the full-bridge converter with switches S₁, S₂, S₅, and S₆, as shown in Figure 1c, is operated with duty cycle control. The transformer turns ratio on this equivalent circuit becomes N_H = 2n_p/n_s. The dc gain can be expressed as V_o/V_in,H ≈ d_eff/N_H. This can be observed in Figure 2b. The converter has five steps in one-half of the switching period. The corresponding step circuits are given in Figure 4, and the circuit operations are explained briefly in the following discussions.

Step 1 [t₀, t₁]: The current i_D1 = 0 at t₀. Thus, D₁ is OFF. In step 1, S₁ and S₆ are conducting, v_ac = V_in, v_Lo1 = V_in/N_H − V_o, and v_Lo2 = −V_o. The currents i_Lr1 and i_Lo1 increase and i_Lo2 decreases. Step 1 ends at t₁ when S₁ turns off.

Step2 [t₁, t₂]:S₁ is turned off at t₁. i_Lr1 = i_Lr2 > 0 and C_S2 (C_S1) is discharged (charged) by i_Lr2. The ZVS turn-on operation of S₂ is expressed as Equation (10):

$$(2L_r+N_H^2{L}_o)i_{Lr2}^2(t_1)\ge 2C_{oss}{V}_{in}^2$$

(10)

Step 3 [t₂, t₃]:v_CS2(t₂) = 0. i_Lr2 > 0 and D_S2 is forward biased. At this moment, S₂ is turned ON under zero voltage. The leg voltage v_ac = 0 and both diodes D₁ and D₂ conducting. Therefore, v_Lo1 = v_Lo2 = −V_o and v_Lr1 + v_Lr2 = −v_S2,drop − v_S6,drop − v_Q,drop. The currents i_Lo1, i_Lo2, i_Lr1, and i_D2 decrease and i_D1 increases.

Step4 [t₃, t₄]:S₆ turns OFF at t₃. i_Lr1 charges (discharges) C_S6 (C_S5). The ZVS turn-on condition of S₅ is obtained as Equation (11):

$$2L_r{i}_{Lr2}^2(t_3)\ge 2C_{oss}{V}_{in}^2$$

(11)

This step ends at t₄ when C_S5 is discharged to zero voltage.

Step 5 [t₄, t₅]:v_CS5(t₄) = 0. Since i_Lr1(t₄) is positive, D_S5 becomes forward biased. In this step, v_ac = −V_in and D₂ and D₁ are ON. It can be obtained that v_Lr1 + v_Lr2 = −V_in, and v_Lo2 = v_Lo1 = −V_o. i_Lo2, i_Lo1, and i_Lr1 all decrease. This step ends at t₅ when i_D2 = 0. The time Δt₄₅ is obtained as Equation (12):

$$\Delta t_{45}\approx (2I_o{L}_r)/(V_{in}{N}_H)$$

(12)

The duty loss can be calculated in Equation (13).

$$d_5\approx (2I_o{L}_r{f}_{sw})/(V_{in}{N}_H)$$

(13)

At t₅, the circuit operation will go to the next half switching period.

4. Steady State Analysis

In relation to the ON/OFF status of Q and S₁–S₆, two equivalent sub-circuits shown in Figure 1 are operated to have a wide voltage input operation and a ZVS turn-on operation. According to the voltage-second balance on L_o1 or L_o2, the load voltage V_o can be expressed as Equation (14):

$$V_o=\{\begin{array}{c}\frac{n_s{V}_{in,L}}{n_p}(d-\frac{n_s{I}_o{L}_r{f}_{sw}}{n_p{V}_{in,L}})-V_D,V_{in,\min }\le V_{in,L}<2.3V_{in,\min }\\ \frac{n_s{V}_{in,H}}{2n_p}(d-\frac{n_s{I}_o{L}_r{f}_{sw}}{n_p{V}_{in,H}})-V_D,2.3V_{in,\min }<V_{in,L}\le 5V_{in,\min }\end{array}$$

(14)

where d is the duty cycle on voltage v_ac or v_bc. For the low voltage input condition, N_L = n_p/n_s is obtained as Equation (15):

$$N_L=\frac{V_{in,L}}{(V_o+V_D)}(d-\frac{I_o{L}_r{f}_{sw}}{N_L{V}_{in,L}})$$

(15)

The winding turns of transformer T are expressed as $n_p\ge (V_{in,\min }{d}_{\max }{T}_{sw})/(\Delta B{A}_e)$ and $n_s=n_p/N_L$. If the duty loss in (9) is defined, L_r1 and L_r2 can be approximated as Equation (16):

$$L_r=L_{r1}=L_{r2}=\frac{N_L{d}_5{V}_{in}}{f_{sw}{I}_o}$$

(16)

In the presented circuit, the load current is equally distributed on inductors L_o1 and L_o2, and I_Lo1 = I_Lo2 = I_o/2. If the ripple currents of L_o1 and L_o2 are identical (i.e., Δi_Lo1 = Δi_Lo1 = Δi_Lo), then L_o1 = L_o2 = L_o can be calculated in Equation (17).

$$L_o=\frac{(V_o+V_D)}{\Delta i_{Lo}{f}_{sw}}(1-d+\frac{n_s{I}_o{L}_r{f}_{sw}}{n_p{V}_{in,L}})$$

(17)

Then, the winding turns of L_o1 and L_o2 are obtained as $n_{Lo}\ge \left[L_o\right(I_o+\Delta i_{Lo})/2]/(B_{\max }{A}_e)$. The peak switch currents are approximated as Equation (18):

$$i_{Sx,paek}\approx \frac{(I_o+\Delta i_{Lo})/2}{N_L}+\frac{\Delta i_{Lm}}{2}=\frac{(I_o+\Delta i_{Lo})/2}{N_L}+\frac{d{V}_{in,L}{T}_{sw}}{2L_m}-\frac{L_r{I}_o}{2N_L{L}_m}$$

(18)

where x = 1~6. From the ZVS conditions in (4) and (6), the ZVS operation of leading-leg switches are easier to achieve than lagging-leg switches under the given inductance L_r1. The necessary inductances L_r1 = L_r2 = L_r2 are derived as $L_r\ge 2C_{oss}{V}_{in}^2/i_{Lr1}^2(t_3)$ to achieve the ZVS operation of lagging-leg switches S₅ and S₆. The voltage stress of S₁–S₆ and Q is V_in,max. The voltage stress and dc currents of D₂ and D₁ are obtained as V_in,max/N_L and I_o/2, respectively.

5. Experimental Results

The performance of the converter is confirmed from a laboratory circuit with 800 W rated power. The electric specifications of the test circuit are V_in = 120–600 V, the output voltage V_o = 48 V, the maximum power P_o = 800 W, and f_sw = 140 kHz. The presented converter operates in the low voltage input condition if 120 V ≤ V_in < 270 V. Then, Q, S₁, and S₂ are OFF. Likewise, the presented converter operates in the high voltage condition if 270 V < V_in ≤ 600 V. For the high voltage input operation, S₃ and S₄ are OFF and Q is ON. A Schmitt trigger circuit with ±20 V voltage tolerance is selected to avoid control signal oscillation at the transition voltage 270 V. Therefore, the actual low and high voltage input ranges are V_in,L = 120–290 V and V_in,H = 250–600 V. Figure 5a gives the circuit parameters of a prototype circuit. The phase-shift PWM integrated circuit UCC3895 is selected to produce the gating waveforms of S₅ and S₆. The gating waveforms of S₁–S₄ are generated by the logic gates and PWM output of UCC3895. Figure 5b gives the picture of the prototype circuit in the laboratory test.

The experimental waveforms of the proposed converter at a low voltage input range (V_in = 120~290 V) are given in Figure 6, Figure 7, Figure 8 and Figure 9. The measured results under a high voltage input range (V_in = 250~600 V) are given in Figure 10, Figure 11, Figure 12 and Figure 13. Figure 6 provides the experimental primary-side (Figure 6a) and secondary-side (Figure 6b) waveforms at V_in = 120 V and P_o = 800 W. Note that the duty cycle on voltage v_bc is close to 0.5, the ripple current on i_Lo1 + i_Lo2 is reduced compared to the ripple current on i_Lo1 or i_Lo2, and the resultant current i_Lo1 + i_Lo2 has twice the switching frequency of currents i_Lo1 and i_Lo2. Figure 7a,b gives the PWM signal of S₃ at 20% power and 100% power with the V_in = 120 V input case. In the same way, the PWM waveform of S₅ (lagging-leg switch) at 50% and 100% loads are illustrated in Figure 7c,d. Figure 8 and Figure 9 provide the measured results of the presented converter operated at V_in = 290 V in the low voltage input region. Since the higher input voltage will result in a lower duty cycle, it is clear that the voltage v_bc at V_in = 290 V input has less duty ratio than in the V_in = 120 V input condition. It can also be noted in Figure 6b and Figure 8b that i_Lo1 + i_Lo2 has more ripple current at V_in = 290 V than V_in = 120 V. Figure 9 gives the experimental waveforms of S₃ in leading leg and S₅ in lagging leg in the 290 V input condition. It can be observed from Figure 7 and Figure 9 that the ZVS turn-on operation of S₃ is realized from 20% power for both 120 V and 290 V input conditions. Likewise, the ZVS turn-on operation of S₅ is accomplished from 50% power under 120 V and 290 V input cases. For a high voltage input range (Q is ON and S₃ and S₄ are OFF), the test results are shown in Figure 10, Figure 11, Figure 12 and Figure 13. For V_in = 250 V, the experimental results at 100% power are given in Figure 10. The PWM signals of S₁ and S₅ are given in Figure 11. In the same way, the experimental waveforms for V_in = 600 V input are given in Figure 12 and Figure 13. From the experimental results in Figure 7, Figure 9, Figure 11 and Figure 13, it can be observed that the leading-leg switch, such as S₁ and S₃, can achieve ZVS operation from 20% load, and the ZVS operation of S₅ in the lagging leg is from 50% power. The measured results of V_in, v_Q,g, v_S1,g, and v_S3,g between 120V and 600 V input are shown in Figure 14. When V_in is increased from 120 V to 290 V, the presented circuit is controlled in the low voltage input range. Q, S₁, and S₂ are OFF and S₃ and S₄ are controlled with the phase-shift PWM approach. When V_in > 290 V, Q is ON and S₃ and S₄ are OFF. S₁ and S₂ are operated with duty cycle control. When V_in is decreased from 600 V to 250 V, the converter is controlled in the high voltage input range. The switch Q is ON and S₃ and S₄ are OFF. The test results in Figure 14 are in agreement with the theoretical analysis. The test efficiencies of the proposed converter are 89.3% and 91.2% for 120 V and 600 V input cases under a full load. The synchronous rectifiers can be further used on the secondary side to reduce the conduction losses on D₁ and D₂ and improve the converter efficiency.

6. Conclusions

A ZVS converter with three-leg circuit topology is presented and discussed, and an 800 W prototype is constructed and measured to achieve ZVS operation and a wide voltage input operation. The presented converter is expected to be used for dc converters with wide input-voltage or output-voltage demand such as dc wind power applications, battery charger systems with wide voltage operation, and solar PV panel power units with variable input voltage. The proposed converter with a phase-shift PWM scheme can be operated at two equivalent circuits. Therefore, active devices in the leading leg are easily turned on under zero voltage. The current doubler rectification circuit is operated on the low-voltage side in order to have less output ripple current. Compared to conventional phase-shift PWM converters, the studied circuit topology has a wider voltage input capability with the drawback of using an extra three switches in the presented converter. Finally, test results with an 800 W prototype are provided to demonstrate circuit characteristics and the validity of the operating principle.