Digital Signal Processing (DSP)-Oriented Reduced-Complexity Algorithms for Calculating Matrix–Vector Products with Small-Order Toeplitz Matrices
Abstract
:1. Introduction
2. Preliminary Remarks
3. Algorithms for Toeplitz Matrix–Vector Multiplication
3.1. Algorithm for
3.2. Algorithm for
3.3. Algorithm for
3.4. Algorithm for
3.5. Algorithm for
3.6. Algorithm for
3.7. Algorithm for
4. Computational Cost Analysis
5. Conclusions
Author Contributions
Funding
Data Availability Statement
Acknowledgments
Conflicts of Interest
Abbreviations
FFT | fast Fourier transform |
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Order of | Multiplications | Additions | Arithmetic Operations | ||||||
---|---|---|---|---|---|---|---|---|---|
Matrix | Direct | Prop. | Reduct. | Direct | Prop. | Incr. | Direct | Prop. | Incr. |
3 | 9 | 6 | 3 | 6 | 15 | 9 | 15 | 21 | 6 |
4 | 16 | 9 | 7 | 12 | 26 | 14 | 28 | 35 | 7 |
5 | 25 | 14 | 11 | 20 | 45 | 25 | 45 | 59 | 14 |
6 | 36 | 18 | 18 | 30 | 60 | 30 | 66 | 78 | 12 |
7 | 49 | 25 | 24 | 42 | 87 | 45 | 91 | 112 | 21 |
8 | 64 | 27 | 37 | 56 | 114 | 58 | 120 | 141 | 21 |
9 | 81 | 36 | 45 | 72 | 144 | 72 | 153 | 180 | 27 |
Order of | Multiplications | Additions | Arithmetic Operations | ||||||
---|---|---|---|---|---|---|---|---|---|
Matrix | Direct | Prop. | Reduct. | Direct | Prop. | Incr. | Direct | Prop. | Reduct. |
3 | 9 | 6 | 3 | 6 | 9 | 3 | 15 | 15 | 0 |
4 | 16 | 9 | 7 | 12 | 15 | 3 | 28 | 24 | 4 |
5 | 25 | 14 | 11 | 20 | 27 | 7 | 45 | 41 | 4 |
6 | 36 | 18 | 18 | 30 | 33 | 3 | 66 | 51 | 15 |
7 | 49 | 25 | 24 | 42 | 51 | 9 | 91 | 76 | 15 |
8 | 64 | 27 | 37 | 56 | 57 | 1 | 120 | 84 | 36 |
9 | 81 | 36 | 45 | 72 | 81 | 9 | 153 | 117 | 36 |
Order of | Slices | ||||
---|---|---|---|---|---|
Matrix | Devices | MULT 18 × 18 | Direct | Proposed | Reduction |
3 | xc3s50-4pq208 | 4 | 136 | 76 | 44.1% |
4 | xc3s50-4pq208 | 4 | 292 | 210 | 28.1% |
5 | xc3s200-4pq208 | 12 | 384 | 249 | 35.2% |
6 | xc3s400-4fg456 | 16 | 542 | 332 | 38.7% |
7 | xc3s400-4fg456 | 16 | 934 | 634 | 32.1% |
8 | xc3s1000-4fg456 | 24 | 1011 | 553 | 45.3% |
9 | xc3s1000-4fg676 | 24 | 1519 | 890 | 41.4% |
Order of | 4 Input LUTs | |||
---|---|---|---|---|
Matrix | Devices | Direct | Proposed | Reduction |
3 | xc3s50-4pq208 | 256 | 140 | 45.3% |
4 | xc3s50-4pq208 | 549 | 382 | 30.4% |
5 | xc3s200-4pq208 | 729 | 467 | 35.9% |
6 | xc3s400-4fg456 | 1031 | 612 | 40.6% |
7 | xc3s400-4fg456 | 1757 | 1172 | 33.3% |
8 | xc3s1000-4fg456 | 1871 | 1042 | 44.3% |
9 | xc3s1000-4fg676 | 2882 | 1656 | 42.5% |
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Papliński, J.P.; Cariow, A.; Strzelec, P.; Makowska, M. Digital Signal Processing (DSP)-Oriented Reduced-Complexity Algorithms for Calculating Matrix–Vector Products with Small-Order Toeplitz Matrices. Signals 2024, 5, 417-437. https://doi.org/10.3390/signals5030021
Papliński JP, Cariow A, Strzelec P, Makowska M. Digital Signal Processing (DSP)-Oriented Reduced-Complexity Algorithms for Calculating Matrix–Vector Products with Small-Order Toeplitz Matrices. Signals. 2024; 5(3):417-437. https://doi.org/10.3390/signals5030021
Chicago/Turabian StylePapliński, Janusz P., Aleksandr Cariow, Paweł Strzelec, and Marta Makowska. 2024. "Digital Signal Processing (DSP)-Oriented Reduced-Complexity Algorithms for Calculating Matrix–Vector Products with Small-Order Toeplitz Matrices" Signals 5, no. 3: 417-437. https://doi.org/10.3390/signals5030021
APA StylePapliński, J. P., Cariow, A., Strzelec, P., & Makowska, M. (2024). Digital Signal Processing (DSP)-Oriented Reduced-Complexity Algorithms for Calculating Matrix–Vector Products with Small-Order Toeplitz Matrices. Signals, 5(3), 417-437. https://doi.org/10.3390/signals5030021