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Electronics
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Progress and Future Development of Real-Time Systems on Chip
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Progress and Future Development of Real-Time Systems on Chip

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 10 December 2024 | Viewed by 5657

Special Issue Editor

Dr. Lukáš Kohútka

E-Mail Website
Guest Editor
Institute of Informatics, Information Systems and Software Engineering, Slovak University of Technology in Bratislava, 812 43 Bratislava, Slovakia
Interests: ASIC; FPGA; digital system design; real-time systems; high performance computing; CPU

Special Issue Information

Dear Colleagues,

We are delighted to announce the forthcoming Special Issue on "Progress and Future Development of Real-Time Systems on Chip". We invite you to contribute your pioneering research and share your valuable insights in this cutting-edge domain. This special issue aims to showcase the latest advances in the development of real-time systems on chip including various novel ASIC and FPGA designs, CPU architectures, real-time task scheduling, and data sorting solutions.

Real-time systems have emerged as an integral part of our modern technological landscape, driving critical applications across industries, such as autonomous vehicles, industrial automation, medical devices, and communication networks. These systems are characterized by stringent timing constraints, where tasks must be completed within specific deadlines to ensure correct and reliable operation. As the demand for real-time computing grows exponentially, so does the need for more efficient and reliable hardware solutions. Real-time systems often involve computationally intensive tasks such as signal processing, image recognition, and data sorting. Hardware acceleration can significantly speed up these operations, freeing up processing resources for other critical tasks. In this context, application-specific integrated circuits (ASICs) are playing a pivotal role in meeting the unique challenges posed by real-time systems. To keep pace with the escalating demands of real-time computing, new and better ASIC and FPGA solutions and approaches are imperative. These solutions must strive to provide enhanced performance, predictability, determinism, energy efficiency, and reliability while catering to the integration and safety requirements of modern real-time systems. This Special Issue aims to highlight the progress made in addressing the challenges of real-time systems on chip, offering a glimpse into the future development prospects.

This Special Issue is focused on topics relevant to real-time systems on chip and related areas, including but not limited to:

  • Systems on Chip (SoC): Novel design methodologies, architectures, and verification techniques for efficient integration of various functionalities onto a single chip, optimizing power consumption and performance.
  • ASIC and FPGA Designs: Cutting-edge research on application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs), exploring high-speed data processing, hardware acceleration, and resource-efficient solutions.
  • CPU Architectures: Innovations in CPU microarchitecture and instruction set design to enhance real-time processing capabilities, exploit parallelism, and improve predictability.
  • Real-Time Task Scheduling: State-of-the-art algorithms, techniques, and frameworks for real-time task scheduling in multi-core and heterogeneous systems, ensuring timely execution and meeting stringent deadlines.
  • Data Sorting Solutions: Efficient algorithms and hardware implementations for real-time data sorting in big data applications, high-performance computing, and streaming data scenarios.

Dr. Lukáš Kohútka
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • real-time systems
  • ASIC
  • FPGA
  • SoC
  • RTL
  • CPU
  • task scheduling
  • data sorting
  • priority queue
  • hardware acceleration
  • operating systems
  • embedded systems

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Published Papers (4 papers)

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Research

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20 pages, 10975 KiB  
Article
Hardware-Based WebAssembly Accelerator for Embedded System
by Jinyeol Kim, Raehyeong Kim, Jongwon Oh and Seung Eun Lee
Electronics 2024, 13(20), 3979; https://doi.org/10.3390/electronics13203979 - 10 Oct 2024
Viewed by 1029
Abstract
WebAssembly (WASM) has emerged as a novel standard aimed at enhancing the performance of web applications, developed to complement traditional JavaScript. By offering a platform-independent binary code format, WASM facilitates rapid and efficient execution within web browsers. This attribute is particularly advantageous for [...] Read more.
WebAssembly (WASM) has emerged as a novel standard aimed at enhancing the performance of web applications, developed to complement traditional JavaScript. By offering a platform-independent binary code format, WASM facilitates rapid and efficient execution within web browsers. This attribute is particularly advantageous for tasks demanding significant computational power. However, in resource-constrained environments such as embedded systems, the processing speed and memory requirements of WASM become prominent drawbacks. To address these challenges, this paper introduces the design and implementation of a hardware accelerator specifically for WASM. The proposed WASM accelerator achieves up to a 142-fold increase in computation speed for the selected algorithms compared to embedded systems. This advancement significantly enhances the execution efficiency and real-time processing capabilities of WASM in embedded systems. The paper analyzes the fundamentals of WebAssembly and provides a comprehensive description of the architecture of the accelerator designed to optimize WASM execution. Also, this paper includes the implementation details and the evaluation process, validating the utility and effectiveness of this methodology. This research makes a critical contribution to extending the applicability of WASM in embedded systems, offering a strategic direction for future technological advancements that ensure efficient execution of WASM in resource-limited environments. Full article
(This article belongs to the Special Issue Progress and Future Development of Real-Time Systems on Chip)
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13 pages, 534 KiB  
Article
A Novel Approach to Managing System-on-Chip Sub-Blocks Using a 16-Bit Real-Time Operating System
by Boisy Pitre and Martin Margala
Electronics 2024, 13(10), 1978; https://doi.org/10.3390/electronics13101978 - 18 May 2024
Viewed by 1091
Abstract
Embedded computers are ubiquitous in products across various industries, including the automotive and medical industries, and in consumer goods such as appliances and entertainment devices. These specialized computing systems utilize Systems on Chips (SoCs), devices that are made up of one or more [...] Read more.
Embedded computers are ubiquitous in products across various industries, including the automotive and medical industries, and in consumer goods such as appliances and entertainment devices. These specialized computing systems utilize Systems on Chips (SoCs), devices that are made up of one or more main microprocessor cores. SoCs are augmented with sub-blocks that perform dedicated tasks to support the system. Sub-blocks contain custom logic or small-footprint microprocessors, depending upon their complexity, and perform support functions such as clock generation, device testing, phase-locked loop synchronization and peripheral management for interfaces such as a Universal Serial Bus (USB) or Serial Peripheral Interface (SPI). SoC designers have traditionally obtained sub-blocks from commercial vendors. While these sub-blocks have well-defined interfaces, their internal implementations are opaque. Without visibility of the specifics of the implementation, SoC designers are limited to the degree to which they can optimize these off-the-shelf sub-blocks. The result is that power and area constraints are dictated by the design of a third-party vendor. This work introduces a novel idea: using an open-source, small, multitasking, real-time operating system inside an SoC sub-block to manage multiple processes, thereby conserving code space. This OS is TurbOS, a new operating system whose primary goal is to provide the highest performance using the least amount of space. It is written in the assembly language of a new pipelined 16-bit microprocessor developed at the University of Florida, the Turbo9. TurbOS is derived from and incorporates the design benefits of an existing operating system called NitrOS-9, and reduces the code size from its progenitor by nearly 20%. Furthermore, it is over 80% smaller than the popular FreeRTOS operating system. TurbOS delivers a rich feature set for managing memory and process resources that are useful in SoC sub-block applications in an extremely small footprint of only 3 kilobytes. Full article
(This article belongs to the Special Issue Progress and Future Development of Real-Time Systems on Chip)
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21 pages, 6400 KiB  
Article
MASA: Multi-Application Scheduling Algorithm for Heterogeneous Resource Platform
by Quan Peng and Shan Wang
Electronics 2023, 12(19), 4056; https://doi.org/10.3390/electronics12194056 - 27 Sep 2023
Cited by 2 | Viewed by 1292
Abstract
Heterogeneous architecture-based systems-on-chip enable the development of flexible and powerful multifunctional RF systems. In complex and dynamic environments where applications arrive continuously and stochastically, real-time scheduling of multiple applications to appropriate processor resources is crucial for fully utilizing the heterogeneous SoC’s resource potential. [...] Read more.
Heterogeneous architecture-based systems-on-chip enable the development of flexible and powerful multifunctional RF systems. In complex and dynamic environments where applications arrive continuously and stochastically, real-time scheduling of multiple applications to appropriate processor resources is crucial for fully utilizing the heterogeneous SoC’s resource potential. However, heterogeneous resource-scheduling algorithms still face many problems in practical situations, including generalized abstraction of applications and heterogeneous resources, resource allocation, efficient scheduling of multiple applications in complex mission scenarios, and how to ensure the effectiveness combining with real-world applications of scheduling algorithms. Therefore, in this paper, we design the Multi-Application Scheduling Algorithm, named MASA, which is a two-phase scheduler architecture based on Deep Reinforcement Learning. The algorithm is made up of neural network scheduler-based task prioritization for dynamic encoding of applications and heuristic scheduler-based task mapping for solving the processor resource allocation problem. In order to achieve stable and fast training of the network scheduler based on the actor–critic strategy, we propose optimization methods for the training of MASA: reward dynamic alignment (RDA), earlier termination of the initial episodes, and asynchronous multi-agent training. The performance of the MASA is tested with classic directed acyclic graph and six real-world application datasets, respectively. Experimental results show that MASA outperforms other neural scheduling algorithms and heuristics, and ablation experiments illustrate how these training optimizations improve the network’s capacity. Full article
(This article belongs to the Special Issue Progress and Future Development of Real-Time Systems on Chip)
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Review

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16 pages, 1170 KiB  
Review
On-Chip Bus Protection against Soft Errors
by Ján Mach, Lukáš Kohútka and Pavel Čičák
Electronics 2023, 12(22), 4706; https://doi.org/10.3390/electronics12224706 - 19 Nov 2023
Cited by 2 | Viewed by 1584
Abstract
The increasing performance demands for processors leveraged in mission and safety-critical applications mean that the processors are implemented in smaller fabrication technologies, allowing a denser integration and higher operational frequency. Besides that, these applications require a high dependability and robustness level. The properties [...] Read more.
The increasing performance demands for processors leveraged in mission and safety-critical applications mean that the processors are implemented in smaller fabrication technologies, allowing a denser integration and higher operational frequency. Besides that, these applications require a high dependability and robustness level. The properties that provide higher performance also lead to higher susceptibility to transient faults caused by radiation. Many approaches exist for protecting individual processor cores, but the protection of interconnect buses is studied less. This paper describes the importance of protecting on-chip bus interconnects and reviews existing protection approaches used in processors for mission and safety-critical processors. The protection approaches are sorted into three groups: information, temporal, and spatial redundancy. Because the final selection of the protection approach depends on the use case and performance, power, and area demands, the three groups are compared according to their fundamental properties. For better context, the review also contains information about existing solutions for protecting the internal logic of the cores and external memories. This review should serve as an entry point to the domain of protecting the on-chip bus interconnect and interface of the core. Full article
(This article belongs to the Special Issue Progress and Future Development of Real-Time Systems on Chip)
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