FPGAs Explored: Pioneering Methods, Theories and Their Applications in Reconfigurable Computing

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: 15 April 2025 | Viewed by 2241

Special Issue Editors


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Guest Editor
Department of Electronics, Information and Bioengineering, Politecnico di Milano, 20133 Milano, Italy
Interests: FPGA; time-to-digital converters (TDC); digital electronics
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Guest Editor
Department of Electronics and Informatics (ETRO), Vrije Universiteit Brussel (VUB), 1050 Brussels, Belgium
Interests: reconfigurable computing; FPGA; biomedical devices; beamforming; microphone array; high-level synthesis; embedded medical systems; PPG signal processing
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

This Special Issue aims to explore the cutting-edge advancements, methodologies, and applications of field-programmable gate arrays (FPGAs) to provide a comprehensive overview of the current state and prospects of this technology.

FPGAs have become a pivotal technology in the landscape of reconfigurable computing, offering unmatched flexibility and speed in processing tasks, which can be altered dynamically to meet specific application needs. Over the past decade, the evolution of FPGA technology has been characterized by significant advancements in hardware efficiency, programming models, and application domains. The importance of FPGAs stems from their unique ability to be reconfigured post manufacture, allowing for the customization of hardware to optimize their performance of specific tasks. This has made them instrumental in areas where conventional fixed-logic devices, such as CPUs and GPUs, may not offer the same level of efficiency or flexibility. Their adaptability has opened new horizons in computational research and industry, facilitating rapid prototyping and energy-efficient computation, which is particularly crucial in today’s energy-conscious world. With the advent of high-level synthesis (HLS) tools, the barrier to designing with FPGAs has been significantly lowered, making them accessible to a broader range of developers and researchers. Looking ahead, the future of FPGA technology points towards their even greater integration with artificial intelligence frameworks, further improvements in their energy efficiency, and enhanced design tools that lower the learning curve for new users.

This issue seeks to map the actual state of FPGA architectures and the more powerful and state-of-the-art techniques used for designing, optimizing, and programming these devices, enhancing their performance and energy efficiency. Contributions may include, but are not limited to, advanced synthesis and optimization techniques for FPGAs, design methodologies and tools for reconfigurable computing, the security and reliability aspects of FPGA-based systems, and future research directions for this dynamic field.

Any application of an FPGA which highlights the benefit of using such a device is welcome. Moreover, we are also interested in papers highlighting the application of FPGAs in emerging fields such as deep learning, cloud computing, and big data analytics, showcasing their potential to accelerate complex algorithm processing and improve computational efficiency. Through case studies and practical applications, this Special Issue aims to provide a comprehensive overview of FPGAs and reconfigurable computing, offering insights into how these technologies can solve complex problems and lead to innovative solutions across various industries.

Dr. Fabio Garzetti
Dr. Bruno Da Silva
Guest Editors

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Keywords

  • FPGA
  • field-programmable gate arrays
  • reconfigurable computing
  • cloud computing
  • FPGA partial reconfiguration
  • SoC

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Published Papers (2 papers)

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Research

35 pages, 880 KiB  
Article
Harnessing FPGA Technology for Energy-Efficient Wearable Medical Devices
by Muhammad Iqbal Khan and Bruno da Silva
Electronics 2024, 13(20), 4094; https://doi.org/10.3390/electronics13204094 - 17 Oct 2024
Viewed by 853
Abstract
Over the past decade, wearable medical devices (WMDs) have become the norm for continuous health monitoring, enabling real-time vital sign analysis and preventive healthcare. These battery-powered devices face computational power, size, and energy resource constraints. Traditionally, low-power microcontrollers (MCUs) and application-specific integrated circuits [...] Read more.
Over the past decade, wearable medical devices (WMDs) have become the norm for continuous health monitoring, enabling real-time vital sign analysis and preventive healthcare. These battery-powered devices face computational power, size, and energy resource constraints. Traditionally, low-power microcontrollers (MCUs) and application-specific integrated circuits (ASICs) have been used for their energy efficiency. However, the increasing demand for multi-modal sensors and artificial intelligence (AI) requires more computational power than MCUs, and rapidly evolving AI asks for more flexibility, which ASICs lack. Field-programmable gate arrays (FPGAs), which are more efficient than MCUs and more flexible than ASICs, offer a potential solution when optimized for energy consumption. By combining real-time reconfigurability with intelligent energy optimization strategies, FPGAs can provide energy-efficient solutions for handling multimodal sensors and evolving AI requirements. This paper reviews low-power strategies toward FPGA-based WMD for physiological monitoring. It examines low-power FPGA families, highlighting their potential in power-sensitive applications. Future research directions are suggested, including exploring underutilized optimizations like sleep mode, voltage scaling, partial reconfiguration, and compressed learning and investigating underexplored flash and hybrid-based FPGAs. Overall, it provides guidelines for designing energy-efficient FPGA-based WMDs. Full article
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13 pages, 2865 KiB  
Article
An FPGA-Accelerated CNN with Parallelized Sum Pooling for Onboard Realtime Routing in Dynamic Low-Orbit Satellite Networks
by Hyeonwoo Kim, Juhyeon Park, Heoncheol Lee, Dongshik Won and Myonghun Han
Electronics 2024, 13(12), 2280; https://doi.org/10.3390/electronics13122280 - 11 Jun 2024
Cited by 1 | Viewed by 895
Abstract
This paper addresses the problem of real-time onboard routing for dynamic low earth orbit (LEO) satellite networks. It is difficult to apply general routing algorithms to dynamic LEO networks due to the frequent changes in satellite topology caused by the disconnection between moving [...] Read more.
This paper addresses the problem of real-time onboard routing for dynamic low earth orbit (LEO) satellite networks. It is difficult to apply general routing algorithms to dynamic LEO networks due to the frequent changes in satellite topology caused by the disconnection between moving satellites. Deep reinforcement learning (DRL) models trained by various dynamic networks can be considered. However, since the inference process with the DRL model requires too long a computation time due to multiple convolutional layer operations, it is not practical to apply to a real-time on-board computer (OBC) with limited computing resources. To solve the problem, this paper proposes a practical co-design method with heterogeneous processors to parallelize and accelerate a part of the multiple convolutional layer operations on a field-programmable gate array (FPGA). The proposed method was tested with a real heterogeneous processor-based OBC and showed that the proposed method was about 3.10 times faster than the conventional method while achieving the same routing results. Full article
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