Electronics

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14 pages, 4594 KiB

Open AccessArticle

Memristors Based on Many-Layer Non-Stoichiometric Germanosilicate Glass Films

by Ivan D. Yushkov, Liping Yin, Gennadiy N. Kamaev, Igor P. Prosvirin, Pavel V. Geydt, Michel Vergnat and Vladimir A. Volodin

Electronics 2023, 12(4), 873; https://doi.org/10.3390/electronics12040873 - 9 Feb 2023

Cited by 3 | Viewed by 1660

Abstract

Nonstoichiometric GeSi_xO_y glass films and many-layer structures based on them were obtained by high-vacuum electron beam vapor deposition (EBVD). Using EBVD, the GeO₂, SiO, SiO₂, or Ge powders were co-evaporated and deposited onto a cold (100 [...] Read more.

Nonstoichiometric GeSi_xO_y glass films and many-layer structures based on them were obtained by high-vacuum electron beam vapor deposition (EBVD). Using EBVD, the GeO₂, SiO, SiO₂, or Ge powders were co-evaporated and deposited onto a cold (100 °C) p⁺-Si(001) substrate with resistivity ρ = 0.0016 ± 0.0001 Ohm·cm. The as-deposited samples were studied by Fourier-transformed infrared spectroscopy, atomic force microscopy, X-ray photoelectron spectroscopy, and Raman spectroscopy. A transparent indium–tin–oxide (ITO) contact was deposited as the top electrode, and memristor metal–insulator–semiconductor (MIS) structures were fabricated. The current–voltage characteristics (I–V), as well as the resistive switching cycles of the MIS, have been studied. Reversible resistive switching (memristor effect) was observed for one-layer GeSi_0.9O_2.8, two-layer GeSi_0.9O_1.8/GeSi_0.9O_2.8 and GeSi_0.9O_1.8/SiO, and three-layer SiO₂/a–Ge/GeSi_0.9O_2.8 MIS structures. For a one-layer MIS structure, the number of rewriting cycles reached several thousand, while the memory window (the ratio of currents in the ON and OFF states) remained at 1–2 orders of magnitude. Intermediate resistance states were observed in many-layer structures. These states may be promising for use in multi-bit memristors and for simulating neural networks. In the three-layer MIS structure, resistive switching took place quite smoothly, and hysteresis was observed in the I–V characteristics; such a structure can be used as an “analog” memristor. Full article

(This article belongs to the Special Issue RRAM Devices: Multilevel State Control and Applications)

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15 pages, 2495 KiB

Open AccessArticle

Charge Transport Mechanism in the Forming-Free Memristor Based on PECVD Silicon Oxynitride

by Andrei A. Gismatulin, Gennadiy N. Kamaev, Vladimir A. Volodin and Vladimir A. Gritsenko

Electronics 2023, 12(3), 598; https://doi.org/10.3390/electronics12030598 - 25 Jan 2023

Cited by 1 | Viewed by 1645

Abstract

A memristor is a new generation memory that merges dynamic random access memory and flash properties. In addition, it can be used in neuromorphic electronics. The advantage of silicon oxynitride, as an active memristor layer, over other dielectrics it is compatibility with silicon [...] Read more.

A memristor is a new generation memory that merges dynamic random access memory and flash properties. In addition, it can be used in neuromorphic electronics. The advantage of silicon oxynitride, as an active memristor layer, over other dielectrics it is compatibility with silicon technology. It is expected that SiN_xO_y-based memristors will combine the advantages of memristors based on nonstoichiometric silicon oxides and silicon nitrides. In the present work, the plasma-enhanced chemical vapor deposition (PECVD) method was used to fabricate a silicon oxynitride-based memristor. The memristor leakage currents determine its power consumption. To minimize the power consumption, it is required to study the charge transport mechanism in the memristor in the high-resistance state and low-resistance state. The charge transport mechanism in the PECVD silicon oxynitride-based memristor in high and low resistance states cannot be described by the Schottky effect, thermally assisted tunneling model, Frenkel effect model of Coulomb isolated trap ionization, Hill–Adachi model of overlapping Coulomb potentials, Makram–Ebeid and Lannoo model of multiphonon isolated trap ionization, Nasyrov–Gritsenko model of phonon-assisted tunneling between traps, or the Shklovskii–Efros percolation model. The charge transport in the forming-free PECVD SiO_0.9N_0.6-based memristor in high and low resistance states is described by the space charge limited current model. The trap parameters responsible for the charge transport in various memristor states are determined. For the high-resistance state, the trap ionization energy W is 0.35 eV, and the trap concentration N_d is 1.7 × 10¹⁹ cm⁻³; for the low-resistance state, the trap ionization energy W is 0.01 eV, and the trap concentration N_t is 4.6 × 10¹⁷ cm⁻³. Full article

(This article belongs to the Special Issue RRAM Devices: Multilevel State Control and Applications)

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14 pages, 5769 KiB

Open AccessFeature PaperArticle

Modulating the Filamentary-Based Resistive Switching Properties of HfO₂ Memristive Devices by Adding Al₂O₃ Layers

by Mamathamba Kalishettyhalli Mahadevaiah, Eduardo Perez, Marco Lisker, Markus Andreas Schubert, Emilio Perez-Bosch Quesada, Christian Wenger and Andreas Mai

Electronics 2022, 11(10), 1540; https://doi.org/10.3390/electronics11101540 - 11 May 2022

Cited by 5 | Viewed by 2272

Abstract

The resistive switching properties of HfO₂ based 1T-1R memristive devices are electrically modified by adding ultra-thin layers of Al₂O₃ into the memristive device. Three different types of memristive stacks are fabricated in the 130 nm CMOS technology of IHP. [...] Read more.

The resistive switching properties of HfO₂ based 1T-1R memristive devices are electrically modified by adding ultra-thin layers of Al₂O₃ into the memristive device. Three different types of memristive stacks are fabricated in the 130 nm CMOS technology of IHP. The switching properties of the memristive devices are discussed with respect to forming voltages, low resistance state and high resistance state characteristics and their variabilities. The experimental I–V characteristics of set and reset operations are evaluated by using the quantum point contact model. The properties of the conduction filament in the on and off states of the memristive devices are discussed with respect to the model parameters obtained from the QPC fit. Full article

(This article belongs to the Special Issue RRAM Devices: Multilevel State Control and Applications)

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17 pages, 1670 KiB

Open AccessArticle

Ternary Neural Networks Based on on/off Memristors: Set-Up and Training

by Antoni Morell, Elvis Díaz Machado, Enrique Miranda, Guillem Boquet and Jose Lopez Vicario

Electronics 2022, 11(10), 1526; https://doi.org/10.3390/electronics11101526 - 10 May 2022

Cited by 2 | Viewed by 2454

Abstract

Neuromorphic systems based on hardware neural networks (HNNs) are expected to be an energy and time-efficient computing architecture for solving complex tasks. In this paper, we consider the implementation of deep neural networks (DNNs) using crossbar arrays of memristors. More specifically, we considered [...] Read more.

Neuromorphic systems based on hardware neural networks (HNNs) are expected to be an energy and time-efficient computing architecture for solving complex tasks. In this paper, we consider the implementation of deep neural networks (DNNs) using crossbar arrays of memristors. More specifically, we considered the case where such devices can be configured in just two states: the low-resistance state (LRS) and the high-resistance state (HRS). HNNs suffer from several non-idealities that need to be solved when mapping our software-based models. A clear example in memristor-based neural networks is conductance variability, which is inherent to resistive switching devices, so achieving good performance in an HNN largely depends on the development of reliable weight storage or, alternatively, mitigation techniques against weight uncertainty. In this manuscript, we provide guidelines for a system-level designer where we take into account several issues related to the set-up of the HNN, such as what the appropriate conductance value in the LRS is or the adaptive conversion of current outputs at one stage to input voltages for the next stage. A second contribution is the training of the system, which is performed via offline learning, and considering the hardware imperfections, which in this case are conductance fluctuations. Finally, the resulting inference system is tested in two well-known databases from MNIST, showing that is competitive in terms of classification performance against the software-based counterpart. Additional advice and insights on system tuning and expected performance are given throughout the paper. Full article

(This article belongs to the Special Issue RRAM Devices: Multilevel State Control and Applications)

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16 pages, 1296 KiB

Open AccessArticle

An Analysis on the Architecture and the Size of Quantized Hardware Neural Networks Based on Memristors

by Rocio Romero-Zaliz, Antonio Cantudo, Eduardo Perez, Francisco Jimenez-Molinos, Christian Wenger and Juan Bautista Roldan

Electronics 2021, 10(24), 3141; https://doi.org/10.3390/electronics10243141 - 17 Dec 2021

Cited by 4 | Viewed by 2754

Abstract

We have performed different simulation experiments in relation to hardware neural networks (NN) to analyze the role of the number of synapses for different NN architectures in the network accuracy, considering different datasets. A technology that stands upon 4-kbit 1T1R ReRAM arrays, where [...] Read more.

We have performed different simulation experiments in relation to hardware neural networks (NN) to analyze the role of the number of synapses for different NN architectures in the network accuracy, considering different datasets. A technology that stands upon 4-kbit 1T1R ReRAM arrays, where resistive switching devices based on

H f O_{2}

dielectrics are employed, is taken as a reference. In our study, fully dense (FdNN) and convolutional neural networks (CNN) were considered, where the NN size in terms of the number of synapses and of hidden layer neurons were varied. CNNs work better when the number of synapses to be used is limited. If quantized synaptic weights are included, we observed that NN accuracy decreases significantly as the number of synapses is reduced; in this respect, a trade-off between the number of synapses and the NN accuracy has to be achieved. Consequently, the CNN architecture must be carefully designed; in particular, it was noticed that different datasets need specific architectures according to their complexity to achieve good results. It was shown that due to the number of variables that can be changed in the optimization of a NN hardware implementation, a specific solution has to be worked in each case in terms of synaptic weight levels, NN architecture, etc. Full article

(This article belongs to the Special Issue RRAM Devices: Multilevel State Control and Applications)

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9 pages, 8417 KiB

Open AccessArticle

Influences of the Temperature on the Electrical Properties of HfO₂-Based Resistive Switching Devices

by Héctor García, Jonathan Boo, Guillermo Vinuesa, Óscar G. Ossorio, Benjamín Sahelices, Salvador Dueñas, Helena Castán, Mireia B. González and Francesca Campabadal

Electronics 2021, 10(22), 2816; https://doi.org/10.3390/electronics10222816 - 17 Nov 2021

Cited by 13 | Viewed by 2434

Abstract

In the attempt to understand the behavior of HfO

_{2}

-based resistive switching devices at low temperatures, TiN/Ti/HfO

_{2}

/W metal–insulator–metal devices were fabricated; the atomic layer deposition technique was used to grow the high-k layer. After performing an electroforming process at room [...] Read more.

In the attempt to understand the behavior of HfO

_{2}

-based resistive switching devices at low temperatures, TiN/Ti/HfO

_{2}

/W metal–insulator–metal devices were fabricated; the atomic layer deposition technique was used to grow the high-k layer. After performing an electroforming process at room temperature, the device was cooled in a cryostat to carry out 100 current–voltage cycles at several temperatures ranging from the “liquid nitrogen temperature” to 350 K. The measurements showed a semiconducting behavior in high and low resistance states. In the low resistance state, a hopping conduction mechanism was obtained. The set and reset voltages increased when temperature decreased because the thermal energies for oxygen vacancies and ions were reduced. However, the temperature did not influence the power absorbed in the reset transition, indicating the local temperature in the filament controls the transition. The set transition turned from gradual to abrupt when decreasing the temperature, due to a positive feedback between the current increase and the Joule heating at low temperatures. Full article

(This article belongs to the Special Issue RRAM Devices: Multilevel State Control and Applications)

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24 pages, 21801 KiB

Open AccessArticle

Assessment and Improvement of the Pattern Recognition Performance of Memdiode-Based Cross-Point Arrays with Randomly Distributed Stuck-at-Faults

by Fernando L. Aguirre, Sebastián M. Pazos, Félix Palumbo, Antoni Morell, Jordi Suñé and Enrique Miranda

Electronics 2021, 10(19), 2427; https://doi.org/10.3390/electronics10192427 - 6 Oct 2021

Cited by 3 | Viewed by 2412

Abstract

In this work, the effect of randomly distributed stuck-at faults (SAFs) in memristive cross-point array (CPA)-based single and multi-layer perceptrons (SLPs and MLPs, respectively) intended for pattern recognition tasks is investigated by means of realistic SPICE simulations. The quasi-static memdiode model (QMM) is [...] Read more.

In this work, the effect of randomly distributed stuck-at faults (SAFs) in memristive cross-point array (CPA)-based single and multi-layer perceptrons (SLPs and MLPs, respectively) intended for pattern recognition tasks is investigated by means of realistic SPICE simulations. The quasi-static memdiode model (QMM) is considered here for the modelling of the synaptic weights implemented with memristors. Following the standard memristive approach, the QMM comprises two coupled equations, one for the electron transport based on the double-diode equation with a single series resistance and a second equation for the internal memory state of the device based on the so-called logistic hysteron. By modifying the state parameter in the current-voltage characteristic, SAFs of different severeness are simulated and the final outcome is analysed. Supervised ex-situ training and two well-known image datasets involving hand-written digits and human faces are employed to assess the inference accuracy of the SLP as a function of the faulty device ratio. The roles played by the memristor’s electrical parameters, line resistance, mapping strategy, image pixelation, and fault type (stuck-at-ON or stuck-at-OFF) on the CPA performance are statistically analysed following a Monte-Carlo approach. Three different re-mapping schemes to help mitigate the effect of the SAFs in the SLP inference phase are thoroughly investigated. Full article

(This article belongs to the Special Issue RRAM Devices: Multilevel State Control and Applications)

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9 pages, 9392 KiB

Open AccessArticle

RRAM Random Number Generator Based on Train of Pulses

by Binbin Yang, Daniel Arumí, Salvador Manich, Álvaro Gómez-Pau, Rosa Rodríguez-Montañés, Mireia Bargalló González, Francesca Campabadal and Liang Fang

Electronics 2021, 10(15), 1831; https://doi.org/10.3390/electronics10151831 - 30 Jul 2021

Cited by 13 | Viewed by 2432

Abstract

In this paper, the modulation of the conductance levels of resistive random access memory (RRAM) devices is used for the generation of random numbers by applying a train of RESET pulses. The influence of the pulse amplitude and width on the device resistance [...] Read more.

In this paper, the modulation of the conductance levels of resistive random access memory (RRAM) devices is used for the generation of random numbers by applying a train of RESET pulses. The influence of the pulse amplitude and width on the device resistance is also analyzed. For each pulse characteristic, the number of pulses required to drive the device to a particular resistance threshold is variable, and it is exploited to extract random numbers. Based on this behavior, a random number generator (RNG) circuit is proposed. To assess the performance of the circuit, the National Institute of Standards and Technology (NIST) randomness tests are applied to evaluate the randomness of the bitstreams obtained. The experimental results show that four random bits are simultaneously obtained, passing all the applied tests without the need for post-processing. The presented method provides a new strategy to generate random numbers based on RRAMs for hardware security applications. Full article

(This article belongs to the Special Issue RRAM Devices: Multilevel State Control and Applications)

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