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Electronics
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Reconfigurable Digital Systems: Development and Applications
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Reconfigurable Digital Systems: Development and Applications

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (31 July 2021) | Viewed by 19495

Special Issue Editor

Dr. Iouliia Skliarova

E-Mail Website1 Website2
Guest Editor
Department of Electronics, Telecommunications and Informatics, IEETA, University of Aveiro, 3810-193 Aveiro, Portugal
Interests: reconfigurable computing; application-specific architectures; digital systems; object-oriented programming; combinatorial optimization; hardware description languages
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Reconfigurable digital systems are traditionally built on the basis of field-programmable gate arrays (FPGA). Currently, FPGA are part of heterogeneous computer platforms that combine different types of processing systems with new generations of programmable logic. FPGA-based systems can be specified, simulated, synthesized, and implemented with the aid of dedicated design environments. There exists a wide range of tools to specify the desired functionality, starting from high-level descriptions in commonly used programming languages down to block-based design and hardware description languages. Reconfigurable computing and FPGA technology have become major subjects of research as they have been identified as competitive alternatives to ASICs, CPUs and GPUs for developing efficient computing systems. Forecasts suggest that the impact of reconfigurable devices will continue to expand, and the range of applications will increase considerably in future.

The main aim of this Special Issue is to seek high-quality submissions that present and discuss the recent advances in the development of reconfigurable digital systems, especially focusing on application successes.

The topics of interest include, but are not limited to the following:

  • Design methods, tools, and compilers for reconfigurable digital systems
  • Algorithms implemented on reconfigurable hardware
  • Reconfigurable computing applications
  • Education for reconfigurable digital systems including courses, teaching and training experience, lab equipment, design and applications

Assist. Prof. Dr. Iouliia Skliarova
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • reconfigurable digital systems
  • design methods
  • hardware accelerators
  • reconfigurable computing applications
  • education experience

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Published Papers (6 papers)

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Research

17 pages, 1348 KiB  
Article
An Efficient On-Demand Hardware Replacement Platform for Metamorphic Functional Processing in Edge-Centric IoT Applications
by Hyeongyun Moon and Daejin Park
Electronics 2021, 10(17), 2088; https://doi.org/10.3390/electronics10172088 - 28 Aug 2021
Cited by 3 | Viewed by 1808
Abstract
The paradigm of Internet-of-things (IoT) systems is changing from a cloud-based system to an edge-based system. These changes were able to solve the delay caused by the rapid concentration of data in the communication network, the delay caused by the lack of server [...] Read more.
The paradigm of Internet-of-things (IoT) systems is changing from a cloud-based system to an edge-based system. These changes were able to solve the delay caused by the rapid concentration of data in the communication network, the delay caused by the lack of server computing capacity, and the security issues that occur in the data communication process. However, edge-based IoT systems performance was insufficient to process large numbers of data due to limited power supply, fixed hardware functions, and limited hardware resources. To improve their performance, application-specific hardware can be installed in edge devices, but performance cannot be improved except for specific applications due to a fixed function of an application-specific hardware. This paper introduces an edge-centric metamorphic IoT (mIoT) platform that can use various hardware modules through on-demand partial reconfiguration, despite the limited hardware resources of edge devices. In addition, this paper introduces an RISC-V based metamorphic IoT processor (mIoTP) with reconfigurable peripheral modules. We experimented to prove that the proposed structure can reduce the server access of edges and can be applied to a large-scale IoT system. Experiments were conducted in a single-edge environment and a large-scale environment combining one physical edge and 99 virtual edges. According to the experimental results, the edge-centric mIoT platform that executes the reconfiguration prediction algorithm at the edge was able to reduce the number of server accesses by up to 82.2% compared to our previous study in which the prediction process was executed at the server. Furthermore, we confirmed that there is no additional reconfiguration time overhead even for the large IoT systems. Full article
(This article belongs to the Special Issue Reconfigurable Digital Systems: Development and Applications)
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20 pages, 5366 KiB  
Article
Emulation of Circuits under Test Using Low-Cost Embedded Platforms
by José-María Guerrero-Rodríguez, Clemente Cobos Sánchez, Ángel Quirós-Olozábal and Juan A. Leñero-Bardallo
Electronics 2021, 10(16), 1990; https://doi.org/10.3390/electronics10161990 - 18 Aug 2021
Cited by 2 | Viewed by 3126
Abstract
Electrical engineering education requires the development of the specific ability and skills to address the design and assembly of practical electronic circuits, as well as the use of advanced electronic instrumentation. However, for electronic instrumentation courses or any other related specialty that pursues [...] Read more.
Electrical engineering education requires the development of the specific ability and skills to address the design and assembly of practical electronic circuits, as well as the use of advanced electronic instrumentation. However, for electronic instrumentation courses or any other related specialty that pursues to gain expertise testing a physical system, the circuit assembly process itself can represent a bottleneck in a practical session. The time dedicated to the circuit assembly is subtracted both to the measurements and the final decision-making time. Therefore, the student’s practical experience is limited. This article presents a reconfigurable physical system based on the Arduino™ shield pin-out, which (after specific programming) can virtually behave as a device under test to carry out measurement procedures on it, emulating any system or process. Although it has been mainly oriented to the Arduino boards, it is possible to add different control devices with a connector compatible. The user does not need to assemble any circuit. Our approach does not only pursue the correct instrument handling as a goal, but it also immerses the student in the context of the functional theory of the proposed circuit under test. Consequently, the same emulation platform can be utilized for other techno-scientific specialties, such as electrical engineering, automatic control systems or physics courses. Besides that, it is a compact product that can be adapted to the needs of any teaching institution. Full article
(This article belongs to the Special Issue Reconfigurable Digital Systems: Development and Applications)
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18 pages, 2617 KiB  
Article
Taylor-Series-Based Reconfigurability of Gamma Correction in Hardware Designs
by Dat Ngo and Bongsoon Kang
Electronics 2021, 10(16), 1959; https://doi.org/10.3390/electronics10161959 - 14 Aug 2021
Cited by 4 | Viewed by 4849
Abstract
Gamma correction is a common image processing technique that is common in video or still image systems. However, this simple and efficient method is typically expressed using the power law, which gives rise to practical difficulties in designing a reconfigurable hardware implementation. For [...] Read more.
Gamma correction is a common image processing technique that is common in video or still image systems. However, this simple and efficient method is typically expressed using the power law, which gives rise to practical difficulties in designing a reconfigurable hardware implementation. For example, the conventional approach calculates all possible outputs for a pre-determined gamma value, and this information is hardwired into memory components. As a result, reconfigurability is unattainable after deployment. This study proposes using the Taylor series to approximate gamma correction to overcome the aforementioned challenging problem, hence, facilitating the post-deployment reconfigurability of the hardware implementation. In other words, the gamma value is freely adjustable, resulting in the high appropriateness for offloading gamma correction onto its dedicated hardware in system-on-a-chip applications. Finally, the proposed hardware implementation is verified on Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit, and the results demonstrate its superiority against benchmark designs. Full article
(This article belongs to the Special Issue Reconfigurable Digital Systems: Development and Applications)
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27 pages, 1171 KiB  
Article
Utilizing Virtualized Hardware Logic Computations to Benefit Multi-User Performance
by Michael J. Hall, Neil E. Olson and Roger D. Chamberlain
Electronics 2021, 10(6), 665; https://doi.org/10.3390/electronics10060665 - 12 Mar 2021
Viewed by 2061
Abstract
Recent trends in computer architecture have increased the role of dedicated hardware logic as an effective approach to computation. Virtualization of logic computations (i.e., by sharing a fixed function) provides a means to effectively utilize hardware resources by context switching the logic to [...] Read more.
Recent trends in computer architecture have increased the role of dedicated hardware logic as an effective approach to computation. Virtualization of logic computations (i.e., by sharing a fixed function) provides a means to effectively utilize hardware resources by context switching the logic to support multiple data streams of computation. Multiple applications or users can take advantage of this by using the virtualized computation in an accelerator as a computational service, such as in a software as a service (SaaS) model over a network. In this paper, we analyze the performance of virtualized hardware logic and develop M/G/1 queueing model equations and simulation models to predict system performance. We predict system performance using the queueing model and tune a schedule for optimal performance. We observe that high variance and high load give high mean latency. The simulation models validate the queueing model, predict queue occupancy, show that a Poisson input process distribution (assumed in the queueing model) is reasonable for low load, and expand the set of scheduling algorithms considered. Full article
(This article belongs to the Special Issue Reconfigurable Digital Systems: Development and Applications)
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17 pages, 1632 KiB  
Article
Project-Based Learning and Evaluation in an Online Digital Design Course
by Iouliia Skliarova
Electronics 2021, 10(6), 646; https://doi.org/10.3390/electronics10060646 - 11 Mar 2021
Cited by 8 | Viewed by 3724
Abstract
This paper reports an experience of an abrupt shift from traditional teaching to distance learning within a course on digital system design using programmable logic platforms. The course organization and evaluation model had to be modified on the fly due to the COVID-19 [...] Read more.
This paper reports an experience of an abrupt shift from traditional teaching to distance learning within a course on digital system design using programmable logic platforms. The course organization and evaluation model had to be modified on the fly due to the COVID-19 pandemic. The adopted teaching and assessment methodology puts a strong focus on the laboratory component, assigning a very significant weight to project-based evaluation. As the access to laboratory equipment was cut, all the previously accumulated experience had to be modified and adapted to new circumstances. The paper discusses teaching methods employed within the course and analyzes in detail a project-based evaluation accentuated on modeling of a simplified processor. The advantages and drawbacks of the reported teaching methods are appointed. Possible design extensions are also suggested, which permit assigning the same core project to different students. We believe that the proposed project is a valuable instructional tool, in particular, for remote learning/assessment. Full article
(This article belongs to the Special Issue Reconfigurable Digital Systems: Development and Applications)
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17 pages, 641 KiB  
Article
Methodology of Firmware Development for ARUZ—An FPGA-Based HPC System
by Rafał Kiełbik, Kamil Rudnicki, Zbigniew Mudza and Jarosław Jung
Electronics 2020, 9(9), 1482; https://doi.org/10.3390/electronics9091482 - 10 Sep 2020
Cited by 4 | Viewed by 2809
Abstract
ARUZ is a large scale, massively parallel, FPGA-based reconfigurable computational system dedicated primarily to molecular analysis. This paper presents a methodology for ARUZ firmware development that simplifies the process, offers low-level optimization, and facilitates verification. According to this methodology, firstly an expanded, generic, [...] Read more.
ARUZ is a large scale, massively parallel, FPGA-based reconfigurable computational system dedicated primarily to molecular analysis. This paper presents a methodology for ARUZ firmware development that simplifies the process, offers low-level optimization, and facilitates verification. According to this methodology, firstly an expanded, generic, all-in-one VHDL description of variable Processing Elements (PEs) is developed manually. GCC preprocessing is then used to extract only the desired target functionality. A dedicated software instantiates and connects PEs in form of a scalable network, divides it into subsets for chips and generates its HDL description. As a result, individual HDL-coded specification, optimized for certain analysis, is provided for the synthesis tool. Code reuse and automated generation of up to 81% of the code economizes the workload. Using well-optimized VHDL for core description rather than High Level Synthesis eliminates unnecessary overhead. The PE network can be scaled inversely proportional to PEs complexity, in order to efficiently utilize available resources. Moreover, downscaling the problem makes verification during HDL simulations and testing the prototype systems easier. Full article
(This article belongs to the Special Issue Reconfigurable Digital Systems: Development and Applications)
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