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A special issue of Materials (ISSN 1996-1944). This special issue belongs to the section "Electronic Materials".

Deadline for manuscript submissions: closed (29 February 2020) | Viewed by 38975

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Special Issue Editors

Prof. Antonio García-Loureiro

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Guest Editor

CITIUS, Universidade de Santiago de Compostela, 15782 Santiago de Compostela, Galicia, Spain
Interests: semiconductor modelling; variability studies; high performance computing

Prof. Karol Kalna

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Guest Editor

Nanoelectronic Devices Computational Group, College of Engineering, Bay Campus Swansea University, Fabian Way, Crymlyn Burrows SA1 8EN, UK
Interests: simulations of semiconductor devices; wide-bandgap semiconductor devices; ensemble Monte Carlo simulations

Dr. Natalia Seoane

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Guest Editor

CITIUS, Universidade de Santiago de Compostela, 15782 Santiago de Compostela, Galicia, Spain
Interests: simulations of semiconductor devices; variability effects; nanowires; FinFETS

Special Issue Information

Dear Colleagues,

In the last few years, the main semiconductor industries have introduced multi-gate non-planar transistors in their core business with applications to memories and logical integrated circuits in order to achieve a larger integration on chip, increase performance, and reduce energy consumption. There is intense research underway to keep developing these devices and address their limitations in order to continue transistor scaling while further improving performance.

Nanowire Field-Effect Transistors (NW-FETs) are nowadays one of the strongest contenders to replace Fin Field-Effect Transistors (FinFETs) in the following technological nodes, because of their superior electrostatic control of the channel transport via a gate-all-around gate.

This Special Issue represents a good opportunity for researchers around the world to disseminate their recent progress related to NW-FETs, from three different points of view: Physics, technology and modelling. Therefore, of particular interest for this Special Issue are material properties, fabrication, design optimization, characterization, numerical and analytical modelling, and variability and circuit design.

If you need any further information about this Special Issue, please do not hesitate to contact me.

Prof. Antonio García-Loureiro
Prof. Karol Kalna
Dr. Natalia Seoane
Guest Editors

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Keywords

nanowire Field-Effect Transistors
material properties
fabrication
modelling
circuit design
variability

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Editorial

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2 pages, 190 KiB

Open AccessEditorial

Special Issue: Nanowire Field-Effect Transistor (FET)

by Natalia Seoane, Antonio García-Loureiro and Karol Kalna

Materials 2020, 13(8), 1845; https://doi.org/10.3390/ma13081845 - 14 Apr 2020

Cited by 7 | Viewed by 2263

Abstract

This Special Issue looks at recent developments in the research field of Nanowire Field-Effect Transistors (NW-FETs), covering different aspects of technology, physics, and modelling of these nanoscale devices. In this summary, we present seven outstanding articles on NW-FETs by providing a brief overview [...] Read more.

(This article belongs to the Special Issue Nanowire Field-Effect Transistor (FET))

Research

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16 pages, 805 KiB

Open AccessFeature PaperArticle

Effective 1D Time-Dependent Schrödinger Equations for 3D Geometrically Correlated Systems

by Devashish Pandey, Xavier Oriols and Guillermo Albareda

Materials 2020, 13(13), 3033; https://doi.org/10.3390/ma13133033 - 7 Jul 2020

Viewed by 2639

Abstract

The so-called Born–Huang ansatz is a fundamental tool in the context of ab-initio molecular dynamics, viz., it allows effectively separating fast and slow degrees of freedom and thus treating electrons and nuclei with different mathematical footings. Here, we consider the use of a Born–Huang-like expansion of the three-dimensional time-dependent Schrödinger equation to separate transport and confinement degrees of freedom in electron transport problems that involve geometrical constrictions. The resulting scheme consists of an eigenstate problem for the confinement degrees of freedom (in the transverse direction) whose solution constitutes the input for the propagation of a set of coupled one-dimensional equations of motion for the transport degree of freedom (in the longitudinal direction). This technique achieves quantitative accuracy using an order less computational resources than the full dimensional simulation for a typical two-dimensional geometrical constriction and upto three orders for three-dimensional constriction. Full article

(This article belongs to the Special Issue Nanowire Field-Effect Transistor (FET))

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9 pages, 3136 KiB

Open AccessFeature PaperArticle

Effects of Applied Voltages on the Charge Transport Properties in a ZnO Nanowire Field Effect Transistor

by Jongwon Yoon, Fu Huang, Ki Hoon Shin, Jung Inn Sohn and Woong-Ki Hong

Materials 2020, 13(2), 268; https://doi.org/10.3390/ma13020268 - 7 Jan 2020

Cited by 11 | Viewed by 3320

Abstract

We investigate the effect of applied gate and drain voltages on the charge transport properties in a zinc oxide (ZnO) nanowire field effect transistor (FET) through temperature- and voltage-dependent measurements. Since the FET based on nanowires is one of the fundamental building blocks in potential nanoelectronic applications, it is important to understand the transport properties relevant to the variation in electrically applied parameters for devices based on nanowires with a large surface-to-volume ratio. In this work, the threshold voltage shift due to a drain-induced barrier-lowering (DIBL) effect was observed using a Y-function method. From temperature-dependent current-voltage (I-V) analyses of the fabricated ZnO nanowire FET, it is found that space charge-limited conduction (SCLC) mechanism is dominant at low temperatures and low voltages; in particular, variable-range hopping dominates the conduction in the temperature regime from 4 to 100 K, whereas in the high-temperature regime (150–300 K), the thermal activation transport is dominant, diminishing the SCLC effect. These results are discussed and explained in terms of the exponential distribution and applied voltage-induced variation in the charge trap states at the band edge. Full article

(This article belongs to the Special Issue Nanowire Field-Effect Transistor (FET))

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15 pages, 2193 KiB

Open AccessFeature PaperArticle

A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs

by Natalia Seoane, Daniel Nagy, Guillermo Indalecio, Gabriel Espiñeira, Karol Kalna and Antonio García-Loureiro

Materials 2019, 12(15), 2391; https://doi.org/10.3390/ma12152391 - 26 Jul 2019

Cited by 22 | Viewed by 3486

Abstract

An in-house-built three-dimensional multi-method semi-classical/classical toolbox has been developed to characterise the performance, scalability, and variability of state-of-the-art semiconductor devices. To demonstrate capabilities of the toolbox, a 10 nm gate length Si gate-all-around field-effect transistor is selected as a benchmark device. The device [...] Read more.

I_{OFF}

) of

0.03

μ

μ

m, and an on-current (

I_{ON}

) of 1770

μ

μ

m, with the

I_{ON} / I_{OFF}

ratio

6.63 \times 10^{4}

, a value

27 %

larger than that of a

10.7

nm gate length Si FinFET. The device SS is 71 mV/dec, no far from the ideal limit of 60 mV/dec. The threshold voltage standard deviation due to statistical combination of four sources of variability (line- and gate-edge roughness, metal grain granularity, and random dopants) is

55.5

mV, a value noticeably larger than that of the equivalent FinFET (30 mV). Finally, using a fluctuation sensitivity map, we establish which regions of the device are the most sensitive to the line-edge roughness and the metal grain granularity variability effects. The on-current of the device is strongly affected by any line-edge roughness taking place near the source-gate junction or by metal grains localised between the middle of the gate and the proximity of the gate-source junction. Full article

(This article belongs to the Special Issue Nanowire Field-Effect Transistor (FET))

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12 pages, 4105 KiB

Open AccessArticle

Characteristic Fluctuations of Dynamic Power Delay Induced by Random Nanosized Titanium Nitride Grains and the Aspect Ratio Effect of Gate-All-Around Nanowire CMOS Devices and Circuits

by Yiming Li, Chieh-Yang Chen, Min-Hui Chuang and Pei-Jung Chao

Materials 2019, 12(9), 1492; https://doi.org/10.3390/ma12091492 - 8 May 2019

Cited by 6 | Viewed by 3269

Abstract

In this study, we investigate direct current (DC)/alternating current (AC) characteristic variability induced by work function fluctuation (WKF) with respect to different nanosized metal grains and the variation of aspect ratios (ARs) of channel cross-sections on a 10 nm gate gate-all-around (GAA) nanowire (NW) metal–oxide–semiconductor field-effect transistor (MOSFET) device. The associated timing and power fluctuations of the GAA NW complementary metal–oxide–semiconductor (CMOS) circuits are further estimated and analyzed simultaneously. The experimentally validated device and circuit simulation running on a parallel computing system are intensively performed while considering the effects of WKF and various ARs to access the device’s nominal and fluctuated characteristics. To provide the best accuracy of simulation, we herein calibrate the simulation results and experimental data by adjusting the fitting parameters of the mobility model. Transfer characteristics, dynamic timing, and power consumption of the tested circuit are calculated using a mixed device–circuit simulation technique. The timing fluctuation mainly follows the trend of the variation of threshold voltage. The fluctuation terms of power consumption comprising static, short-circuit, and dynamic powers are governed by the trend that the larger the grain size, the larger the fluctuation. Full article

(This article belongs to the Special Issue Nanowire Field-Effect Transistor (FET))

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11 pages, 1688 KiB

Open AccessArticle

Simulation of the Impact of Ionized Impurity Scattering on the Total Mobility in Si Nanowire Transistors

by Toufik Sadi, Cristina Medina-Bailon, Mihail Nedjalkov, Jaehyun Lee, Oves Badami, Salim Berrada, Hamilton Carrillo-Nunez, Vihar Georgiev, Siegfried Selberherr and Asen Asenov

Materials 2019, 12(1), 124; https://doi.org/10.3390/ma12010124 - 2 Jan 2019

Cited by 21 | Viewed by 5933

Abstract

Nanowire transistors (NWTs) are being considered as possible candidates for replacing FinFETs, especially for CMOS scaling beyond the 5-nm node, due to their better electrostatic integrity. Hence, there is an urgent need to develop reliable simulation methods to provide deeper insight into NWTs’ physics and operation, and unlock the devices’ technological potential. One simulation approach that delivers reliable mobility values at low-field near-equilibrium conditions is the combination of the quantum confinement effects with the semi-classical Boltzmann transport equation, solved within the relaxation time approximation adopting the Kubo–Greenwood (KG) formalism, as implemented in this work. We consider the most relevant scattering mechanisms governing intraband and multi-subband transitions in NWTs, including phonon, surface roughness and ionized impurity scattering, whose rates have been calculated directly from the Fermi’s Golden rule. In this paper, we couple multi-slice Poisson–Schrödinger solutions to the KG method to analyze the impact of various scattering mechanisms on the mobility of small diameter nanowire transistors. As demonstrated here, phonon and surface roughness scattering are strong mobility-limiting mechanisms in NWTs. However, scattering from ionized impurities has proved to be another important mobility-limiting mechanism, being mandatory for inclusion when simulating realistic and doped nanostructures, due to the short range Coulomb interaction with the carriers. We also illustrate the impact of the nanowire geometry, highlighting the advantage of using circular over square cross section shapes. Full article

(This article belongs to the Special Issue Nanowire Field-Effect Transistor (FET))

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6 pages, 3079 KiB

Open AccessArticle

InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities

by Clarissa Convertino, Cezar Zota, Heinz Schmid, Daniele Caimi, Marilyne Sousa, Kirsten Moselund and Lukas Czornomaz

Materials 2019, 12(1), 87; https://doi.org/10.3390/ma12010087 - 27 Dec 2018

Cited by 29 | Viewed by 4740

Abstract

III-V semiconductors are being considered as promising candidates to replace silicon channel for low-power logic and RF applications in advanced technology nodes. InGaAs is particularly suitable as the channel material in n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), due to its high electron mobility. In the present work, we report on InGaAs FinFETs monolithically integrated on silicon substrates. The InGaAs channels are created by metal–organic chemical vapor deposition (MOCVD) epitaxial growth within oxide cavities, a technique referred to as template-assisted selective epitaxy (TASE), which allows for the local integration of different III-V semiconductors on silicon. FinFETs with a gate length down to 20nm are fabricated based on a CMOS-compatible replacement-metal-gate process flow. This includes self-aligned source-drain n⁺ InGaAs regrown contacts as well as 4 nm source-drain spacers for gate-contacts isolation. The InGaAs material was examined by scanning transmission electron microscopy (STEM) and the epitaxial structures showed good crystal quality. Furthermore, we demonstrate a controlled InGaAs digital etching process to create doped extensions underneath the source-drain spacer regions. We report a device with gate length of 90 nm and fin width of 40 nm showing on-current of 100 µA/µm and subthreshold slope of about 85 mV/dec. Full article

(This article belongs to the Special Issue Nanowire Field-Effect Transistor (FET))

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12 pages, 816 KiB

Open AccessArticle

Physics of Discrete Impurities under the Framework of Device Simulations for Nanostructure Devices

by Nobuyuki Sano, Katsuhisa Yoshida, Chih-Wei Yao and Hiroshi Watanabe

Materials 2018, 11(12), 2559; https://doi.org/10.3390/ma11122559 - 16 Dec 2018

Cited by 12 | Viewed by 3207

Abstract

Localized impurities doped in the semiconductor substrate of nanostructure devices play an essential role in understanding and resolving transport and variability issues in device characteristics. Modeling discrete impurities under the framework of device simulations is, therefore, an urgent need for reliable prediction of device performance via device simulations. In the present paper, we discuss the details of the physics associated with localized impurities in nanostructure devices, which are inherent, yet nontrivial, to any device simulation schemes: The physical interpretation and the role of electrostatic Coulomb potential in device simulations are clarified. We then show that a naive introduction of localized impurities into the Poisson equation leads to a logical inconsistency within the framework of the drift-diffusion simulations. We describe a systematic methodology for how to treat the Coulomb potential consistently with both the Poisson and current-continuity (transport) equations. The methodology is extended to the case of nanostructure devices so that the effects of the interface between different materials are taken into account. Full article

(This article belongs to the Special Issue Nanowire Field-Effect Transistor (FET))

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Review

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42 pages, 9756 KiB

Open AccessReview

Quantum Transport in a Silicon Nanowire FET Transistor: Hot Electrons and Local Power Dissipation

by Antonio Martinez and John R. Barker

Materials 2020, 13(15), 3326; https://doi.org/10.3390/ma13153326 - 26 Jul 2020

Cited by 7 | Viewed by 4524

Abstract

A review and perspective is presented of the classical, semi-classical and fully quantum routes to the simulation of electro-thermal phenomena in ultra-scaled silicon nanowire field-effect transistors. It is shown that the physics of ultra-scaled devices requires at least a coupled electron quantum transport semi-classical heat equation model outlined here. The importance of the local density of states (LDOS) is discussed from classical to fully quantum versions. It is shown that the minimal quantum approach requires self-consistency with the Poisson equation and that the electronic LDOS must be determined within at least the self-consistent Born approximation. To bring in this description and to provide the energy resolved local carrier distributions it is necessary to adopt the non-equilibrium Green function (NEGF) formalism, briefly surveyed here. The NEGF approach describes quantum coherent and dissipative transport, Pauli exclusion and non-equilibrium conditions inside the device. There are two extremes of NEGF used in the community. The most fundamental is based on coupled equations for the Green functions electrons and phonons that are computed at the atomically resolved level within the nanowire channel and into the surrounding device structure using a tight binding Hamiltonian. It has the advantage of treating both the non-equilibrium heat flow within the electron and phonon systems even when the phonon energy distributions are not described by a temperature model. The disadvantage is the grand challenge level of computational complexity. The second approach, that we focus on here, is more useful for fast multiple simulations of devices important for TCAD (Technology Computer Aided Design). It retains the fundamental quantum transport model for the electrons but subsumes the description of the energy distribution of the local phonon sub-system statistics into a semi-classical Fourier heat equation that is sourced by the local heat dissipation from the electron system. It is shown that this self-consistent approach retains the salient features of the full-scale approach. For focus, we outline our electro-thermal simulations for a typical narrow Si nanowire gate all-around field-effect transistor. The self-consistent Born approximation is used to describe electron-phonon scattering as the source of heat dissipation to the lattice. We calculated the effect of the device self-heating on the current voltage characteristics. Our fast and simpler methodology closely reproduces the results of a more fundamental compute-intensive calculations in which the phonon system is treated on the same footing as the electron system. We computed the local power dissipation and “local lattice temperature” profiles. We compared the self-heating using hot electron heating and the Joule heating, i.e., assuming the electron system was in local equilibrium with the potential. Our simulations show that at low bias the source region of the device has a tendency to cool down for the case of the hot electron heating but not for the case of Joule heating. Our methodology opens the possibility of studying thermoelectricity at nano-scales in an accurate and computationally efficient way. At nano-scales, coherence and hot electrons play a major role. It was found that the overall behaviour of the electron system is dominated by the local density of states and the scattering rate. Electrons leaving the simulated drain region were found to be far from equilibrium. Full article

(This article belongs to the Special Issue Nanowire Field-Effect Transistor (FET))

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16 pages, 1563 KiB

Open AccessReview

Quantum Treatment of Inelastic Interactions for the Modeling of Nanowire Field-Effect Transistors

by Youseung Lee, Demetrio Logoteta, Nicolas Cavassilas, Michel Lannoo, Mathieu Luisier and Marc Bescond

Materials 2020, 13(1), 60; https://doi.org/10.3390/ma13010060 - 21 Dec 2019

Cited by 6 | Viewed by 3026

Abstract

During the last decades, the Nonequilibrium Green’s function (NEGF) formalism has been proposed to develop nano-scaled device-simulation tools since it is especially convenient to deal with open device systems on a quantum-mechanical base and allows the treatment of inelastic scattering. In particular, it is able to account for inelastic effects on the electronic and thermal current, originating from the interactions of electron–phonon and phonon–phonon, respectively. However, the treatment of inelastic mechanisms within the NEGF framework usually relies on a numerically expensive scheme, implementing the self-consistent Born approximation (SCBA). In this article, we review an alternative approach, the so-called Lowest Order Approximation (LOA), which is realized by a rescaling technique and coupled with Padé approximants, to efficiently model inelastic scattering in nanostructures. Its main advantage is to provide a numerically efficient and physically meaningful quantum treatment of scattering processes. This approach is successfully applied to the three-dimensional (3D) atomistic quantum transport OMEN code to study the impact of electron–phonon and anharmonic phonon–phonon scattering in nanowire field-effect transistors. A reduction of the computational time by about ×6 for the electronic current and ×2 for the thermal current calculation is obtained. We also review the possibility to apply the first-order Richardson extrapolation to the Padé N/N − 1 sequence in order to accelerate the convergence of divergent LOA series. More in general, the reviewed approach shows the potentiality to significantly and systematically lighten the computational burden associated to the atomistic quantum simulations of dissipative transport in realistic 3D systems. Full article

(This article belongs to the Special Issue Nanowire Field-Effect Transistor (FET))

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