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Micromachines
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Emerging CMOS Devices, Volume II
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Emerging CMOS Devices, Volume II

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "D1: Semiconductor Devices".

Deadline for manuscript submissions: closed (10 March 2023) | Viewed by 13932

Special Issue Editors

Prof. Dr. Carlos Sampedro

E-Mail Website
Guest Editor
Department of Electronics and Computer Technology, University of Granada, 18071 Granada, Spain
Interests: advanced device simulation; Monte Carlo; CMOS co-integration; 2D materials
Special Issues, Collections and Topics in MDPI journals
Dr. Cristina Medina Bailón

E-Mail Website
Guest Editor
Nanoelectronics Research Group, Department of Electronics and Computer Technology, University of Granada, 18071 Granada, Spain
Interests: advanced simulation of semiconductor devices; semi-classical methods; Ensemble Monte Carlo simulations; high performance computing

Special Issue Information

Dear Colleagues,

The next decade presents significant challenges for the electronic community where different technologies will provide solutions in the emerging fields of big data, Internet of Things, and artificial intelligence. In this scenario of electronic systems ubiquity, new CMOS device paradigms are being developed to fulfill future requirements and to be co-integrated with other emerging technologies, including 2D materials. Great efforts are being made by industry and academia in the fields of fabrication, advanced simulation, characterization, and design to determine the emerging CMOS devices that will perform in future systems. Reconfigurable MOS, TFETs, 1TDRAM, MOS-based biosensors, and CMOS on non-conventional substrates and 2D materials will be key devices in future applications. In this Special Issue of Micromachines, researchers and developers are invited to submit manuscripts for the Special Issue “Emerging CMOS Devices”, where we will focus on advancements in the fabrication, simulation, and characterization of different electronic structures. This Special Issue welcomes articles and review articles that cover a broad range of possible topics, including, but not limited to, fabrication, simulation, and characterization of emerging CMOS devices, new channel materials for CMOS, 2D material-based CMOS applications, CMOS co-integration, nanometer-scale devices, alternative transistor architectures, or emerging memory devices. All submissions will be reviewed in accordance with the normal procedures of Micromachines.

We look forward to receiving your submissions!

Prof. Dr. Carlos Sampedro
Dr. Cristina Medina Bailón
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • nanometer-scale devices: technology, characterization techniques, and evaluation metrics for high performance, low power, low standby power, high frequency, and memory applications
  • alternative transistor architectures including FDSOI, DGSOI, FinFET, MuGFET, vertical MOSFET, Nanowires, FeFET and Tunnel FET, MEMS/NEMS, Beyond-CMOS nanoelectronic devices
  • new functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain, nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.
  • emerging memory devices
  • CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling. Three-dimensional integration of devices and circuits, heterogeneous integration
  • advanced test structures and characterization techniques, parameter extraction, reliability, and variability assessment techniques for new materials and novel devices
  • new channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V, and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials
  • properties of ultra-thin films and buried oxides, defects, interface quality. Thin gate dielectrics: high-κ materials for switches and memory
  • modeling and simulation of all types of semiconductor devices, including FinFETs, GAA FETs, ultra-thin SOI devices, emerging memory devices, new material-based nanodevices, optoelectronic devices, TFTs, sensors, power electronic devices, spintronic devices, tunnel FETs, SETs, organic electronic devices, and bioelectronic devices
  • modeling and simulation of all sorts of semiconductor processes, including first principles material design, and growth simulation of nano-scale fabrication
  • fundamental aspects of device modeling and simulation, including quantum transport, thermal transport, fluctuation, noise, and reliability
  • compact modeling for circuit simulation, including low-power, high frequency, and power electronics applications
  • process/device/circuit co-simulation in context with system design and verification
  • equipment, topography, lithography modeling
  • interconnect modeling, including noise and parasitic effects
  • numerical methods and algorithms, including grid generation, user-interface, and visualization
  • metrology for the modeling of semiconductor devices and processes
  • multiscale approach from First Principles to TCAD simulations
  • estimation with TCAD and machine learning
  • neuromorphic devices and quantum computing
  • multi-physics simulation

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Published Papers (5 papers)

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22 pages, 5205 KiB  
Article
FinFET 6T-SRAM All-Digital Compute-in-Memory for Artificial Intelligence Applications: An Overview and Analysis
by Waqas Gul, Maitham Shams and Dhamin Al-Khalili
Micromachines 2023, 14(8), 1535; https://doi.org/10.3390/mi14081535 - 31 Jul 2023
Cited by 4 | Viewed by 3394
Abstract
Artificial intelligence (AI) has revolutionized present-day life through automation and independent decision-making capabilities. For AI hardware implementations, the 6T-SRAM cell is a suitable candidate due to its performance edge over its counterparts. However, modern AI hardware such as neural networks (NNs) access off-chip [...] Read more.
Artificial intelligence (AI) has revolutionized present-day life through automation and independent decision-making capabilities. For AI hardware implementations, the 6T-SRAM cell is a suitable candidate due to its performance edge over its counterparts. However, modern AI hardware such as neural networks (NNs) access off-chip data quite often, degrading the overall system performance. Compute-in-memory (CIM) reduces off-chip data access transactions. One CIM approach is based on the mixed-signal domain, but it suffers from limited bit precision and signal margin issues. An alternate emerging approach uses the all-digital signal domain that provides better signal margins and bit precision; however, it will be at the expense of hardware overhead. We have analyzed digital signal domain CIM silicon-verified 6T-SRAM CIM solutions, after classifying them as SRAM-based accelerators, i.e., near-memory computing (NMC), and custom SRAM-based CIM, i.e., in-memory-computing (IMC). We have focused on multiply and accumulate (MAC) as the most frequent operation in convolution neural networks (CNNs) and compared state-of-the-art implementations. Neural networks with low weight precision, i.e., <12b, show lower accuracy but higher power efficiency. An input precision of 8b achieves implementation requirements. The maximum performance reported is 7.49 TOPS at 330 MHz, while custom SRAM-based performance has shown a maximum of 5.6 GOPS at 100 MHz. The second part of this article analyzes the FinFET 6T-SRAM as one of the critical components in determining overall performance of an AI computing system. We have investigated the FinFET 6T-SRAM cell performance and limitations as dictated by the FinFET technology-specific parameters, such as sizing, threshold voltage (Vth), supply voltage (VDD), and process and environmental variations. The HD FinFET 6T-SRAM cell shows 32% lower read access time and 1.09 times better leakage power as compared with the HC cell configuration. The minimum achievable supply voltage is 600 mV without utilization of any read- or write-assist scheme for all cell configurations, while temperature variations show noise margin deviation of up to 22% of the nominal values. Full article
(This article belongs to the Special Issue Emerging CMOS Devices, Volume II)
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15 pages, 896 KiB  
Article
A Physics-Informed Automatic Neural Network Generation Framework for Emerging Device Modeling
by Guangxin Guo, Hailong You, Cong Li, Zhengguang Tang and Ouwen Li
Micromachines 2023, 14(6), 1150; https://doi.org/10.3390/mi14061150 - 29 May 2023
Cited by 1 | Viewed by 2675
Abstract
With the rapid development of semiconductor technology, traditional equation-based modeling faces challenges in accuracy and development time. To overcome these limitations, neural network (NN)-based modeling methods have been proposed. However, the NN-based compact model encounters two major issues. Firstly, it exhibits unphysical behaviors [...] Read more.
With the rapid development of semiconductor technology, traditional equation-based modeling faces challenges in accuracy and development time. To overcome these limitations, neural network (NN)-based modeling methods have been proposed. However, the NN-based compact model encounters two major issues. Firstly, it exhibits unphysical behaviors such as un-smoothness and non-monotonicity, which hinder its practical use. Secondly, finding an appropriate NN structure with high accuracy requires expertise and is time-consuming. In this paper, we propose an Automatic Physical-Informed Neural Network (AutoPINN) generation framework to solve these challenges. The framework consists of two parts: the Physics-Informed Neural Network (PINN) and the two-step Automatic Neural Network (AutoNN). The PINN is introduced to resolve unphysical issues by incorporating physical information. The AutoNN assists the PINN in automatically determining an optimal structure without human involvement. We evaluate the proposed AutoPINN framework on the gate-all-around transistor device. The results demonstrate that AutoPINN achieves an error of less than 0.05%. The generalization of our NN is promising, as validated by the test error and the loss landscape. The results demonstrate smoothness in high-order derivatives, and the monotonicity can be well-preserved. We believe that this work has the potential to accelerate the development and simulation process of emerging devices. Full article
(This article belongs to the Special Issue Emerging CMOS Devices, Volume II)
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14 pages, 9852 KiB  
Article
Improvement of AlGaN/GaN HEMTs Linearity Using Etched-Fin Gate Structure for Ka Band Applications
by Ming-Wen Lee, Yueh-Chin Lin, Heng-Tung Hsu, Francisco Gamiz and Edward-Yi Chang
Micromachines 2023, 14(5), 931; https://doi.org/10.3390/mi14050931 - 25 Apr 2023
Cited by 4 | Viewed by 2362
Abstract
In this paper, AlGaN/GaN high electron mobility transistors (HEMTs) with etched-fin gate structures fabricated to improve device linearity for Ka-band application are reported. Within the proposed study of planar, one-etched-fin, four-etched-fin, and nine-etched-fin devices, which have 50-μm, 25-μm, 10-μm, and 5-μm partial gate [...] Read more.
In this paper, AlGaN/GaN high electron mobility transistors (HEMTs) with etched-fin gate structures fabricated to improve device linearity for Ka-band application are reported. Within the proposed study of planar, one-etched-fin, four-etched-fin, and nine-etched-fin devices, which have 50-μm, 25-μm, 10-μm, and 5-μm partial gate widths, respectively, the four-etched-fin gate AlGaN/GaN HEMT devices have demonstrated optimized device linearity with respect to the extrinsic transconductance (Gm) value, the output third order intercept point (OIP3), and the third-order intermodulation output power (IMD3) level. The IMD3 is improved by 7 dB at 30 GHz for the 4 × 50 μm HEMT device. The OIP3 is found to reach a maximum value of 36.43 dBm with the four-etched-fin device, which exhibits high potential for the advancement of wireless power amplifier components for Ka band applications. Full article
(This article belongs to the Special Issue Emerging CMOS Devices, Volume II)
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14 pages, 6249 KiB  
Article
Expanding the Set of Three-Input Logic Functions in Inverted T-Shaped TFETs
by Hao Ye, Pengjun Wang, Gang Li, Yijian Shi, Bo Chen, Xiangyu Li and Jianping Hu
Micromachines 2023, 14(2), 445; https://doi.org/10.3390/mi14020445 - 14 Feb 2023
Viewed by 1680
Abstract
Three-input logic primitives show high efficiency in logic synthesis compared to traditional two-input logic, which encourages researchers to implement three-input logic gates with emerging nanotechnologies. This paper demonstrates a compact implementation of three-input monotone logic gates based on the inverted T-shaped TFET. Firstly, [...] Read more.
Three-input logic primitives show high efficiency in logic synthesis compared to traditional two-input logic, which encourages researchers to implement three-input logic gates with emerging nanotechnologies. This paper demonstrates a compact implementation of three-input monotone logic gates based on the inverted T-shaped TFET. Firstly, based on the gate coupling mechanism in the novel inverted T channel, the BTBT current can be suppressed in the vertical or horizontal region to achieve the channel strobe. Therefore, the typical three-input monotone logic functions, Majority, OrAnd, and AndOr, are successfully implemented on a single transistor. Then, a simplified potential model describing gate coupling is established to describe the impact of key device parameters on the logic behavior. Combined with TCAD simulation, the design rules of devices with different logic functions are given. Finally, a series of three-input monotonic logic gates are designed and verified. The results show that the use of the proposed TFETs can effectively save the number of transistors in the three-input logic gate, which indicates that the three-input TFET is a compact and flexible candidate for three-input logic gates. Full article
(This article belongs to the Special Issue Emerging CMOS Devices, Volume II)
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11 pages, 2231 KiB  
Article
MOSFET Physics-Based Compact Model Mass-Produced: An Artificial Neural Network Approach
by Shijie Huang and Lingfei Wang
Micromachines 2023, 14(2), 386; https://doi.org/10.3390/mi14020386 - 4 Feb 2023
Cited by 8 | Viewed by 3287
Abstract
The continued scaling-down of nanoscale semiconductor devices has made it very challenging to obtain analytic surface potential solutions from complex equations in physics, which is the fundamental purpose of the MOSFET compact model. In this work, we proposed a general framework to automatically [...] Read more.
The continued scaling-down of nanoscale semiconductor devices has made it very challenging to obtain analytic surface potential solutions from complex equations in physics, which is the fundamental purpose of the MOSFET compact model. In this work, we proposed a general framework to automatically derive analytical solutions for surface potential in MOSFET, by leveraging the universal approximation power of deep neural networks. Our framework incorporated a physical-relation-neural-network (PRNN) to learn side-by-side from a general-purpose numerical simulator in handling complex equations of mathematical physics, and then instilled the “knowledge’’ from the simulation data into the neural network, so as to generate an accurate closed-form mapping between device parameters and surface potential. Inherently, the surface potential was able to reflect the numerical solution of a two-dimensional (2D) Poisson equation, surpassing the limits of traditional 1D Poisson equation solutions, thus better illustrating the physical characteristics of scaling devices. We obtained promising results in inferring the analytic surface potential of MOSFET, and in applying the derived potential function to the building of 130 nm MOSFET compact models and circuit simulation. Such an efficient framework with accurate prediction of device performances demonstrates its potential in device optimization and circuit design. Full article
(This article belongs to the Special Issue Emerging CMOS Devices, Volume II)
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