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Micromachines
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Emerging CMOS Devices
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Emerging CMOS Devices

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "D1: Semiconductor Devices".

Deadline for manuscript submissions: closed (31 August 2021) | Viewed by 23731

Special Issue Editors

Prof. Dr. Carlos Sampedro

E-Mail Website
Guest Editor
Department of Electronics and Computer Technology, University of Granada, 18071 Granada, Spain
Interests: advanced device simulation; Monte Carlo; CMOS co-integration; 2D materials
Special Issues, Collections and Topics in MDPI journals
Prof. Dr. Francisco Gamiz

E-Mail Website
Guest Editor
Laboratory of Nanoelectronics, Graphene and 2D materialsDepartment of Electronics and Computer Technology, University of Granada, 18071 Granada, Spain
Interests: advanced device simulation; device characterization; CMOS co-integration; 2D materials; biosensors
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

The next decade presents paramount challenges for the electronic community where different technologies will provide solutions in the emerging fields of big data, Internet of things, and artificial intelligence. In this scenario of electronic systems ubiquity, new CMOS device paradigms are being developed to fulfill future requirements and to be co-integrated with other emerging technologies including 2D materials. Great efforts are being made by industry and academia in the fields of fabrication, advanced simulation, characterization, and design to determine the emerging CMOS devices that will perform in future systems. Reconfigurable MOS, TFETs, 1TDRAM, MOS-based biosensors, and CMOS on non-conventional substrates and 2D materials will be key devices in future applications. In this Special Issue of Micromachines, researchers and developers are invited to submit manuscripts for the Special Issue “Emerging CMOS Devices”, where we will focus on advancements in the fabrication, simulation, and characterization of different electronic structures. This Special Issue welcomes articles and review articles that cover a broad range of possible topics, including but not limited to fabrication, simulation, and characterization of emerging CMOS devices, new channel materials for CMOS, 2D material-based CMOS applications, CMOS co-integration, nanometer-scale devices, alternative transistor architectures, or emerging memory devices. All submissions will be reviewed in accordance with the normal procedures of Micromachines.

We look forward to receiving your submissions!

Keywords:

Nanometer-scale devices: technology, characterization techniques, and evaluation metrics for high performance, low power, low standby power, high frequency, and memory applications.

Alternative transistor architectures including FDSOI, DGSOI, FinFET, MuGFET, vertical MOSFET, Nanowires, FeFET and Tunnel FET, MEMS/NEMS, Beyond-CMOS nanoelectronic devices.

New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain, nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.

Emerging memory devices.

CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling. Three-dimensional integration of devices and circuits, heterogeneous integration.

Transport phenomena, compact modeling, device simulation, and front- and back-end process simulation.

Advanced test structures and characterization techniques, parameter extraction, reliability, and variability assessment techniques for new materials and novel devices.

New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V, and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials.

Properties of ultra-thin films and buried oxides, defects, interface quality. Thin gate dielectrics: high-κ materials for switches and memory.

Prof. Dr. Carlos Sampedro
Prof. Dr. Francisco Gamiz
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

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Published Papers (7 papers)

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Research

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8 pages, 314 KiB  
Article
Analysis of the Reformulated Source to Drain Tunneling Probability for Improving the Accuracy of a Multisubband Ensemble Monte Carlo Simulator
by Jose Luis Padilla, Cristina Medina-Bailon, Antonio Palomares, Luca Donetti, Carlos Navarro, Carlos Sampedro and Francisco Gamiz
Micromachines 2022, 13(4), 533; https://doi.org/10.3390/mi13040533 - 28 Mar 2022
Viewed by 1415
Abstract
As an attempt to improve the description of the tunneling current that arises in ultrascaled nanoelectronic devices when charge carriers succeed in traversing the potential barrier between source and drain, an alternative and more accurate non-local formulation of the tunneling probability was suggested. [...] Read more.
As an attempt to improve the description of the tunneling current that arises in ultrascaled nanoelectronic devices when charge carriers succeed in traversing the potential barrier between source and drain, an alternative and more accurate non-local formulation of the tunneling probability was suggested. This improvement of the probability computation might result of particular interest in the context of Monte Carlo simulations where the utilization of the conventional Wentzel-Kramers-Brillouin (WKB) approximation tends to overestimate the number of particles experiencing this type of direct tunneling. However, in light of the reformulated expression for the tunneling probability, it becomes of paramount importance to assess the type of potentials for which it behaves adequately. We demonstrate that, for ensuring boundedness, the top of the potential barrier cannot feature a plateau, but rather has to behave quadratically as one approaches its maximum. Moreover, we show that monotonicity of the reformulated tunneling probability is not guaranteed by boundedness and requires an additional constraint regarding the derivative of the prefactor that modifies the traditional WKB tunneling probability. Full article
(This article belongs to the Special Issue Emerging CMOS Devices)
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11 pages, 3000 KiB  
Article
Research on Total Ionizing Dose Effect and Reinforcement of SOI-TFET
by Chen Chong, Hongxia Liu, Shulong Wang and Xiaocong Wu
Micromachines 2021, 12(10), 1232; https://doi.org/10.3390/mi12101232 - 10 Oct 2021
Cited by 5 | Viewed by 2203
Abstract
Since the oxide/source overlap structure can improve the tunneling probability and on-state current of tunneling field effect transistor (TFET) devices, and the silicon-on-insulator (SOI) structure has the effect of resisting the single event effect, SOI-TFET with the oxide/source overlap structure is a device [...] Read more.
Since the oxide/source overlap structure can improve the tunneling probability and on-state current of tunneling field effect transistor (TFET) devices, and the silicon-on-insulator (SOI) structure has the effect of resisting the single event effect, SOI-TFET with the oxide/source overlap structure is a device with development potential. The total ionizing dose (TID) effect on SOI-TFET was studied by discussing the switching ratio, band–band tunneling rate, threshold voltage, sub-threshold swing and bipolar effect of the device under different doses of irradiation. At the same time, simulations prove that selecting the proper thickness of the buried oxide (BOX) layer can effectively reduce the influence of the TID effect. This provides a way of direction and method for research on the irradiation effects on the device in the future. Full article
(This article belongs to the Special Issue Emerging CMOS Devices)
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21 pages, 10209 KiB  
Article
Simulation and Modeling of Novel Electronic Device Architectures with NESS (Nano-Electronic Simulation Software): A Modular Nano TCAD Simulation Framework
by Cristina Medina-Bailon, Tapas Dutta, Ali Rezaei, Daniel Nagy, Fikru Adamu-Lema, Vihar P. Georgiev and Asen Asenov
Micromachines 2021, 12(6), 680; https://doi.org/10.3390/mi12060680 - 10 Jun 2021
Cited by 12 | Viewed by 5152
Abstract
The modeling of nano-electronic devices is a cost-effective approach for optimizing the semiconductor device performance and for guiding the fabrication technology. In this paper, we present the capabilities of the new flexible multi-scale nano TCAD simulation software called Nano-Electronic Simulation Software (NESS). NESS [...] Read more.
The modeling of nano-electronic devices is a cost-effective approach for optimizing the semiconductor device performance and for guiding the fabrication technology. In this paper, we present the capabilities of the new flexible multi-scale nano TCAD simulation software called Nano-Electronic Simulation Software (NESS). NESS is designed to study the charge transport in contemporary and novel ultra-scaled semiconductor devices. In order to simulate the charge transport in such ultra-scaled devices with complex architectures and design, we have developed numerous simulation modules based on various simulation approaches. Currently, NESS contains a drift-diffusion, Kubo–Greenwood, and non-equilibrium Green’s function (NEGF) modules. All modules are numerical solvers which are implemented in the C++ programming language, and all of them are linked and solved self-consistently with the Poisson equation. Here, we have deployed some of those modules to showcase the capabilities of NESS to simulate advanced nano-scale semiconductor devices. The devices simulated in this paper are chosen to represent the current state-of-the-art and future technologies where quantum mechanical effects play an important role. Our examples include ultra-scaled nanowire transistors, tunnel transistors, resonant tunneling diodes, and negative capacitance transistors. Our results show that NESS is a robust, fast, and reliable simulation platform which can accurately predict and describe the underlying physics in novel ultra-scaled electronic devices. Full article
(This article belongs to the Special Issue Emerging CMOS Devices)
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13 pages, 3744 KiB  
Article
Hysteresis in As-Synthesized MoS2 Transistors: Origin and Sensing Perspectives
by Carlos Marquez, Norberto Salazar, Farzan Gity, Jose C. Galdon, Carlos Navarro, Carlos Sampedro, Paul K. Hurley, Edward Yi Chang and Francisco Gamiz
Micromachines 2021, 12(6), 646; https://doi.org/10.3390/mi12060646 - 31 May 2021
Cited by 4 | Viewed by 3495
Abstract
Two-dimensional materials, including molybdenum disulfide (MoS2), present promising sensing and detecting capabilities thanks to their extreme sensitivity to changes in the environment. Their reduced thickness also facilitates the electrostatic control of the channel and opens the door to flexible electronic applications. [...] Read more.
Two-dimensional materials, including molybdenum disulfide (MoS2), present promising sensing and detecting capabilities thanks to their extreme sensitivity to changes in the environment. Their reduced thickness also facilitates the electrostatic control of the channel and opens the door to flexible electronic applications. However, these materials still exhibit integration difficulties with complementary-MOS standardized processes and methods. The device reliability is compromised by gate insulator selection and the quality of the metal/semiconductor and semiconductor/insulator interfaces. Despite some improvements regarding mobility, hysteresis and Schottky barriers having been reported thanks to metal engineering, vertically stacked heterostructures with compatible thin-layers (such as hexagonal boron nitride or device encapsulation) variability is still an important constraint to sensor performance. In this work, we fabricated and extensively characterized the reliability of as-synthesized back-gated MoS2 transistors. Under atmospheric and room-temperature conditions, these devices present a wide electrical hysteresis (up to 5 volts) in their transfer characteristics. However, their performance is highly influenced by the temperature, light and pressure conditions. The singular signature in the time response of the devices points to adsorbates and contaminants inducing mobile charges and trapping/detrapping carrier phenomena as the mechanisms responsible for time-dependent current degradation. Far from being only a reliability issue, we demonstrated a method to exploit this device response to perform light, temperature and/or pressure sensors in as-synthesized devices. Two orders of magnitude drain current level differences were demonstrated by comparing device operation under light and dark conditions while a factor up to 105 is observed at vacuum versus atmospheric pressure environments. Full article
(This article belongs to the Special Issue Emerging CMOS Devices)
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12 pages, 7442 KiB  
Article
Self-Consistent Enhanced S/D Tunneling Implementation in a 2D MS-EMC Nanodevice Simulator
by Cristina Medina-Bailon, José Luis Padilla, Carlos Sampedro, Luca Donetti, Vihar P. Gergiev, Francisco Gamiz and Asen Asenov
Micromachines 2021, 12(6), 601; https://doi.org/10.3390/mi12060601 - 22 May 2021
Cited by 1 | Viewed by 2241
Abstract
The implementation of a source to drain tunneling in ultrascaled devices using MS-EMC has traditionally led to overestimated current levels in the subthreshold regime. In order to correct this issue and enhance the capabilities of this type of simulator, we discuss in this [...] Read more.
The implementation of a source to drain tunneling in ultrascaled devices using MS-EMC has traditionally led to overestimated current levels in the subthreshold regime. In order to correct this issue and enhance the capabilities of this type of simulator, we discuss in this paper two alternative and self-consistent solutions focusing on different parts of the simulation flow. The first solution reformulates the tunneling probability computation by modulating the WKB approximation in a suitable way. The second corresponds to a change in the current calculation technique based on the utilization of the Landauer formalism. The results from both solutions are compared and contrasted to NEGF results from NESS. We conclude that the current computation modification constitutes the most suitable and advisable strategy to improve the MS-EMC tool. Full article
(This article belongs to the Special Issue Emerging CMOS Devices)
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9 pages, 5444 KiB  
Article
Nanodevices Tend to Be Round
by Georges Pananakakis, Gérard Ghibaudo and Sorin Cristoloveanu
Micromachines 2021, 12(3), 330; https://doi.org/10.3390/mi12030330 - 20 Mar 2021
Cited by 1 | Viewed by 1973
Abstract
Under several circumstances, a nanowire transistor with a square cross-section behaves as a circular. Taking the Gate-All-Around junctionless transistor as a primary example, we investigate the transition of the conductive region from square to circle-like. In this case, the metamorphosis is accentuated by [...] Read more.
Under several circumstances, a nanowire transistor with a square cross-section behaves as a circular. Taking the Gate-All-Around junctionless transistor as a primary example, we investigate the transition of the conductive region from square to circle-like. In this case, the metamorphosis is accentuated by smaller size, lower doping, and higher gate voltage. After defining the geometrical criterion for square-to-circle shift, simulation results are used to document the main consequences. This transition occurs naturally in nanowires thinner than 50 nm. The results are rather universal, and supportive evidence is gathered from inversion-mode Gate-All-Around (GAA) MOSFETs as well as from thermal diffusion process. Full article
(This article belongs to the Special Issue Emerging CMOS Devices)
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Review

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22 pages, 4808 KiB  
Review
SRAM Cell Design Challenges in Modern Deep Sub-Micron Technologies: An Overview
by Waqas Gul, Maitham Shams and Dhamin Al-Khalili
Micromachines 2022, 13(8), 1332; https://doi.org/10.3390/mi13081332 - 17 Aug 2022
Cited by 17 | Viewed by 6142
Abstract
Microprocessors use static random-access memory (SRAM) cells in the cache memory design. As a part of the central computing component, their performance is critical. Modern system-on-chips (SoC) escalate performance pressure because only 10–15% of the transistors accounts for logic, while the remaining transistors [...] Read more.
Microprocessors use static random-access memory (SRAM) cells in the cache memory design. As a part of the central computing component, their performance is critical. Modern system-on-chips (SoC) escalate performance pressure because only 10–15% of the transistors accounts for logic, while the remaining transistors are for the cache memory. Moreover, modern implantable, portable and wearable electronic devices rely on artificial intelligence (AI), demanding an efficient and reliable SRAM design for compute-in-memory (CIM). For performance benchmark achievements, maintaining reliability is a major concern in recent technological nodes. Specifically, battery-operated applications utilize low-supply voltages, putting the SRAM cell’s stability at risk. In modern devices, the off-state current of a transistor is becoming comparable to the on-state current. On the other hand, process variations change the transistor design parameters and eventually compromise design integrity. Furthermore, sensitive information processing, environmental conditions and charge emission from IC packaging materials undermine the SRAM cell’s reliability. FinFET-SRAMs, with aggressive scaling, have taken operation to the limit, where a minute anomaly can cause failure. This article comprehensively reviews prominent challenges to the SRAM cell design after classifying them into five distinct categories. Each category explains underlying mathematical relations followed by viable solutions. Full article
(This article belongs to the Special Issue Emerging CMOS Devices)
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