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Micromachines
Special Issues
Emerging Memory Materials and Devices
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Emerging Memory Materials and Devices

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "A：Physics".

Deadline for manuscript submissions: closed (30 September 2024) | Viewed by 5508

Special Issue Editors

Dr. Qilin Hua

E-Mail Website
Guest Editor
School of Integrated Circuits and Electronics, Beijing Institute of Technology, Beijing 100081, China
Interests: flexible/stretchable electronics; nanoelectronics; neuromorphic computing
Dr. Tao Zeng

E-Mail Website
Guest Editor
Department of Materials Science and Engineering, National University of Singapore, Singapore 117575, Singapore
Interests: RRAM; FeRAM; synaptic emulation; neuromorphic computing

Special Issue Information

Dear Colleagues,

With the advent of the “post-Moore era”, rapid developments in the fields of the Internet of Things, big data, and artificial intelligence have challenged the traditional “von Neumann” computing architecture. Brain-inspired neuromorphic computing emulates the structure of the human brain, which is capable of parallel processing and distributed computing of complex information data while maintaining high efficiency and ultra-low power consumption. Emerging memory devices, including resistive random-access memory (RRAM), ferroelectric random access memory (FeRAM), and magnetoresistive random access memory (MRAM), are considered to be ideal hardware implementations of neuromorphic computing due to improved performance, lower power consumption, and higher data density. Over the past few decades, great efforts have been made in the development of emerging memory materials, devices, and circuits for synaptic emulation, logic operations, and neuromorphic computing. However, there are still extensive challenges to address before demonstrating the hardware implementation of neuromorphic computing. These challenges may include the operational reliability of memory devices, the biorealistic realization of synaptic functions, the algorithm and circuit of the artificial neural network, and so on. To overcome those obstacles, the study of material selection, physical mechanism, and circuit construction are still necessary. This Special Issue will cover topics that involve emerging memory materials, devices, and circuits in the context of synaptic emulation and neuromorphic computing.

Dr. Qilin Hua
Dr. Tao Zeng
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • emerging memory materials and devices: RRAM, FeRAM, MRAM
  • artificial synapse/neuron
  • artificial sensor system
  • artificial neural networks
  • in-memory computing
  • neuromorphic computing

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Published Papers (3 papers)

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Research

10 pages, 3480 KiB  
Article
Impact of Program–Erase Operation Intervals at Different Temperatures on 3D Charge-Trapping Triple-Level-Cell NAND Flash Memory Reliability
by Xuesong Zheng, Yifan Wu, Haitao Dong, Yizhi Liu, Pengpeng Sang, Liyi Xiao and Xuepeng Zhan
Micromachines 2024, 15(9), 1060; https://doi.org/10.3390/mi15091060 - 23 Aug 2024
Viewed by 945
Abstract
Three-dimensional charge-trapping (CT) NAND flash memory has attracted extensive attention owing to its unique merits, including huge storage capacities, large memory densities, and low bit cost. The reliability property is becoming an important factor for NAND flash memory with multi-level-cell (MLC) modes like [...] Read more.
Three-dimensional charge-trapping (CT) NAND flash memory has attracted extensive attention owing to its unique merits, including huge storage capacities, large memory densities, and low bit cost. The reliability property is becoming an important factor for NAND flash memory with multi-level-cell (MLC) modes like triple-level-cell (TLC) or quad-level-cell (QLC), which is seriously affected by the intervals between program (P) and erase (E) operations during P/E cycles. In this work, the impacts of the intervals between P&E cycling under different temperatures and P/E cycles were systematically characterized. The results are further analyzed in terms of program disturb (PD), read disturb (RD), and data retention (DR). It was found that fail bit counts (FBCs) during the high temperature (HT) PD process are much smaller than those of the room temperature (RT) PD process. Moreover, upshift error and downshift error dominate the HT PD and RT PD processes, respectively. To improve the memory reliability of 3D CT TLC NAND, different intervals between P&E operations should be adopted considering the operating temperatures. These results could provide potential insights to optimize the lifetime of NAND flash-based memory systems. Full article
(This article belongs to the Special Issue Emerging Memory Materials and Devices)
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13 pages, 20047 KiB  
Article
Bi-Directional and Operand-Controllable In-Memory Computing for Boolean Logic and Search Operations with Row and Column Directional SRAM (RC-SRAM)
by Han Xiao, Ruiyong Zhao, Yulan Liu, Yuanzhen Liu and Jing Chen
Micromachines 2024, 15(8), 1056; https://doi.org/10.3390/mi15081056 - 22 Aug 2024
Viewed by 728
Abstract
The von Neumann architecture is no longer sufficient for handling large-scale data. In-memory computing has emerged as the potent method for breaking through the memory bottleneck. A new 10T SRAM bitcell with row and column control lines called RC-SRAM is proposed in this [...] Read more.
The von Neumann architecture is no longer sufficient for handling large-scale data. In-memory computing has emerged as the potent method for breaking through the memory bottleneck. A new 10T SRAM bitcell with row and column control lines called RC-SRAM is proposed in this article. The architecture based on RC-SRAM can achieve bi-directional and operand-controllable logic-in-memory and search operations through different signal configurations, which can comprehensively respond to various occasions and needs. Moreover, we propose threshold-controlled logic gates for sensing, which effectively reduces the circuit area and improves accuracy. We validate the RC-SRAM with a 28 nm CMOS technology, and the results show that the circuits are not only full featured and flexible for customization but also have a significant increase in the working frequency. At VDD = 0.9 V and T = 25 °C, the bi-directional search frequency is up to 775 MHz and 567 MHz, and the speeds for row and column Boolean logic reach 759 MHz and 683 MHz. Full article
(This article belongs to the Special Issue Emerging Memory Materials and Devices)
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16 pages, 6061 KiB  
Article
DAM SRAM CORE: An Efficient High-Speed and Low-Power CIM SRAM CORE Design for Feature Extraction Convolutional Layers in Binary Neural Networks
by Ruiyong Zhao, Zhenghui Gong, Yulan Liu and Jing Chen
Micromachines 2024, 15(5), 617; https://doi.org/10.3390/mi15050617 - 30 Apr 2024
Viewed by 3286
Abstract
This article proposes a novel design for an in-memory computing SRAM, the DAM SRAM CORE, which integrates storage and computational functionality within a unified 11T SRAM cell and enables the performance of large-scale parallel Multiply–Accumulate (MAC) operations within the SRAM array. This design [...] Read more.
This article proposes a novel design for an in-memory computing SRAM, the DAM SRAM CORE, which integrates storage and computational functionality within a unified 11T SRAM cell and enables the performance of large-scale parallel Multiply–Accumulate (MAC) operations within the SRAM array. This design not only improves the area efficiency of the individual cells but also realizes a compact layout. A key highlight of this design is its employment of a dynamic aXNOR-based computation mode, which significantly reduces the consumption of both dynamic and static power during the computational process within the array. Additionally, the design innovatively incorporates a self-stabilizing voltage gradient quantization circuit, which enhances the computational accuracy of the overall system. The 64 × 64 bit DAM SRAM CORE in-memory computing core was fabricated using the 55 nm CMOS logic process and validated via simulations. The experimental results show that this core can deliver 5-bit output results with 1-bit input feature data and 1-bit weight data, while maintaining a static power consumption of 0.48 mW/mm2 and a computational power consumption of 11.367 mW/mm2. This showcases its excellent low-power characteristics. Furthermore, the core achieves a data throughput of 109.75 GOPS and exhibits an impressive energy efficiency of 21.95 TOPS/W, which robustly validate the effectiveness and advanced nature of the proposed in-memory computing core design. Full article
(This article belongs to the Special Issue Emerging Memory Materials and Devices)
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