Micromachines

Editorial

Jump to: Research, Review

4 pages, 179 KiB

Open AccessEditorial

Editorial for the Special Issue “MEMS Packaging Technologies and 3D Integration”

by Seonho Seok

Micromachines 2022, 13(5), 749; https://doi.org/10.3390/mi13050749 - 9 May 2022

Cited by 2 | Viewed by 2349

Abstract

As fabrication technologies advance, the packaging of MEMS device is being developed in two main directions: MEMS device packaging and MEMS or sensor system integration [...] Full article

(This article belongs to the Special Issue MEMS Packaging Technologies and 3D Integration)

Research

Jump to: Editorial, Review

15 pages, 7035 KiB

Open AccessArticle

A Study on Biocompatible Polymer-Based Packaging of Neural Interface for Chronic Implantation

by HyungDal Park, Wonsuk Choi, Seonghwan Oh, Yong-Jun Kim, Seonho Seok and Jinseok Kim

Micromachines 2022, 13(4), 516; https://doi.org/10.3390/mi13040516 - 26 Mar 2022

Cited by 9 | Viewed by 2755

Abstract

This paper proposed and verified the use of polymer-based packaging to implement the chronic implantation of neural interfaces using a combination of a commercial thermal epoxy and a thin parylene film. The packaging’s characteristics and the performance of the vulnerable interface between the [...] Read more.

This paper proposed and verified the use of polymer-based packaging to implement the chronic implantation of neural interfaces using a combination of a commercial thermal epoxy and a thin parylene film. The packaging’s characteristics and the performance of the vulnerable interface between the thermal epoxy layer and polyimide layer, which is mainly used for neural electrodes and an FPCB, were evaluated through in vitro, in vivo, and acceleration experiments. The performance of neural interfaces—composed of the combination of the thermal epoxy and thin parylene film deposition as encapsulation packaging—was evaluated by using signal acquisition experiments based on artificial stimulation signal transmissions through in vitro and in vivo experiments. It has been found that, when commercial thermal epoxy normally cured at room temperature was cured at higher temperatures of 45 °C and 65 °C, not only is its lifetime increased with about twice the room-temperature-based curing conditions but also an interfacial adhesion is higher with more than twice the room-temperature-based curing conditions. In addition, through in vivo experiments using rats, it was confirmed that bodily fluids did not flow into the interface between the thermal epoxy and FPCB for up to 18 months, and it was verified that the rats maintained healthy conditions without occurring an immune response in the body to the thin parylene film deposition on the packaging’s surface. Full article

(This article belongs to the Special Issue MEMS Packaging Technologies and 3D Integration)

► Show Figures

Figure 1

14 pages, 31706 KiB

Open AccessArticle

Characteristics of Cracking Failure in Microbump Joints for 3D Chip-on-Chip Interconnections under Drop Impact

by Zhen Liu, Mingang Fang, Lei Shi, Yu Gu, Zhuo Chen and Whenhui Zhu

Micromachines 2022, 13(2), 281; https://doi.org/10.3390/mi13020281 - 10 Feb 2022

Cited by 9 | Viewed by 2115

Abstract

With the rapid development of microelectronics packaging and integration, the failure risk of micro-solder joints in packaging structure caused by impact load has been increasingly concerning. However, the failure mechanism and reliability performance of a Cu-pillar-based microbump joint can use little of the [...] Read more.

With the rapid development of microelectronics packaging and integration, the failure risk of micro-solder joints in packaging structure caused by impact load has been increasingly concerning. However, the failure mechanism and reliability performance of a Cu-pillar-based microbump joint can use little of the existing research on board-level solder joints as reference, due to the downscaling and joint structure evolution. In this study, to investigate the cracking behavior of microbump joints targeted at chip-on-chip (CoC) stacked interconnections, the CoC test samples were subjected to repeated drop tests to reveal the crack morphology. It was found that the crack causing the microbump failure first initiated at the interface between the intermetallic compound (IMC) layer and the solder, propagated along the interface for a certain length, and then deflected into the solder matrix. To further explore the crack propagation mechanism, stress intensity factor (SIF) of the crack tip at the interface between IMC and solder was calculated by contour integral method, and the effects of solder thickness and crack length were also quantitatively analyzed and combined with the crack deflection criterion. By combining the SIF with the fracture toughness of the solder–Ni interface and the solder matrix, a criterion for crack deflecting from the original propagating path was established, which can be used for prediction of critical crack length and deflection angle for the initiation of crack deflection. Finally, the relationship between solder thickness and critical deflection length and deflection angle of main crack was verified by a board level drop test, and the influence of grain structure in solder matrix on actual failure lifetime was briefly discussed. Full article

(This article belongs to the Special Issue MEMS Packaging Technologies and 3D Integration)

► Show Figures

Figure 1

28 pages, 19580 KiB

Open AccessArticle

Investigation of Integrated Reactive Multilayer Systems for Bonding in Microsystem Technology

by El-Mostafa Bourim, Il-Suk Kang and Hee Yeoun Kim

Micromachines 2021, 12(10), 1272; https://doi.org/10.3390/mi12101272 - 19 Oct 2021

Cited by 12 | Viewed by 3821

Abstract

For the integration of a reactive multilayer system (iRMS) with a high exothermic reaction enthalpy as a heat source on silicon wafers for low-temperature bonding in the 3D integration and packaging of microsystems, two main conflicting issues should be overcome: heat accumulation arising [...] Read more.

For the integration of a reactive multilayer system (iRMS) with a high exothermic reaction enthalpy as a heat source on silicon wafers for low-temperature bonding in the 3D integration and packaging of microsystems, two main conflicting issues should be overcome: heat accumulation arising from the layer interface pre-intermixing, which causes spontaneous self-ignition during the deposition of the system layers, and conductive heat loss through the substrate, which leads to reaction propagation quenching. In this work, using electron beam evaporation, we investigated the growth of a high exothermic metallic Pd/Al reactive multilayer system (RMS) on different Si-wafer substrates with different thermal conduction, specifically a bare Si-wafer, a RuO_x or PdO_x layer buffering Si-wafer, and a SiO₂-coated Si-wafer. With the exception of the bare silicon wafer, the RMS grown on all other coated wafers underwent systematic spontaneous self-ignition surging during the deposition process once it reached a thickness of around 1 μm. This issue was surmounted by investigating a solution based on tuning the output energy by stacking alternating sections of metallic reactive multilayer Pd/Al and Ni/Al systems that have a high and medium enthalpy of exothermic reactions, respectively. This heterostructure with a bilayer thickness of 100 nm was successfully grown on a SiO₂-coated Si-wafer to a total thickness of 3 μm without any spontaneous upsurge of self-ignition; it could be electrically ignited at room temperature, enabling a self-sustained propagating exothermic reaction along the reactive patterned track without undergoing quenching. The results of this study will promote the growth of reactive multilayer systems by electron beam evaporation processing and their potential integration as local heat sources on Si-wafer substrates for bonding applications in microelectronics and microsystems technology. Full article

(This article belongs to the Special Issue MEMS Packaging Technologies and 3D Integration)

► Show Figures

Figure 1

13 pages, 7768 KiB

Open AccessArticle

Geometrical Effects on Ultrasonic Al Bump Direct Bonding for Microsystem Integration: Simulation and Experiments

by Jun-Hao Lee, Pin-Kuan Li, Hai-Wen Hung, Wallace Chuang, Eckart Schellkes, Kiyokazu Yasuda and Jenn-Ming Song

Micromachines 2021, 12(7), 750; https://doi.org/10.3390/mi12070750 - 26 Jun 2021

Cited by 4 | Viewed by 2096

Abstract

This study employed finite element analysis to simulate ultrasonic metal bump direct bonding. The stress distribution on bonding interfaces in metal bump arrays made of Al, Cu, and Ni/Pd/Au was simulated by adjusting geometrical parameters of the bumps, including the shape, size, and [...] Read more.

This study employed finite element analysis to simulate ultrasonic metal bump direct bonding. The stress distribution on bonding interfaces in metal bump arrays made of Al, Cu, and Ni/Pd/Au was simulated by adjusting geometrical parameters of the bumps, including the shape, size, and height; the bonding was performed with ultrasonic vibration with a frequency of 35 kHz under a force of 200 N, temperature of 200 °C, and duration of 5 s. The simulation results revealed that the maximum stress of square bumps was greater than that of round bumps. The maximum stress of little square bumps was at least 15% greater than those of little round bumps and big round bumps. An experimental demonstration was performed in which bumps were created on Si chips through Al sputtering and lithography processes. Subtractive lithography etching was the only effective process for the bonding of bumps, and Ar plasma treatment magnified the joint strength. The actual joint shear strength was positively proportional to the simulated maximum stress. Specifically, the shear strength reached 44.6 MPa in the case of ultrasonic bonding for the little Al square bumps. Full article

(This article belongs to the Special Issue MEMS Packaging Technologies and 3D Integration)

► Show Figures

Figure 1

14 pages, 11945 KiB

Open AccessArticle

Study of the Absorption of Electromagnetic Radiation by 3D, Vacuum-Packaged, Nano-Machined CMOS Transistors for Uncooled IR Sensing

by Gil Cherniak, Moshe Avraham, Sharon Bar-Lev, Gady Golan and Yael Nemirovsky

Micromachines 2021, 12(5), 563; https://doi.org/10.3390/mi12050563 - 16 May 2021

Cited by 5 | Viewed by 2842

Abstract

There is an ongoing effort to fabricate miniature, low-cost, and sensitive thermal sensors for domestic and industrial uses. This paper presents a miniature thermal sensor (dubbed TMOS) that is fabricated in advanced CMOS FABs, where the micromachined CMOS-SOI transistor, implemented with a 130-nm [...] Read more.

There is an ongoing effort to fabricate miniature, low-cost, and sensitive thermal sensors for domestic and industrial uses. This paper presents a miniature thermal sensor (dubbed TMOS) that is fabricated in advanced CMOS FABs, where the micromachined CMOS-SOI transistor, implemented with a 130-nm technology node, acts as a sensing element. This study puts emphasis on the study of electromagnetic absorption via the vacuum-packaged TMOS and how to optimize it. The regular CMOS transistor is transformed to a high-performance sensor by the micro- or nano-machining process that releases it from the silicon substrate by wafer-level processing and vacuum packaging. Since the TMOS is processed in a CMOS-SOI FAB and is comprised of multiple thin layers that follow strict FAB design rules, the absorbed electromagnetic radiation cannot be modeled accurately and a simulation tool is required. This paper presents modeling and simulations based on the LUMERICAL software package of the vacuum-packaged TMOS. A very high absorption coefficient may be achieved by understanding the physics, as well as the role of each layer. Full article

(This article belongs to the Special Issue MEMS Packaging Technologies and 3D Integration)

► Show Figures

Figure 1

14 pages, 10538 KiB

Open AccessArticle

Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

by Pao-Hsiung Wang, Yu-Wei Huang and Kuo-Ning Chiang

Micromachines 2021, 12(3), 295; https://doi.org/10.3390/mi12030295 - 10 Mar 2021

Cited by 13 | Viewed by 3745

Abstract

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material [...] Read more.

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP. Full article

(This article belongs to the Special Issue MEMS Packaging Technologies and 3D Integration)

► Show Figures

Figure 1

13 pages, 1293 KiB

Open AccessArticle

A Hybrid Fuzzy Decision Model for Evaluating MEMS and IC Integration Technologies

by Qian-Yo Lee, Ming-Xuan Lee and Yen-Chun Lee

Micromachines 2021, 12(3), 276; https://doi.org/10.3390/mi12030276 - 7 Mar 2021

Cited by 4 | Viewed by 2065

Abstract

Integrated devices incorporating MEMS (microelectromechanical systems) with IC (integrated circuit) components have been becoming increasingly important in the era of IoT (Internet of Things). In this study, a hybrid fuzzy MCDM (multi-criteria decision making) model was proposed to effectively evaluate alternative technologies that [...] Read more.

Integrated devices incorporating MEMS (microelectromechanical systems) with IC (integrated circuit) components have been becoming increasingly important in the era of IoT (Internet of Things). In this study, a hybrid fuzzy MCDM (multi-criteria decision making) model was proposed to effectively evaluate alternative technologies that incorporate MEMS with IC components. This model, composed of the fuzzy AHP (analytic hierarchy process) and fuzzy VIKOR (VIseKriterijumska Optimizacija I Kompromisno Resenje) methods, solves the decision problem of how best to rank MEMS and IC integration technologies in a fuzzy environment. The six important criteria and the major five alternative technologies associated with our research themes were explored through literature review and expert investigations. The priority weights of criteria were derived using fuzzy AHP. After that, fuzzy VIKOR was deployed to rank alternatives. The empirical results show that development schedule and manufacturing capability are the two most important criteria and 3D (three-dimensional) SiP (system-in-package) and monolithic SoC (system-on-chip) are the top two favored technologies. The proposed fuzzy decision model could serve as a reference for the future strategic evaluation and selection of MEMS and IC integration technologies. Full article

(This article belongs to the Special Issue MEMS Packaging Technologies and 3D Integration)

► Show Figures

Figure 1

15 pages, 5260 KiB

Open AccessArticle

A RF Redundant TSV Interconnection for High Resistance Si Interposer

by Mengcheng Wang, Shenglin Ma, Yufeng Jin, Wei Wang, Jing Chen, Liulin Hu and Shuwei He

Micromachines 2021, 12(2), 169; https://doi.org/10.3390/mi12020169 - 8 Feb 2021

Cited by 13 | Viewed by 4097

Abstract

Through Silicon Via (TSV) technology is capable meeting effective, compact, high density, high integration, and high-performance requirements. In high-frequency applications, with the rapid development of 5G and millimeter-wave radar, the TSV interposer will become a competitive choice for radio frequency system-in-package (RF SIP) [...] Read more.

Through Silicon Via (TSV) technology is capable meeting effective, compact, high density, high integration, and high-performance requirements. In high-frequency applications, with the rapid development of 5G and millimeter-wave radar, the TSV interposer will become a competitive choice for radio frequency system-in-package (RF SIP) substrates. This paper presents a redundant TSV interconnect design for high resistivity Si interposers for millimeter-wave applications. To verify its feasibility, a set of test structures capable of working at millimeter waves are designed, which are composed of three pieces of CPW (coplanar waveguide) lines connected by single TSV, dual redundant TSV, and quad redundant TSV interconnects. First, HFSS software is used for modeling and simulation, then, a modified equivalent circuit model is established to analysis the effect of the redundant TSVs on the high-frequency transmission performance to solidify the HFSS based simulation. At the same time, a failure simulation was carried out and results prove that redundant TSV can still work normally at 44 GHz frequency when failure occurs. Using the developed TSV process, the sample is then fabricated and tested. Using L-2L de-embedding method to extract S-parameters of the TSV interconnection. The insertion loss of dual and quad redundant TSVs are 0.19 dB and 0.46 dB at 40 GHz, respectively. Full article

(This article belongs to the Special Issue MEMS Packaging Technologies and 3D Integration)

► Show Figures

Figure 1

10 pages, 5691 KiB

Open AccessArticle

Analysis of Frequency Drift of Silicon MEMS Resonator with Temperature

by Bo Jiang, Shenhu Huang, Jing Zhang and Yan Su

Micromachines 2021, 12(1), 26; https://doi.org/10.3390/mi12010026 - 29 Dec 2020

Cited by 20 | Viewed by 3984

Abstract

High-quality-factor Micro-Electro-Mechanical System (MEMS) resonators have been widely used in sensors and actuators to obtain great mechanical sensitivity. The frequency drift of resonator with temperature is a problem encountered practically. The paper focuses on the resonator frequency distribution law in the temperature range [...] Read more.

High-quality-factor Micro-Electro-Mechanical System (MEMS) resonators have been widely used in sensors and actuators to obtain great mechanical sensitivity. The frequency drift of resonator with temperature is a problem encountered practically. The paper focuses on the resonator frequency distribution law in the temperature range of—40 to 60 °C. The four-layer models were established to analyze thermal stress caused by temperature due to the mismatch of thermal expansion coefficients. The temperature variation leads to the transformation of stress, which leads to the shift of resonance frequency. The paper analyzes the influence of hard and soft adhesive package on the temperature coefficient of frequency. The resonant accelerometer was employed for the frequency measurements in the paper. In experiments, three types of adhesive dispensing patterns were implemented. The results are consistent with the simulation well. The optimal packaging method achieves −24.1 ppm/°C to −30.2 ppm/°C temperature coefficient of the resonator in the whole temperature range, close to the intrinsic property of silicon (−31 ppm). Full article

(This article belongs to the Special Issue MEMS Packaging Technologies and 3D Integration)

► Show Figures

Figure 1

12 pages, 5287 KiB

Open AccessArticle

Characterization and Analysis of Metal Adhesion to Parylene Polymer Substrate Using Scotch Tape Test for Peripheral Neural Probe

by Seonho Seok, HyungDal Park and Jinseok Kim

Micromachines 2020, 11(6), 605; https://doi.org/10.3390/mi11060605 - 22 Jun 2020

Cited by 12 | Viewed by 4242

Abstract

This paper presents measurement and FEM (Finite Element Method) analysis of metal adhesion force to a parylene substrate for implantable neural probe. A test device composed of 300 nm-thick gold and 30 nm-thick titanium metal electrodes on top of parylene substrate was prepared. [...] Read more.

This paper presents measurement and FEM (Finite Element Method) analysis of metal adhesion force to a parylene substrate for implantable neural probe. A test device composed of 300 nm-thick gold and 30 nm-thick titanium metal electrodes on top of parylene substrate was prepared. The metal electrodes suffer from delamination during wet metal patterning process; thus, CF₄ plasma treatment was applied to the parylene substrate before metal deposition. The two thin film metal layers were deposited by e-beam evaporation process. Metal electrodes had 200 μm in width, 300 μm spacing between the metal lines, and 5 mm length as the neural probe. Adhesion force of the metal lines to parylene substrate was measured with scotch tape test. Angle between the scotch tape and the test device substrate changed from 60° to 90° during characterization. Force exerted the scotch tape was recorded as the function of displacement of the scotch tape. It was found that a peak was created in measured force-displacement curve due to metal delamination. Metal adhesion was estimated 1.3 J/m² by referring to the force peak and metal width at the force-displacement curve. Besides, the scotch tape test was simulated to comprehend delamination behavior of the test through FEM modeling. Full article

(This article belongs to the Special Issue MEMS Packaging Technologies and 3D Integration)

► Show Figures

Figure 1

13 pages, 4411 KiB

Open AccessArticle

On the Feasibility of Fan-Out Wafer-Level Packaging of Capacitive Micromachined Ultrasound Transducers (CMUT) by Using Inkjet-Printed Redistribution Layers

by Ali Roshanghias, Marc Dreissigacker, Christina Scherf, Christian Bretthauer, Lukas Rauter, Johanna Zikulnig, Tanja Braun, Karl-F. Becker, Sven Rzepka and Martin Schneider-Ramelow

Micromachines 2020, 11(6), 564; https://doi.org/10.3390/mi11060564 - 31 May 2020

Cited by 15 | Viewed by 4463

Abstract

Fan-out wafer-level packaging (FOWLP) is an interesting platform for Microelectromechanical systems (MEMS) sensor packaging. Employing FOWLP for MEMS sensor packaging has some unique challenges, while some originate merely from the fabrication of redistribution layers (RDL). For instance, it is crucial to protect the [...] Read more.

Fan-out wafer-level packaging (FOWLP) is an interesting platform for Microelectromechanical systems (MEMS) sensor packaging. Employing FOWLP for MEMS sensor packaging has some unique challenges, while some originate merely from the fabrication of redistribution layers (RDL). For instance, it is crucial to protect the delicate structures and fragile membranes during RDL formation. Thus, additive manufacturing (AM) for RDL formation seems to be an auspicious approach, as those challenges are conquered by principle. In this study, by exploiting the benefits of AM, RDLs for fan-out packaging of capacitive micromachined ultrasound transducers (CMUT) were realized via drop-on-demand inkjet printing technology. The long-term reliability of the printed tracks was assessed via temperature cycling tests. The effects of multilayering and implementation of an insulating ramp on the reliability of the conductive tracks were identified. Packaging-induced stresses on CMUT dies were further investigated via laser-Doppler vibrometry (LDV) measurements and the corresponding resonance frequency shift. Conclusively, the bottlenecks of the inkjet-printed RDLs for FOWLP were discussed in detail. Full article

(This article belongs to the Special Issue MEMS Packaging Technologies and 3D Integration)

► Show Figures

Figure 1

14 pages, 22549 KiB

Open AccessArticle

Effect of Au Film Thickness and Surface Roughness on Room-Temperature Wafer Bonding and Wafer-Scale Vacuum Sealing by Au-Au Surface Activated Bonding

by Michitaka Yamamoto, Takashi Matsumae, Yuichi Kurashima, Hideki Takagi, Tadatomo Suga, Seiichi Takamatsu, Toshihiro Itoh and Eiji Higurashi

Micromachines 2020, 11(5), 454; https://doi.org/10.3390/mi11050454 - 27 Apr 2020

Cited by 31 | Viewed by 5897

Abstract

Au-Au surface activated bonding (SAB) using ultrathin Au films is effective for room-temperature pressureless wafer bonding. This paper reports the effect of the film thickness (15–500 nm) and surface roughness (0.3–1.6 nm) on room-temperature pressureless wafer bonding and sealing. The root-mean-square surface roughness [...] Read more.

Au-Au surface activated bonding (SAB) using ultrathin Au films is effective for room-temperature pressureless wafer bonding. This paper reports the effect of the film thickness (15–500 nm) and surface roughness (0.3–1.6 nm) on room-temperature pressureless wafer bonding and sealing. The root-mean-square surface roughness and grain size of sputtered Au thin films on Si and glass wafers increased with the film thickness. The bonded area was more than 85% of the total wafer area when the film thickness was 100 nm or less and decreased as the thickness increased. Room-temperature wafer-scale vacuum sealing was achieved when Au thin films with a thickness of 50 nm or less were used. These results suggest that Au-Au SAB using ultrathin Au films is useful in achieving room-temperature wafer-level hermetic and vacuum packaging of microelectromechanical systems and optoelectronic devices. Full article

(This article belongs to the Special Issue MEMS Packaging Technologies and 3D Integration)

► Show Figures

Figure 1

Review

Jump to: Editorial, Research

15 pages, 5504 KiB

Open AccessReview

Polymer-Based Biocompatible Packaging for Implantable Devices: Packaging Method, Materials, and Reliability Simulation

by Seonho Seok

Micromachines 2021, 12(9), 1020; https://doi.org/10.3390/mi12091020 - 27 Aug 2021

Cited by 19 | Viewed by 4715

Abstract

Polymer materials attract more and more interests for a biocompatible package of novel implantable medical devices. Medical implants need to be packaged in a biocompatible way to minimize FBR (Foreign Body Reaction) of the implant. One of the most advanced implantable devices is [...] Read more.

Polymer materials attract more and more interests for a biocompatible package of novel implantable medical devices. Medical implants need to be packaged in a biocompatible way to minimize FBR (Foreign Body Reaction) of the implant. One of the most advanced implantable devices is neural prosthesis device, which consists of polymeric neural electrode and silicon neural signal processing integrated circuit (IC). The overall neural interface system should be packaged in a biocompatible way to be implanted in a patient. The biocompatible packaging is being mainly achieved in two approaches; (1) polymer encapsulation of conventional package based on die attach, wire bond, solder bump, etc. (2) chip-level integrated interconnect, which integrates Si chip with metal thin film deposition through sacrificial release technique. The polymer encapsulation must cover different materials, creating a multitude of interface, which is of much importance in long-term reliability of the implanted biocompatible package. Another failure mode is bio-fluid penetration through the polymer encapsulation layer. To prevent bio-fluid leakage, a diffusion barrier is frequently added to the polymer packaging layer. Such a diffusion barrier is also used in polymer-based neural electrodes. This review paper presents the summary of biocompatible packaging techniques, packaging materials focusing on encapsulation polymer materials and diffusion barrier, and a FEM-based modeling and simulation to study the biocompatible package reliability. Full article

(This article belongs to the Special Issue MEMS Packaging Technologies and 3D Integration)

► Show Figures

Figure 1

Journal Menu

Journal Browser

MEMS Packaging Technologies and 3D Integration

Share This Special Issue

Special Issue Editor

Special Issue Information

Keywords

Benefits of Publishing in a Special Issue

Related Special Issues

Published Papers (14 papers)

Editorial

Research

Review

Further Information

Guidelines

MDPI Initiatives

Follow MDPI