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Sensors and Analog Front-End Circuits for IoT Systems and High Sensitivity Measurements

A special issue of Sensors (ISSN 1424-8220). This special issue belongs to the section "Electronic Sensors".

Deadline for manuscript submissions: closed (30 June 2024) | Viewed by 27829

Special Issue Editors


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Guest Editor
Division of Electronics and Informatics, Graduate School of Science and Technology, Gunma University, Kiryu 376-8515, Japan
Interests: circuit design; IC testing; signal processing
Special Issues, Collections and Topics in MDPI journals
Industrial Property Cooperation Center, Fukagawa Gatharia W3 Building, 1-2-15 Kiba, Koto-ku, Tokyo, Japan
Interests: position sensors; magnetic sensors; IoT
Special Issues, Collections and Topics in MDPI journals

E-Mail Website
Guest Editor
Division of Electronics and Informatics, Faculty of Science and Technology, Gunma University, Kiryu Gunma 376-8515, Japan
Interests: CFD (Computer Fluid Dynamics)

Special Issue Information

Dear Colleagues,

IoT systems use many sensors and their analog front-end circuits are very important; they should be low-cost, low-power and be of small size . On the other hand, high-sensitivity measurement sensors for weak signals are performance-oriented. This Special Issue deals with sensors and analog front-end circuits for IoT systems and high-sensitivity measurements, including the design, calibration and testing technologies as well as the novel concepts. New sensors and new architectures of analog front-end circuits for IoT systems and high-sensitivity measurements are covered in this Special Issue. The related technologies to achieve a high performance, low cost, miniature size, one-chip integration, board integration, high reliability, calibration for high accuracy, and testing for mass production as well as the following digital signal processing algorithms and systems are also covered. We are looking for original contributions to these areas.

Prof. Dr. Haruo Kobayashi
Toshio Iino
Dr. Anna Kuwana
Guest Editors

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Keywords

  • Sensors for IoT systems
  • High-sensitivity measurement
  • Sensors for the aboves (image sensors, photo sensors, magnetic sensors, acceleration sensors, gyro sensors, temperature sensors, position sensors, strain sensors, pressure sensors, sounds sensors, flow sensors, gas sensors, soil sensors, biomagnetism sensors, and so on)
  • Integrated sensors
  • MEMS sensors
  • Analog filter
  • Op amp
  • Delta-sigma ADC
  • Incremental ADC
  • SAR ADC
  • Analog signal conditioning
  • Calibration
  • Testing

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Related Special Issue

Published Papers (10 papers)

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Research

13 pages, 10028 KiB  
Communication
A 9-10-Bit Adjustable and Energy-Efficient Switching Scheme for Successive Approximation Register Analog-to-Digital Converter with One Least Significant Bit Common-Mode Voltage Variation
by Yunfeng Hu, Chaoyi Chen, Lexing Hu, Qingming Huang, Bin Tang, Mengsi Hu, Bingbing Yuan, Zhaohui Wu and Bin Li
Sensors 2024, 24(11), 3273; https://doi.org/10.3390/s24113273 - 21 May 2024
Cited by 1 | Viewed by 912
Abstract
A 9-10-bit adjustable and energy-efficient switching scheme for SAR ADC with one-LSB common-mode voltage variation is proposed. Based on capacitor-splitting technology and common-mode conversion techniques, the proposed switching scheme reduces the DAC switching energy by 96.41% compared to the conventional scheme. The low [...] Read more.
A 9-10-bit adjustable and energy-efficient switching scheme for SAR ADC with one-LSB common-mode voltage variation is proposed. Based on capacitor-splitting technology and common-mode conversion techniques, the proposed switching scheme reduces the DAC switching energy by 96.41% compared to the conventional scheme. The low complexity and the one-LSB common-mode voltage offset of this scheme benefit from the simultaneous switching of the reference voltages of the capacitors corresponding to the positive array and the negative array throughout the entire reference voltage switching process, and the reference voltage of each capacitor in the scheme does not change more than two voltages. The post-layout result shows that the ADC achieves the 54.96 dB SNDR, the 61.73 dB SFDR, and the 0.67 μw power consumption with the 10-bit mode and the 48.33 dB SNDR, the 54.17 dB SFDR, and the 0.47 μw power consumption with the 9-bit mode in a 180 nm process with a 100 kS/s sampling frequency. Full article
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14 pages, 3092 KiB  
Article
A Novel Method for Remaining Useful Life Prediction of RF Circuits Based on the Gated Recurrent Unit–Convolutional Neural Network Model
by Wanyu Yang, Kunping Wu, Bing Long and Shulin Tian
Sensors 2024, 24(9), 2841; https://doi.org/10.3390/s24092841 - 29 Apr 2024
Viewed by 831
Abstract
The remaining useful life (RUL) prediction of RF circuits is an important tool for circuit reliability. Data-driven-based approaches do not require knowledge of the failure mechanism and reduce the dependence on knowledge of complex circuits, and thus can effectively realize RUL prediction. This [...] Read more.
The remaining useful life (RUL) prediction of RF circuits is an important tool for circuit reliability. Data-driven-based approaches do not require knowledge of the failure mechanism and reduce the dependence on knowledge of complex circuits, and thus can effectively realize RUL prediction. This manuscript proposes a novel RUL prediction method based on a gated recurrent unit–convolutional neural network (GRU-CNN). Firstly, the data are normalized to improve the efficiency of the algorithm; secondly, the degradation of the circuit is evaluated using the hybrid health score based on the Euclidean and Manhattan distances; then, the life cycle of the RF circuits is segmented based on the hybrid health scores; and finally, an RUL prediction is carried out for the circuits at each stage using the GRU-CNN model. The results show that the RMSE of the GRU-CNN model in the normal operation stage is only 3/5 of that of the GRU and CNN models, while the prediction uncertainty is minimized. Full article
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18 pages, 5986 KiB  
Article
A Time-of-Flight Image Sensor Using 8-Tap P-N Junction Demodulator Pixels
by Ryosuke Miyazawa, Yuya Shirakawa, Kamel Mars, Keita Yasutomi, Keiichiro Kagawa, Satoshi Aoyama and Shoji Kawahito
Sensors 2023, 23(8), 3987; https://doi.org/10.3390/s23083987 - 14 Apr 2023
Cited by 2 | Viewed by 3379
Abstract
This paper presents a time-of-flight image sensor based on 8-Tap P-N junction demodulator (PND) pixels, which is designed for hybrid-type short-pulse (SP)-based ToF measurements under strong ambient light. The 8-tap demodulator implemented with multiple p-n junctions used for modulating the electric potential to [...] Read more.
This paper presents a time-of-flight image sensor based on 8-Tap P-N junction demodulator (PND) pixels, which is designed for hybrid-type short-pulse (SP)-based ToF measurements under strong ambient light. The 8-tap demodulator implemented with multiple p-n junctions used for modulating the electric potential to transfer photoelectrons to eight charge-sensing nodes and charge drains has an advantage of high-speed demodulation in large photosensitive areas. The ToF image sensor implemented using 0.11 µm CIS technology, consisting of an 120 (H) × 60 (V) image array of the 8-tap PND pixels, successfully works with eight consecutive time-gating windows with the gating width of 10 ns and demonstrates for the first time that long-range (>10 m) ToF measurements under high ambient light are realized using single-frame signals only, which is essential for motion-artifact-free ToF measurements. This paper also presents an improved depth-adaptive time-gating-number assignment (DATA) technique for extending the depth range while having ambient-light canceling capability and a nonlinearity error correction technique. By applying these techniques to the implemented image sensor chip, hybrid-type single-frame ToF measurements with depth precision of maximally 16.4 cm (1.4% of the maximum range) and the maximum non-linearity error of 0.6% for the full-scale depth range of 1.0–11.5 m and operations under direct-sunlight-level ambient light (80 klux) have been realized. The depth linearity achieved in this work is 2.5 times better than that of the state-of-the-art 4-tap hybrid-type ToF image sensor. Full article
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19 pages, 659 KiB  
Article
Sensing Algorithm to Estimate Slight Displacement and Posture Change of Target from Monocular Images
by Tadashi Ito, Hiroo Yoneyama, Yuto Akiyama, Tomonori Hagiwara and Shunsuke Ezawa
Sensors 2023, 23(2), 851; https://doi.org/10.3390/s23020851 - 11 Jan 2023
Cited by 2 | Viewed by 1931
Abstract
Various types of displacement sensors, which measure position changes of object, have been developed depending on the type and shape of the object under measurement, measurement range of the amount of displacement, required accuracy, and application. We are developing a new type of [...] Read more.
Various types of displacement sensors, which measure position changes of object, have been developed depending on the type and shape of the object under measurement, measurement range of the amount of displacement, required accuracy, and application. We are developing a new type of displacement sensor that is image-based, capable of measuring changes in 6DOF (3D position and orientation) of an object simultaneously, and is compact and low-cost. This displacement sensor measures the 6DOF of an object using images obtained by a monocular vision system. To confirm the usefulness of the proposed method, experimental measurements were conducted using a simple and inexpensive optical system. In this experiment, we were able to accurately measure changes of about 0.25 mm in displacement and 0.1 deg in inclination of the object at a distance of a few centimeters, and thus confirming the usefulness of the proposed method. Full article
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12 pages, 4523 KiB  
Communication
Improved Quasi-Z-Source High Step-Up DC–DC Converter Based on Voltage-Doubler Topology
by Toru Sai, Younghyun Moon and Yasuhiro Sugimoto
Sensors 2022, 22(24), 9893; https://doi.org/10.3390/s22249893 - 15 Dec 2022
Cited by 7 | Viewed by 1926
Abstract
The step-up DC–DC converter is widely used for applications such as IoT sensor nodes, energy harvesting, and photovoltaic (PV) systems. In this article, a new topological quasi-Z-source (QZ) high step-up DC–DC converter for the PV system is proposed. The topology of this converter [...] Read more.
The step-up DC–DC converter is widely used for applications such as IoT sensor nodes, energy harvesting, and photovoltaic (PV) systems. In this article, a new topological quasi-Z-source (QZ) high step-up DC–DC converter for the PV system is proposed. The topology of this converter is based on the voltage-doubler circuits. Compared with a conventional quasi-Z-source DC–DC converter, the proposed converter features low voltage ripple at the output, the use of a common ground switch, and low stress on circuit components. The new topology, named a low-side-drive quasi-Z-source boost converter (LQZC), consists of a flying capacitor (CF), the QZ network, two diodes, and a N-channel MOS switch. A 60 W laboratory prototype DC–DC converter achieved 94.9% power efficiency. Full article
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17 pages, 6238 KiB  
Article
Modified Triple-Tuned Bandpass Filter with Two Concurrently Tuned Transmission Zeros
by Mirosław Magnuski, Artur Noga, Maciej Surma and Dariusz Wójcik
Sensors 2022, 22(24), 9760; https://doi.org/10.3390/s22249760 - 13 Dec 2022
Cited by 2 | Viewed by 2209
Abstract
In this paper, a modified triple-tuned microstrip bandpass filter is presented. The filter consists of inductively cross-coupled resonators tuned with varactors. The application of the additional source-load couplings together with resonator branch swapping results in two transmission zeros tuned concurrently with operating frequency. [...] Read more.
In this paper, a modified triple-tuned microstrip bandpass filter is presented. The filter consists of inductively cross-coupled resonators tuned with varactors. The application of the additional source-load couplings together with resonator branch swapping results in two transmission zeros tuned concurrently with operating frequency. These transmission zeros placed on both sides of the passband significantly increase slope steepness in transition bands. The example filter tuned from 0.36 to 0.78 GHz and controlled by a single voltage was manufactured and validated by measurements. It has a constant fractional bandwidth of 11%, low in-band insertion loss ranging from 1.8 to 2.5 dB, and out-of-band attenuation up to 5 GHz without parasitic passbands. The obtained filter parameters made it useful for preselector networks. Full article
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17 pages, 11098 KiB  
Article
Circuit Techniques to Improve Low-Light Characteristics and High-Accuracy Evaluation System for CMOS Image Sensor
by Norihito Kato, Fukashi Morishita, Satoshi Okubo and Masao Ito
Sensors 2022, 22(16), 6040; https://doi.org/10.3390/s22166040 - 12 Aug 2022
Viewed by 3151
Abstract
The surveillance cameras we focus on target the volume zone, and area reduction is a top priority. However, by simplifying the ADC comparator, we face a new RUSH current issue, for which we propose a circuit solution. This paper proposes two novel techniques [...] Read more.
The surveillance cameras we focus on target the volume zone, and area reduction is a top priority. However, by simplifying the ADC comparator, we face a new RUSH current issue, for which we propose a circuit solution. This paper proposes two novel techniques of column-ADC for surveillance cameras to improve low-light characteristics. RUSH current compensation reduces transient current consumption fluctuations during AD conversion and utilizing timing shift ADCs decreases the number of simultaneously operating ADCs. These proposed techniques improve low-light characteristics because they reduce the operating noise of the circuit. In order to support small signal measurement, this paper also proposes a high-accuracy evaluation system that can measure both small optical/electrical signals in low-light circumstances. To demonstrate these proposals, test chips were fabricated using a 55 nm CIS process and their optical/electrical characteristics were measured. As a result, low-light linearity as optical characteristics were reduced by 63% and column interference (RUSH current) as an electrical characteristic was also reduced by 50%. As for the high-accuracy evaluation system, we confirmed that the inter-sample variation of column interference was 0.05 LSB. This ADC achieved a figure-of-merit (FoM) of 0.32 e-·pJ/step, demonstrating its usefulness for other ADC architectures while using a single-slope-based simple configuration. Full article
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14 pages, 3432 KiB  
Article
High Gain, Low Noise and Power Transimpedance Amplifier Based on Second Generation Voltage Conveyor in 65 nm CMOS Technology
by José C. García-Montesdeoca, Juan A. Montiel-Nelson and Javier Sosa
Sensors 2022, 22(16), 5997; https://doi.org/10.3390/s22165997 - 11 Aug 2022
Cited by 2 | Viewed by 3089
Abstract
A transimpedance amplifier (TIA) based on a voltage conveyor structure designed for high gain, low noise, low distortion, and low power consumption is presented in this work. Following a second-generation voltage conveyor topology, the current and voltage blocks are a regulated cascode amplifier [...] Read more.
A transimpedance amplifier (TIA) based on a voltage conveyor structure designed for high gain, low noise, low distortion, and low power consumption is presented in this work. Following a second-generation voltage conveyor topology, the current and voltage blocks are a regulated cascode amplifier and a down converter buffer, respectively. The proposed voltage buffer is designed for low distortion and low power consumption, whereas the regulated cascode is designed for low noise and high gain. The resulting TIA was fabricated in 65 nm CMOS technology for logic and mixed-mode designs, using low-threshold voltage transistors and a supply voltage of ±1.2 V. It exhibited a 52 dBΩ transimpedance gain and a 1.1 GHz bandwidth, consuming 55.3 mW using a ±1.2 V supply. Our preamplifier stage, based on a regulated cascode, was designed considering detector capacitance, bonding wire, and packaging capacitance. The voltage buffer was designed for low-power consumption and low distortion. The measured input-referred noise of the TIA was 22 pA/√Hz. The obtained total harmonic distortion of the TIA was close to 5%. In addition, the group delay is constant for the considered bandwidth. Comparisons against published results in terms of area (A), power consumption (P), bandwidth (BW), transimpedance gain (G), and noise (N) are were performed. Both figures of merit FoMs—the ratio √ (G × BW) and P × A—and FoM/N values demostrated the advantages of the proposed approach. Full article
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14 pages, 5578 KiB  
Communication
A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator
by Deeksha Verma, Khuram Shehzad, Sung Jin Kim, Young Gun Pu, Sang-Sun Yoo, Keum Cheol Hwang, Youngoo Yang and Kang-Yoon Lee
Sensors 2022, 22(14), 5393; https://doi.org/10.3390/s22145393 - 19 Jul 2022
Cited by 3 | Viewed by 5479
Abstract
A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance, several techniques have been [...] Read more.
A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance, several techniques have been proposed. A dual-path bootstrap switch was proposed to increase the linearity sampling. The Voltage Common Mode (VCM)-based Capacitive Digital-to-Analog Converter (CDAC) switching technique was implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. The proposed architecture of the two-stage dynamic latch comparator provides high speed and low power consumption. Moreover, to achieve faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement of a high-frequency external clock, as all conversions are carried out in a single clock cycle. The proposed error amplifier-based bandgap reference voltage generator provides a stable reference voltage to the ADC for practical implementation. The measurement results of the proposed SAR ADC, including an on-chip bandgap reference voltage generator, show an Effective Number of Bits (ENOB) of 9.49 bits and Signal-to-Noise and Distortion Ratio (SNDR) of 58.88 dB with 1.2 V of power supply while operating with a sampling rate of 1 MS/s. Full article
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19 pages, 3829 KiB  
Article
Identifying A(s) and β(s) in Single-Loop Feedback Circuits Using the Intermediate Transfer Function Approach
by Gordon Walter Roberts
Sensors 2022, 22(11), 4303; https://doi.org/10.3390/s22114303 - 6 Jun 2022
Viewed by 2415
Abstract
It is common practice to model the input–output behavior of a single-loop feedback circuit using the two parameters, A and β. Such an approach was first proposed by Black to explain the advantages and disadvantages of negative feedback. Extensive theories of system [...] Read more.
It is common practice to model the input–output behavior of a single-loop feedback circuit using the two parameters, A and β. Such an approach was first proposed by Black to explain the advantages and disadvantages of negative feedback. Extensive theories of system behavior (e.g., stability, impedance control) have since been developed by mathematicians and/or control engineers centered around these two parameters. Circuit engineers rely on these insights to optimize the dynamic behavior of their circuits. Unfortunately, no method exists for uniquely identifying A or β in terms of the components of the circuit. Rather, indirect methods, such as the injection method of Middlebrook or the break-the-loop approach proposed by Rosenstark, compute the return ratio RR of the feedback loop and inferred the parameters A and β. While one often assumes that the zeros of (1 + RR) are equal to the zeros of (1 + A × β), i.e., the closed-loop poles are equivalent, this is not true in general. It is the objective of this paper to present an exact method to uniquely identify each feedback parameter, A or β, in terms of the circuit components. Further, this paper will identify the circuit conditions for which the product of A × β leads to the correct closed-loop poles. Full article
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