Technologies

Research

20 pages, 1645 KiB

Open AccessEditor’s ChoiceArticle

Hardware Implementation of a Softmax-Like Function for Deep Learning

by Ioannis Kouretas and Vassilis Paliouras

Technologies 2020, 8(3), 46; https://doi.org/10.3390/technologies8030046 - 28 Aug 2020

Cited by 25 | Viewed by 10446

In this paper a simplified hardware implementation of a CNN softmax-like layer is proposed. Initially the softmax activation function is analyzed in terms of required numerical accuracy and certain optimizations are proposed. A proposed adaptable hardware architecture is evaluated in terms of the [...] Read more.

In this paper a simplified hardware implementation of a CNN softmax-like layer is proposed. Initially the softmax activation function is analyzed in terms of required numerical accuracy and certain optimizations are proposed. A proposed adaptable hardware architecture is evaluated in terms of the introduced error due to the proposed softmax-like function. The proposed architecture can be adopted to the accuracy required by the application by retaining or eliminating certain terms of the approximation thus allowing to explore accuracy for complexity trade-offs. Furthermore, the proposed circuits are synthesized in a 90 nm 1.0 V CMOS standard-cell library using Synopsys Design Compiler. Comparisons reveal that significant reduction is achieved in area × delay and power × delay products for certain cases, respectively, over prior art. Area and power savings are achieved with respect to performance and accuracy. Full article

(This article belongs to the Special Issue MOCAST 2019: Modern Circuits and Systems Technologies on Electronics)

► Show Figures

Figure 1

17 pages, 13338 KiB

Open AccessEditor’s ChoiceArticle

A Zynq-Based Robotic System for Treatment of Contagious Diseases in Hospital Isolated Environment

by Christos Paparizos, Nikolaos Tsafas and Michael Birbas

Technologies 2020, 8(2), 28; https://doi.org/10.3390/technologies8020028 - 15 May 2020

Cited by 4 | Viewed by 4318

Abstract

The rapid evolution of smart assisted living operations in combination with the blooming of commercial robots calls for the use of robotic based systems. Specifically, certain circumstances such as the handling of critical, contagious virus outbreaks like the recent novel Coronavirus epidemic can [...] Read more.

The rapid evolution of smart assisted living operations in combination with the blooming of commercial robots calls for the use of robotic based systems. Specifically, certain circumstances such as the handling of critical, contagious virus outbreaks like the recent novel Coronavirus epidemic can be benefited by an assisting mobile robot system controlled remotely, complementing measures like the isolation of patients from medical stuff. Within this context, the robotic-based solution to be employed needs to be easy to deploy, able to manufacture with low cost, and able to operate with ease by non-trained personnel. Also, to address the needs of existing hospitals, traditional or smart ones, as well as the temporary risk management facilities in, for example, quarantined cities, ease of integration in terms of size and infrastructure requirements is a must. In this work, the design and implementation of a robotic chassis bearing an arm manipulator is presented, addressing all these needs efficiently. Special attention has been given to the ease of teleoperation with minimal need for equipment and expertise, utilizing a Leap Motion virtual reality sensor which outweighs Microsoft’s Kinect capabilities. Furthermore, a reconfigurable hardware and software integrated system has been used to control the communication, algorithm processing and motion control utilizing a Xilinx Zynq system on chip (SoC). Full article

(This article belongs to the Special Issue MOCAST 2019: Modern Circuits and Systems Technologies on Electronics)

► Show Figures

Figure 1

14 pages, 782 KiB

Open AccessArticle

Comparison of Time Delay Estimation Methods Used for Fast Pipeline Leak Localization in High-Noise Environment

by Georgios-Panagiotis Kousiopoulos, Georgios-Napoleon Papastavrou, Dimitrios Kampelopoulos, Nikolaos Karagiorgos and Spiros Nikolaidis

Technologies 2020, 8(2), 27; https://doi.org/10.3390/technologies8020027 - 14 May 2020

Cited by 14 | Viewed by 4160

Abstract

Pipeline networks are one of the most efficient and extensively used means for transporting fluid products. However, they suffer from a serious problem that threatens their normal and secure operation, which is the occurrence of leaks. In this article, an acoustic technique for [...] Read more.

Pipeline networks are one of the most efficient and extensively used means for transporting fluid products. However, they suffer from a serious problem that threatens their normal and secure operation, which is the occurrence of leaks. In this article, an acoustic technique for the localization of leaks in pipelines placed in the high-noise environment of an oil refinery is described. This technique is based on the estimation of the time delay between the moments at which an acoustic signal produced by a leak reaches two sensors mounted on the external surface of the pipeline at a certain distance between them. For this reason, three different time delay estimation methods, based on the cross-correlation procedure, are studied in this article. These methods are tested for their accuracy in the estimation of the leak position, as well as for their ability to work with measurements of short duration and the results are compared. This is important because the acquisition duration affects directly the response time of the leak localization system, which is a crucial parameter for the targeted applications. Finally, an algorithm for fast and accurate identification of the leak point is proposed. Full article

(This article belongs to the Special Issue MOCAST 2019: Modern Circuits and Systems Technologies on Electronics)

► Show Figures

Figure 1

13 pages, 2599 KiB

Open AccessEditor’s ChoiceArticle

A New Simplified Model and Parameter Estimations for a HfO₂-Based Memristor †

by Valeri Mladenov

Technologies 2020, 8(1), 16; https://doi.org/10.3390/technologies8010016 - 7 Mar 2020

Cited by 2 | Viewed by 4232

Abstract

The purpose of this paper was to propose a complete analysis and parameter estimations of a new simplified and highly nonlinear hafnium dioxide memristor model that is appropriate for high-frequency signals. For the simulations; a nonlinear window function previously offered by the author [...] Read more.

The purpose of this paper was to propose a complete analysis and parameter estimations of a new simplified and highly nonlinear hafnium dioxide memristor model that is appropriate for high-frequency signals. For the simulations; a nonlinear window function previously offered by the author together with a highly nonlinear memristor model was used. This model was tuned according to an experimentally recorded current–voltage relationship of a HfO₂ memristor. This study offered an estimation of the optimal model parameters using a least squares algorithm in SIMULINK and a methodology for adjusting the model by varying its parameters overbroad ranges. The optimal values of the memristor model parameters were obtained after minimizing the error between the experimental and simulated current–voltage characteristics. A comparison of the obtained errors between the simulated and experimental current–voltage relationships was made. The error derived by the optimization algorithm was a little bit lower than that obtained by the used methodology. To avoid convergence problems; the step function in the considered model was replaced by a differentiable tangent hyperbolic function. A PSpice library model of the HfO₂ memristor based on its mathematical model was created. The considered model was successfully applied and tested in a multilayer memristor neural network with bridge memristor–resistor synapses Full article

(This article belongs to the Special Issue MOCAST 2019: Modern Circuits and Systems Technologies on Electronics)

► Show Figures

Figure 1

14 pages, 829 KiB

Open AccessEditor’s ChoiceArticle

High Throughput Implementation of the Keccak Hash Function Using the Nios-II Processor

by Argyrios Sideris, Theodora Sanida and Minas Dasygenis

Technologies 2020, 8(1), 15; https://doi.org/10.3390/technologies8010015 - 10 Feb 2020

Cited by 16 | Viewed by 6365

Abstract

Presently, cryptographic hash functions play a critical role in many applications, such as digital signature systems, security communications, protocols, and network security infrastructures. The new standard cryptographic hash function is Secure Hash Algorithm 3 (SHA-3), which is not vulnerable to attacks. The Keccak [...] Read more.

Presently, cryptographic hash functions play a critical role in many applications, such as digital signature systems, security communications, protocols, and network security infrastructures. The new standard cryptographic hash function is Secure Hash Algorithm 3 (SHA-3), which is not vulnerable to attacks. The Keccak algorithm is the winner of the NIST competition for the adoption of the new standard SHA-3 hash algorithm. In this work, we present hardware throughput optimization techniques for the SHA-3 algorithm using the Very High Speed Integrated Circuit Hardware Description Language (VHDL) programming language for all output lengths in the Keccak hash function (224, 256, 384 and 512). Our experiments were performed with the Nios II processor on the FPGA Arria 10 GX (10AX115N2P45E1SG). We applied two architectures, one without custom instruction and one with floating point hardware 2. Finally, we compare the results with other existing similar designs and found that the proposed design with floating point 2 optimizes throughput (Gbps) compared to existing FPGA implementations. Full article

(This article belongs to the Special Issue MOCAST 2019: Modern Circuits and Systems Technologies on Electronics)

► Show Figures

Figure 1

18 pages, 1605 KiB

Open AccessEditor’s ChoiceArticle

A Parametric EIT System Spice Simulation with Phantom Equivalent Circuits

by Christos Dimas, Nikolaos Uzunoglu and Paul Peter Sotiriadis

Technologies 2020, 8(1), 13; https://doi.org/10.3390/technologies8010013 - 1 Feb 2020

Cited by 15 | Viewed by 6999

Abstract

In this paper a number of LT Spice simulations have been carried out on an Electrical Impedance Tomography (EIT) system, which includes the whole analog and digital circuitry as well as the subject to be examined (phantom model). The aim of this study [...] Read more.

In this paper a number of LT Spice simulations have been carried out on an Electrical Impedance Tomography (EIT) system, which includes the whole analog and digital circuitry as well as the subject to be examined (phantom model). The aim of this study is to show how the analog and digital parts, the electrodes and the subject’s physical properties may impact the measurements and the quality of the reconstructed image. This could provide a useful tool for designing an EIT system. Special attention has been given to the current source’s output impedance and swing, to the noise produced by the circuits and to the Analog to Digital Converters (ADCs) resolution and sampling rate. Furthermore, some 3D phantom subjects have been modeled and simulated as equivalent circuits, merged with the EIT simulated hardware, in order to observe how changes on their properties interact with the whole circuitry and affect the final result. Observations show that mirrored current sources with

z_{o u t}

> 350 k

Ω

and sufficiently high ADC acquisition sampling rate (

f_{s a m p l e} \geq 16 f_{i n}

) can result to accurate impedance measurements and therefore quality image reconstruction within a frequency span of at least 10 to 100 kHz. Moreover, possible hardware failures (electrode disconnections and imbalanced contact impedances) can be detected with a simple examination of the first extracted image and measurement set, so that by direct modification of the reconstruction process, a corrected result can be obtained. Full article

(This article belongs to the Special Issue MOCAST 2019: Modern Circuits and Systems Technologies on Electronics)

► Show Figures

Figure 1

11 pages, 1399 KiB

Open AccessEditor’s ChoiceArticle

Accelerometer and Magnetometer Joint Calibration and Axes Alignment

by Konstantinos Papafotis and Paul P. Sotiriadis

Technologies 2020, 8(1), 11; https://doi.org/10.3390/technologies8010011 - 23 Jan 2020

Cited by 11 | Viewed by 5451

Abstract

In this work, we propose an algorithm for joint calibration and axes alignment of a 3-axis accelerometer and a 3-axis magnetometer. The proposed algorithm applies when the two sensors are fixed on the same rigid platform. It achieves accurate calibration without requiring any [...] Read more.

In this work, we propose an algorithm for joint calibration and axes alignment of a 3-axis accelerometer and a 3-axis magnetometer. The proposed algorithm applies when the two sensors are fixed on the same rigid platform. It achieves accurate calibration without requiring any external piece of equipment like a turntable for the accelerometer or Gauss magnetic chamber and Maxwell coils setup for the magnetometer. The efficiency and accuracy of the proposed algorithm are evaluated using experimental data. Full article

(This article belongs to the Special Issue MOCAST 2019: Modern Circuits and Systems Technologies on Electronics)

► Show Figures

Figure 1

14 pages, 1312 KiB

Open AccessArticle

Application-Specific SoC Design Using Core Mapping to 3D Mesh NoCs with Nonlinear Area Optimization and Simulated Annealing

by Jan Moritz Joseph, Dominik Ermel, Lennart Bamberg, Alberto García-Oritz and Thilo Pionteck

Technologies 2020, 8(1), 10; https://doi.org/10.3390/technologies8010010 - 23 Jan 2020

Cited by 2 | Viewed by 4041

Abstract

Core mapping, in which a core graph is mapped to a network graph to minimize communication, is a common design problem for Systems-on-Chip interconnected by a Network-on-Chip. In conventional multiprocessors, this mapping is area-agnostic as the cores in the core graph are uniform [...] Read more.

Core mapping, in which a core graph is mapped to a network graph to minimize communication, is a common design problem for Systems-on-Chip interconnected by a Network-on-Chip. In conventional multiprocessors, this mapping is area-agnostic as the cores in the core graph are uniform and therefore iso-area. This changes for Systems-on-Chip because tasks are mapped to specific blocks and not general-purpose cores. Thus, the area of these specific cores is varying. This requires novel mapping methods. In this paper, we propose a an area-aware cost function for simulated annealing; Furthermore, we advocate the use of nonlinear models as the area is nonlinear: A semi-definite program (SDP) can be used as it is sufficiently fast and shows 20% better area than conventional linear models. Our cost function allows for up to 16.4% better area, 2% better communication (bandwidth times hop distance) and 13.8% better total bandwidth in the network in comparison to the standard approach that accounts for both the network communication and uses cores with varying areas as well. Full article

(This article belongs to the Special Issue MOCAST 2019: Modern Circuits and Systems Technologies on Electronics)

► Show Figures

Figure 1

15 pages, 459 KiB

Open AccessArticle

The Importance of Introducing the OCTC Method to Undergraduate Students as a Tool for Circuit Analysis and Amplifier Design

by Nikolaos Voudoukis, Christos Dimas, Konstantinos Asimakopoulos, Dimitrios Baxevanakis, Konstantinos Papafotis, Konstantinos Oustoglou and Paul Peter Sotiriadis

Technologies 2020, 8(1), 7; https://doi.org/10.3390/technologies8010007 - 19 Jan 2020

Viewed by 6884

Abstract

The open-circuit-time-constant (OCTC) method is an approximate analytical computationally simple approach applicable to baseband amplifiers and cascades of them. It has a dual purpose: a) to estimate the dominant pole, and the −3dB bandwidth frequency, and b) to identify actual or parasitic component [...] Read more.

The open-circuit-time-constant (OCTC) method is an approximate analytical computationally simple approach applicable to baseband amplifiers and cascades of them. It has a dual purpose: a) to estimate the dominant pole, and the −3dB bandwidth frequency, and b) to identify actual or parasitic component values primarily responsible for this bandwidth guiding the designer in optimizing component values and circuit architecture. The present study focuses on the teaching of OCTC and the analysis of students’ depth of understanding. The OCTC module is part of the course “Electronics III” aimed towards advanced undergraduate students who are asked to solve two sets of problems analytically and simulate the circuits using LTspice and compare the results. The paper discusses students’ misconceptions and the evaluation of students’ performance via assignment grades, an anonymous sampling test and final exams (four exams during two academic years). A quantitative evaluation of the students’ perspective of the course is also presented based on two anonymous surveys, at the beginning and the end of the semester. According to the evaluation results, the proposed way of introducing the OCTC method along with the simulation exercises was beneficial for the students and improved their academic performance and attitude towards the course. Full article

(This article belongs to the Special Issue MOCAST 2019: Modern Circuits and Systems Technologies on Electronics)

► Show Figures

Figure 1

15 pages, 936 KiB

Open AccessEditor’s ChoiceArticle

A TensorFlow Extension Framework for Optimized Generation of Hardware CNN Inference Engines

by Vasileios Leon, Spyridon Mouselinos, Konstantina Koliogeorgi, Sotirios Xydis, Dimitrios Soudris and Kiamal Pekmestzi

Technologies 2020, 8(1), 6; https://doi.org/10.3390/technologies8010006 - 13 Jan 2020

Cited by 6 | Viewed by 7857

Abstract

The workloads of Convolutional Neural Networks (CNNs) exhibit a streaming nature that makes them attractive for reconfigurable architectures such as the Field-Programmable Gate Arrays (FPGAs), while their increased need for low-power and speed has established Application-Specific Integrated Circuit (ASIC)-based accelerators as alternative efficient [...] Read more.

The workloads of Convolutional Neural Networks (CNNs) exhibit a streaming nature that makes them attractive for reconfigurable architectures such as the Field-Programmable Gate Arrays (FPGAs), while their increased need for low-power and speed has established Application-Specific Integrated Circuit (ASIC)-based accelerators as alternative efficient solutions. During the last five years, the development of Hardware Description Language (HDL)-based CNN accelerators, either for FPGA or ASIC, has seen huge academic interest due to their high-performance and room for optimizations. Towards this direction, we propose a library-based framework, which extends TensorFlow, the well-established machine learning framework, and automatically generates high-throughput CNN inference engines for FPGAs and ASICs. The framework allows software developers to exploit the benefits of FPGA/ASIC acceleration without requiring any expertise on HDL development and low-level design. Moreover, it provides a set of optimization knobs concerning the model architecture and the inference engine generation, allowing the developer to tune the accelerator according to the requirements of the respective use case. Our framework is evaluated by optimizing the LeNet CNN model on the MNIST dataset, and implementing FPGA- and ASIC-based accelerators using the generated inference engine. The optimal FPGA-based accelerator on Zynq-7000 delivers 93% less memory footprint and 54% less Look-Up Table (LUT) utilization, and up to 10× speedup on the inference execution vs. different Graphics Processing Unit (GPU) and Central Processing Unit (CPU) implementations of the same model, in exchange for a negligible accuracy loss, i.e., 0.89%. For the same accuracy drop, the 45 nm standard-cell-based ASIC accelerator provides an implementation which operates at 520 MHz and occupies an area of 0.059 mm

^{2}

, while the power consumption is ∼7.5 mW. Full article

(This article belongs to the Special Issue MOCAST 2019: Modern Circuits and Systems Technologies on Electronics)

► Show Figures

Figure 1

15 pages, 869 KiB

Open AccessEditor’s ChoiceArticle

SET Pulse Characterization and SER Estimation in Combinational Logic with Placement and Multiple Transient Faults Considerations

by Georgios Ioannis Paliaroutis, Pelopidas Tsoumanis, Nestor Evmorfopoulos, George Dimitriou and Georgios I. Stamoulis

Technologies 2020, 8(1), 5; https://doi.org/10.3390/technologies8010005 - 10 Jan 2020

Cited by 4 | Viewed by 4326

Abstract

Integrated circuit susceptibility to radiation-induced faults remains a major reliability concern. The continuous downscaling of device feature size and the reduction in supply voltage in CMOS technology tend to worsen the problem. Thus, the evaluation of Soft Error Rate (SER) in the presence [...] Read more.

Integrated circuit susceptibility to radiation-induced faults remains a major reliability concern. The continuous downscaling of device feature size and the reduction in supply voltage in CMOS technology tend to worsen the problem. Thus, the evaluation of Soft Error Rate (SER) in the presence of multiple transient faults is necessary, since it remains an open research field. In this work, a Monte-Carlo simulation-based methodology is presented taking into consideration the masking mechanisms and placement information. The proposed SER estimation tool exploits the results of a Single Event Transient (SET) pulse characterization process with HSPICE to obtain an accurate assessment of circuit vulnerability to radiation. A new metric, called Glitch Latching Probability, which represents the impact of the masking effects on a SET, is introduced to identify gate sensitivity and, finally, experimental results on a set of ISCAS’ 89 benchmarks are presented. Full article

(This article belongs to the Special Issue MOCAST 2019: Modern Circuits and Systems Technologies on Electronics)

► Show Figures

Figure 1

19 pages, 5053 KiB

Open AccessArticle

Minimum MOS Transistor Count Fractional-Order Voltage-Mode and Current-Mode Filters

by Panagiotis Bertsias, Costas Psychalinos, Ahmed S. Elwakil and Brent Maundy

Technologies 2019, 7(4), 85; https://doi.org/10.3390/technologies7040085 - 6 Dec 2019

Cited by 3 | Viewed by 4807

Abstract

Voltage-mode and current-mode fractional-order filter topologies, which are capable of realizing various types of transfer functions, are introduced in this paper. Thanks to the employment of the transconductance parameter of the MOS transistors, the derived filter structures offer the benefit of the electronic [...] Read more.

Voltage-mode and current-mode fractional-order filter topologies, which are capable of realizing various types of transfer functions, are introduced in this paper. Thanks to the employment of the transconductance parameter of the MOS transistors, the derived filter structures offer the benefit of the electronic adjustment of their frequency characteristics. With regards to the literature, the number of MOS transisitors is minimized leading to significant reduction of the circuit complexity and power dissipation. Simulation results, derived using the Design Kit of the 0.35 μm Austria Mikro Systeme CMOS process and the Cadence IC design suite, confirm the correct operation of the presented filter structures. Full article

(This article belongs to the Special Issue MOCAST 2019: Modern Circuits and Systems Technologies on Electronics)

► Show Figures

Figure 1

16 pages, 6348 KiB

Open AccessEditor’s ChoiceArticle

An Inverse Pheromone Approach in a Chaotic Mobile Robot’s Path Planning Based on a Modified Logistic Map

by Eleftherios K. Petavratzis, Christos K. Volos, Lazaros Moysis, Ioannis N. Stouboulos, Hector E. Nistazakis, George S. Tombras and Kimon P. Valavanis

Technologies 2019, 7(4), 84; https://doi.org/10.3390/technologies7040084 - 6 Dec 2019

Cited by 17 | Viewed by 4558

Abstract

One major topic in the research of path planning of autonomous mobile robots is the fast and efficient coverage of a given terrain. For this purpose, an efficient method for covering a given workspace is proposed, based on chaotic path planning. The method [...] Read more.

One major topic in the research of path planning of autonomous mobile robots is the fast and efficient coverage of a given terrain. For this purpose, an efficient method for covering a given workspace is proposed, based on chaotic path planning. The method is based on a chaotic pseudo random bit generator that is generated using a modified logistic map, which is used to generate a chaotic motion pattern. This is then combined with an inverse pheromone approach in order to reduce the number of revisits in each cell. The simulated robot under study has the capability to move in four or eight directions. From extensive simulations performed in Matlab, it is derived that motion in eight directions gives superior results. Especially, with the inclusion of pheromone, the coverage percentage can significantly be increased, leading to better performance. Full article

(This article belongs to the Special Issue MOCAST 2019: Modern Circuits and Systems Technologies on Electronics)

► Show Figures

Figure 1

Journal Menu

Journal Browser

MOCAST 2019: Modern Circuits and Systems Technologies on Electronics

Share This Special Issue

Special Issue Editors

Special Issue Information

Keywords

Benefits of Publishing in a Special Issue

Related Special Issues

Published Papers (13 papers)

Research

Further Information

Guidelines

MDPI Initiatives

Follow MDPI