Application of Scattering Parameters to DPL Time-Lag Parameter Estimation at Nanoscale in Modern Integration Circuit Structures

Abstract

This paper presents the methodology of material parameters’ estimation for the dual-phase-lag (DPL) model at the nanoscale in modern integration circuit (IC) structures. The analyses and measurements performed were used in the unique dedicated micro-electro-mechanical system (MEMS) test structure. The electric and thermal domain of this structure was analysed. Finally, the silicon dioxide (SiO₂) temperature time-lag estimation procedure is presented based on the scattering parameters measured by a vector network analyser for the considered MEMS structure together with the 2-omega method. The proposed methodology has the ability to estimate the time-lag parameter with high accuracy and is also suitable for the temperature time-lag estimation for other manufacturing process technologies of ICs and other insulation materials used for integrated circuits such as silicon nitride (Si₃N₄), titanium nitride (TiN), and hafnium dioxide (HfO₂).

1. Introduction

The modelling and analysis of thermal and electromagnetic phenomena in integrated circuits (ICs) have great significance for the reliable design of modern nanoscale electronic structures and micro-electro-mechanical systems (MEMSs). It is also highly recommended to use this approach during various design-related activities. The most important of them are as follows: continuous decrease of semiconductor technology nodes, design cost reduction of microelectronic systems, and application of modern transistors in ICs (e.g., a fin field-effect transistor—FinFET [1,2], a gate-all-around field-effect transistor—GAAFET [3], and a vertical-slit field-effect transistor—VeSFET [4]).

Therefore, the presented work focuses on the following issues:

• The effective modelling and simulation methods of electromagnetic (EM) and thermal phenomena of integration circuits, micro-electro-mechanical systems (MEMSs), and 3D integrated systems (see [1,5]).
• The design of an equivalent electric circuit extractor and electrical simulation tools, e.g., [2,6,7].
• The verification of new simulation tools dedicated for the design of experimental application specific integrated circuits (ASICs).
• Estimation of IC material parameters for the nanometric technologies.

The first and last issues will be presented in the paper and are performed on scattering parameters measurements of a designed MEMS test structure with a printed circuit board (PCB) test board.

2. Heat Transfer at the Nanoscale

The heat transfer problems in solids can be described using Fourier’s theory [8,9]. The mathematical description is based on Fourier’s law and the Fourier–Kirchhoff (FK) equation and can be expressed as follows:

$$\{\begin{array}{c}{c}_v\frac{\partial T\left(x,t\right)}{\partial t}=-\nabla ·q\left(x,t\right)+q_v\left(x,t\right)\\ q\left(x,t\right)=-k·\nabla T\left(x,t\right)\end{array} \mathrm{for} x\in R^n,n\in N,t\in R_{+}\cup \left\{0\right\}$$

(1)

where q is heat flux vector; k is material thermal conductivity; T is distributed temperature; and c_v and q_V are volumetric heat capacity and value of internally generated heat, respectively. The FK equation has been commonly used to describe heat flow for over two centuries. However, the application of the FK equation has some significant limitations at the nanoscale [10].

The main limitation is related to the assumption of the infinite heat flow velocity in the semiconductor structure, which is very important in the case of nanostructures with a Knudsen number of Kn < 0.1 (where the characteristic length of IC is ca. ten times longer than the heat carrier mean free path 41.8 nm at 300 K [8]). Furthermore, the simultaneous change of temperature gradient and heat flux is a non-physical behaviour [9,10,11,12,13]; these phenomena have been presented in the case of nanosized structures in [8]. The second problem is associated with the radiative heat transfer and the Casimir effect (i.e., photons tunnelling) [14,15]; these phenomena occur in MEMSs [16] at small distances between surfaces (or particles). Both phenomena cause more dynamic and intense heat transfer than the classical Fourier–Kirchhoff and radiation models.

The new and more general dual-phase-lag (DPL) model of heat flow in solids at the nanoscale was introduced by Tzou [17,18] and is described with the following equations:

$$\{\begin{array}{c}{c}_v\frac{\partial T\left(x,t\right)}{\partial t}=-\nabla ·q\left(x,t\right)+q_v\left(x,t\right)\\ q\left(x,t\right)+{\tau }_q\frac{\partial q\left(x,t\right)}{\partial t}=-k\nabla T\left(x,t\right)-{\tau }_{T}k\nabla \frac{\partial T\left(x,t\right)}{\partial t}\end{array}$$

(2)

or

$${\tau }_q{c}_v\frac{{\partial }^{2}T\left(x,t\right)}{\partial t^2}+c_v\frac{\partial T\left(x,t\right)}{\partial t}=k\mathsf{\Delta }T\left(x,t\right)+{\tau }_{T}k\frac{\partial \mathsf{\Delta }T\left(x,t\right)}{\partial t}+q_v\left(x,t\right)+{\tau }_q\frac{\partial q_v\left(x,t\right)}{\partial t}$$

(3)

where τ_T and τ_q are temperature time-lag and heat flux time-lag, respectively. The simplified version of the DPL heat transfer model can be obtained for one time-lag parameter τ_q for τ_q > 0 and τ_T = 0. This equation was proposed by Cattaneo and Vernotte (CV) in [19,20,21,22,23,24,25,26] and is also used to eliminate the paradox of the heat-flux infinite velocity transfer.

The comprehensive presentation of the DPL model aspects is included in the following published sources:

• Modified boundary conditions, the DPL model simplification, and numerically effective 3D harmonic temperature models’ representation were presented in [1];
• Internal heat generation source analysis and its realistic approximation were presented in Appendix A and [19] (pp. 12–13 in Appendix A);
• Detailed analysis of anomalies and intriguing behaviours of the CV, DPL, and FK models were discussed by Vermeersch and De Mey, as well as Kovács and Ván, in [1,27,28,29] and [25];
• Material parameters are collected in [1,30];
• Detailed description of the most commonly used heat transfer models at the nanoscale was presented in [16] (pp. 1–4) [22,23,24,30].

The DPL model can be used to describe heat transfer behaviour in various solid materials (e.g., metals, bulk crystals, dielectrics, and amorphous materials). For most of them, indicative dual-phase time-lag parameters values (τ_T, τ_q) can be approximated using theoretical formulas [1]. Unfortunately, these parameters are strictly dependent on material density, fractal dimensions of material structure [30], and so on. Therefore, the values of the time-lag parameters should be empirically and independently characterised for each IC and MEMS technology process types. It is possible to perform empirical measurements of their values using a unique tool based on the femtosecond pulse laser with reflection mirrors for the following:

• Thin metals (Brorson et al. [31,32]; Elsayed-Ali [33]; and Qiu et al. [34,35,36,37]);
• No crystalline and amorphous materials (Fournier and Boccara [38]).

However, the test probes used for this purpose should be prepared not exactly like real structures in ICs and MEMSs. The first investigation of the dual-phase time-lag parameters estimation using dedicated MEMS structures with a measurement system implemented on a PCB was depicted in [39,40,41,42,43]. The authors of this paper propose the scattering wave parameters presented in [2] to extract the value of the dual-phase time-lag parameter τ_T.

3. Test Structure

The DPL model was verified using a dedicated test structure containing a 104 nm thin silicon oxide layer (SiO₂: ε_r = 3.9 [44,45], we assume a constant value up-to 13.5 GHz based on [46]; tan δ = 0.0002 [47]) placed between two platinum resistors (the top resistor: Pt: W_top = 2.75 μm, thickness h = 150 nm, length L = 460 μm, resistance R_top = 155 Ω at 20 °C [39,48,49]; the bottom resistor: Pt, W_bottom = 4.96 μm, thickness h = 150 nm, length L = 460 μm, resistance R_bottom = 262.3 Ω at 20 °C [39,48,49]). Generally, each resistor could be used either as a heat source line or a temperature sensor. The bottom resistor is treated as a heater, and the upper resistor is a temperature sensor. Each resistor has a four-wire connection for independent measurements of voltage and current. These elements are placed on a 100 nm wide silicon dioxide (SiO₂) layer stacked on a 400 µm thick silicon layer. The test structure presented in Figure 1c was manufactured in MEMS technology by the Institute of Electron Technology (ITE) in Warsaw, Poland [39,40,41,42,43,44,45]. The bottom and upper resistor dependence on temperature and their temperature rise dependence on heating power were measured and characterised in [39,40]. The entire structure is bonded to a metal copper foil on a PCB test board (Figure 1a,b).

4. Test Structure Models and Measurement Process

4.1. Thermal Model

The 2D DPL thermal model of the MEMS test structure is described with the application of the harmonic temperature models proposed in [1]:

$$\{\begin{array}{c}k\beta \mathsf{\Delta }{T}_r-k\gamma \mathsf{\Delta }{T}_i+\frac{g_0}{\sqrt{2}}=-\omega c_v{T}_i\\ k\beta \mathsf{\Delta }{T}_i+k\gamma \mathsf{\Delta }{T}_r \hspace{1em}\hspace{1em} =\hspace{1em}\omega c_v{T}_r\end{array}$$

(4)

$$\hspace{1em}\beta =\frac{1+{\tau }_T{\tau }_q{\omega }^2}{1+{\tau }_q^2{\omega }^2};\hspace{1em}\gamma =\frac{\left({\tau }_T-{\tau }_q\right)\omega }{1+{\tau }_q^2{\omega }^2}$$

(5)

where $\underset{\_}{T}=\underset{\_}{T}(x,y,z)=T_r+j{T}_i\in Z$ is harmonic temperature field distribution for angular frequency ω = 2πf, associated with the temperature in the following way:

$$T\left(x,y,z,t\right)=T_m\left(x,y,z\right) \sin \left(\omega t+\phi \left(x,y,z\right)\right)=\mathrm{Im}\left[\sqrt{2} \underset{\_}{T}\left(x,y,z\right) \exp \left(j\omega t\right)\right]$$

(6)

$$\sqrt{2} \underset{\_}{T}\left(x,y,z\right)=T_m\left(x,y,z\right) \exp \left(j\phi \left(x,y,z\right)\right)$$

(7)

Moreover, T_m and φ are amplitude and phase-shift for a given angular frequency, respectively. Please note that the maximal complex values of the harmonic temperature field are taken into consideration; thus, the coefficient $\sqrt{2}$ is introduced in Equations (4)–(7). The dissipated heat power generation per unit volume in the bottom resistor (g₀ > 0) is described in Appendix A. The heat power generation outside the bottom resistor is equal to zero g₀ = 0 W/m³. The following boundary conditions were applied:

• The upper side of the structure—the heat-free convection is encoded using Neumann boundary condition with a heat transfer coefficient equal to 658.763 W/(m²K).
• The left and right side of the structure—the symmetry is applied using Neumann boundary conditions.
• The Dirichlet boundary condition for the bottom side of the structure T_r = T_ambient, T_i = 0.

The material parameters are included in

Table 1. Considered material parameter values based on [1,30].

Material Name	$\mathit{k} \left[\frac{\mathbf{W}}{\mathbf{m}·\mathbf{K}}\right]$	${\mathit{c}}_{\mathit{v}}\left[\frac{\mathbf{kg}}{{\mathit{m}}^3\mathit{K}}\right]$	τq [ns]	τT [ns]
Silicon (Si)	160	1.78 × 106	3	120
Silicon dioxide (SiO2)	1.38	1.65 × 106	3	predicted: 50–120
Platinum (Pt)	71.6	2.85 × 106	0.0916	2.6 × 10−12

. In addition, calculated temperature distributions for 10 Hz, 1 kHz, 100 kHz, and 1 GHz are presented in

Table 2. The equivalent resistance and inductance of transmission line for low frequencies up to 1 MHz.

Conductor	Equivalent Resistance	Equivalent Inductance
Top resistor (Pt, Wtop = 2.75 μm., h = 150 nm, L = 460 μm)	155 Ω at 20 °C 0.3045 Ttop + 147.4524 Ω [44]	6.91443 × 10−10 H
Bottom resistor (Pt, Wbottom = 4.96 mm., h = 150 nm, L = 460 μm)	262.3 Ω at 20 °C 0.5064 Tbottom + 249.6276 Ω [44]	5.81732 × 10−10 H
PCB ground (Cu, Wground = 200 μm, h = 35 μm, L = 460 μm, ρCu = 1.72∙10−8 Ωm−1)	1.13 mΩ	2.62057 × 10−10 H
Equivalent capacitances and mutually coupled inductances: Ltop-bottom = 5.25685 × 10−10 H, Ltop-ground = 1.90503 × 10−10 H, Lbottom-ground = 1.90799 × 10−10 H, Ctop-bottom ≈ 0.56405 × 10−12 F, Cbottom-ground ≈ 0.631304 × 10−15 F.

.

As can be observed in Figure 2, the changes of temperature amplitude |T(x,y,f)| in SiO₂ are located around the bottom heating resistor at f = 100 MHz and higher frequencies. Therefore, SiO₂ thermal characterisation should be performed for f ≥ 100 MHz. Consequently, the simulations were carried out for the frequency in the range f = 200–900 MHz.

Values of a temperature time-lag and a heat flux time-lag for bulk SiO₂ material have been proposed in the literature equal to τ_T ≈ 60 ns and τ_q ≈ 3 ns, respectively (see [1,30]). Nevertheless, we also have to determine this value for the ITE process technologies. We want to propose a methodology of the DPL time lag estimation for other insulation materials applied in the integrated circuits, such as silicon nitride (Si₃N₄), titanium nitride (TiN), hafnium dioxide (HfO₂), and others. Thus, numerous simulations were carried out for the temperature time-lag-delay parameter in the range τ_T = 50–120 ns to find the estimated value.

The experiments and analyses carried out by Tomasz Raszkowski in his PhD thesis [50,51], concerning the transformation of the DPL equation into the Grünwald–Letnikov fractional space-derivative dual-phase-lag equation [16,46,47], indicate a lower influence of the heat flux time lag parameter τ_q for the whole thermal system response than for the temperature time lag parameter τ_T.

The analysis of the influence of time lag differences τ_T-τ_q [1] (pp. 140—Figure 2, pp. 143—Figures 5 and 6, pp. 142—Table 2) as well as the total thermal delay of complex IC thermal system [1] (pp. 151, see Table 6) show that the heat-flux time lag parameter is less critical than the temperature-time lag for final thermal system response. Therefore, we adopted its value equal to τ_q ≈ 3 ns, as proposed in the literature. Simulations were carried out and are presented in Figure 3. It can be noticed that the most significant change in the phase of temperature depending on the time-lags is recognised at the frequency range near 300 MHz and 500 MHz. However, the most significant amplitude of temperature changes on the upper resistor is observed close to the lower frequency f ≈ 300 MHz (see Figure 3a). Therefore, the highest sensitivity of time-lag estimation is at f ≈ 300 MHz. Finally, f ≈ 300 MHz frequency neighbourhood, in the range of τ_T = 50–120 ns and τ_q ≈ 3 ns, was selected as the best parameter value set for further investigation (Figure 4b).

Next, based on the collected simulation results, the linear regression was used to model the relationship between the temperature time-lag τ_T and the averaged phase-shift of the upper resistor temperature arg T(x,y,f). The function

$${{\tau }_T|}_{f=300\mathrm{MHz}}=2.391746 (\pm 0.064775)·\arg \left(T_{\mathrm{upper}}\right)-87.07922(\pm 4.52158)\hspace{1em}\left[\mathrm{ns},°\right]$$

(8)

is used for the analysed MEMS test structure, which is presented in Figure 1c (τ_T ∈ (50 ns, 120 ns) and τ_q = 3 ns) with R² = 0.999774.

4.2. Electrical Analysis and Final Measurement Procedure

The electrical behaviour or the MEMS test structure (Figure 1c) was determined using the Vector Network Analyzer PNA-X Microwave Agilent N5242A after application of the de-embedding procedure [2]. The electrical reference planes were set to the test board SMA (SubMiniature version A) connectors using Agilent N4691B Electronic Calibration Module. All non-utilised connectors were terminated. The complex scattering parameters (s₁₁, s₁₂, s₂₁, s₂₂) have to be measured at 32,000 spot frequency points in the range 10 kHz–15 GHz using 50 Ω characteristic impedance of the measurement equipment.

The analysis of the electric behaviour of the MEMS test structure (Figure 1d) and the PCB test board is based on the previous study about transmission lines presented in [2]. Therefore, the following conclusions were derived for the chosen frequency close to f ≈ 300 MHz:

• The upper and lower resistor lengths are very short compared with the wavelength at f ≈ 300 MHz. Therefore, the distributed character of both resistors shall be taken into account for f > c/(20 L ε_r^−1/2) ≈ 64 GHz, where c is the speed of the light in the vacuum, and the relative electric permittivity of SiO₂ is equal to ε_r ≈ 3.9. Consequently, only a de-embedded procedure for a PCB is required for the PCB transmission lines’ elimination [2].
• The investigation presented in [2] shows that the eddy-current losses (and skin effect) in a conductor and dielectric losses can be neglected with a 1.4% error up to 10 GHz and an error lower than 0.3% up to 2 GHz.
• The extracted parasitic parameters in Table 2 show that inductance and capacitance can be neglected for f ≈ 300 MHz.
• It should also be noted the self-heating can be neglected for a small current flowing through the platinum resistor (e.g., I_bottom ≤ 5 mA [44]).
• As can be noticed, the application of the network analyser allows for the direct measurement of the power wave transmitted through the MEMS test structure s₁₂ = s₂₁, which represents the insertion loss of the analysed network. To determine the temperature time-lag delay, we used the s₂₁ measurements for a frequency close to f = 150 MHz (n = 21 spot frequency points in the range 145 MHz ≤ f ≤ 155 MHz) and determined the averaged value and standard deviation of this parameter arg(s₂₁) = 62.3219 (±0.676051)° at f = 150 MHz, with the sum of error squares (SS) = 9.01973 and degrees of freedom (DOFs) = 21 (see Figure 5). Finally, the temperature time-lag delay can be calculated from Equation (8):

$${\tau }_T=61.9791(\pm 1.61694) \mathrm{ns} \mathrm{at} f=300 \mathrm{MHz}$$

(9)

4.3. Results and Discussions

As can be observed in Figure 2, the changes of temperature amplitude |T(x,y,f)| in SiO₂ are localised around the bottom heating resistor at f = 100 MHz and higher frequencies. Therefore, SiO₂ thermal characterisation should be performed for f ≥ 100 MHz.

Based on the simulation, it can be noticed that the best scopes for which we obtain the highest sensitivity of the measurement method are the frequency range near 300 MHz to 500 MHz (see Figure 4). However, the most significant amplitude of temperature changes on the upper resistor is observed close to the lower frequency f ≈ 300 MHz (Figure 3a).

Next, based on the collected simulation results, the linear regression was used to model the relationship between the temperature time-lag τ_T and the averaged phase-shift of the upper resistor temperature arg T(x,y,f) in the form of a function:

$${{\tau }_T|}_{f=300\mathrm{MHz}}=2.391746 (\pm 0.064775)·\arg \left(T_{\mathrm{upper}}\right)-87.07922(\pm 4.52158)\hspace{1em}\left[\mathrm{ns},°\right]$$

(10)

for the analysed MEMS test structure, which is presented in Figure 1c (τ_T ∈ (50 ns, 120 ns) and τ_q = 3 ns) with R² = 0.999774.

To determine the temperature time-lag delay, we used the s₂₁ measurements for a frequency close to f = 150 MHz and determined the averaged value and standard deviation of this parameter arg(s₂₁) = 62.3219 (±0.676051)° at f = 150 MHz (see Figure 4). Finally, the temperature time-lag delay can be calculated from Equations (8) and (10) using scattering parameters arg(s₂₁):

$${\tau }_T=61.9791(\pm 1.61694) \mathrm{ns} \mathrm{at} f=300 \mathrm{MHz}$$

(11)

for I_top ≤ 5 mA and I_bottom ≤ 5 mA [44].

5. Conclusions

This paper includes electromagnetic and thermal analyses of the MEMS test structure developed to validate the DPL model based on the methodology and tools presented in [2] for electric and thermal domains [1], respectively. The detailed analysis allows determining the best measurement frequency as well as electric and thermal model simplifications. Moreover, the new approach is associated with conducting measurements of electromagnetic scattering parameters together with simplification of the EM and thermal models of the MEMS test structure.

As a final result, we used a network analyser to determine the temperature time-lag delay in SiO₂ τ_T = 61.9791 (±1.61694) ns for assumed heat flux time-lag delay ${\tau }_q=3\mathrm{ns}$, which is a big challenge in the case of ICs and MEMSs. The final time-lag delay values are applicable for the devices manufactured in the technology process developed by the Institute of Electron Technology in Warsaw, Poland.

The proposed method is suitable for determining the time-lag delay parameters of other materials and other technological processes of ICs, which can be very important during thermal and electro-thermal investigations of advanced electronic nano structures. The ability of high accuracy estimation of temperature distribution in the newest electronic devices is very significant for the real thermal model analysis. As a result, it is crucial for the reliability of whole nanoscale appliances in modern semiconductor structures.