Journal of Low Power Electronics and Applications

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J. Low Power Electron. Appl., Volume 6, Issue 4 (December 2016) – 2 articles

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Low Power Design for Future Wearable and Implantable Devices

by Katrine Lundager, Behzad Zeinali, Mohammad Tohidi, Jens K. Madsen and Farshad Moradi

J. Low Power Electron. Appl. 2016, 6(4), 20; https://doi.org/10.3390/jlpea6040020 - 20 Oct 2016

Cited by 26 | Viewed by 13559

Abstract

With the fast progress in miniaturization of sensors and advances in micromachinery systems, a gate has been opened to the researchers to develop extremely small wearable/implantable microsystems for different applications. However, these devices are reaching not to a physical limit but a power limit, which is a critical limit for further miniaturization to develop smaller and smarter wearable/implantable devices (WIDs), especially for multi-task continuous computing purposes. Developing smaller and smarter devices with more functionality requires larger batteries, which are currently the main power provider for such devices. However, batteries have a fixed energy density, limited lifetime and chemical side effect plus the fact that the total size of the WID is dominated by the battery size. These issues make the design very challenging or even impossible. A promising solution is to design batteryless WIDs scavenging energy from human or environment including but not limited to temperature variations through thermoelectric generator (TEG) devices, body movement through Piezoelectric devices, solar energy through miniature solar cells, radio-frequency (RF) harvesting through antenna etc. However, the energy provided by each of these harvesting mechanisms is very limited and thus cannot be used for complex tasks. Therefore, a more comprehensive solution is the use of different harvesting mechanisms on a single platform providing enough energy for more complex tasks without the need of batteries. In addition to this, complex tasks can be done by designing Integrated Circuits (ICs), as the main core and the most power consuming component of any WID, in an extremely low power mode by lowering the supply voltage utilizing low-voltage design techniques. Having the ICs operational at very low voltages, will enable designing battery-less WIDs for complex tasks, which will be discussed in details throughout this paper. In this paper, a path towards battery-less computing is drawn by looking at device circuit co-design for future system-on-chips (SoCs). Full article

(This article belongs to the Special Issue Recent Advances in Emerging Low Power Circuits and Systems)

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InGaAs-OI Substrate Fabrication on a 300 mm Wafer

by Sebastien Sollier, Julie Widiez, Gweltaz Gaudin, Frederic Mazen, Thierry Baron, Mickail Martin, Marie-Christine Roure, Pascal Besson, Christophe Morales, Elodie Beche, Frank Fournel, Sylvie Favier, Amelie Salaun, Patrice Gergaud, Maryline Cordeau, Christellle Veytizou, Ludovic Ecarnot, Daniel Delprat, Ionut Radu and Thomas Signamarcheix

J. Low Power Electron. Appl. 2016, 6(4), 19; https://doi.org/10.3390/jlpea6040019 - 30 Sep 2016

Cited by 3 | Viewed by 7470

Abstract

In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs) wafer on insulator (InGaAs-OI) substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB) and Smart Cut^TM technology. Three key process steps of the integration were therefore specifically developed and optimized. The first one was the epitaxial growing process, designed to reduce the surface roughness of the InGaAs film. Second, direct wafer bonding conditions were investigated and optimized to achieve non-defective bonding up to 600 °C. Finally, we adapted the splitting condition to detach the InGaAs layer according to epitaxial stack specifications. The paper presents the overall process flow that achieved InGaAs-OI, the required optimization, and the associated characterizations, namely atomic force microscopy (AFM), scanning acoustic microscopy (SAM), and HR-XRD, to insure the crystalline quality of the post transferred layer. Full article

(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2015)

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J. Low Power Electron. Appl., Volume 6, Issue 4 (December 2016) – 2 articles

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