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JLPEA
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Emerging Network-on-Chip Architectures for Low Power Embedded Systems
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Emerging Network-on-Chip Architectures for Low Power Embedded Systems

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (31 January 2017) | Viewed by 54418

Special Issue Editor

Dr. Davide Patti

E-Mail Website
Guest Editor
Department of Computer Science and Telecommunications Engineering, University of Catania, 95124 Catania, Italy
Interests: network-on-chip; blockchains; machine learning; hardware accelerators
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Manycore architectures, formed by hundreds of processing elements, will soon replace traditional multicore architectures, bringing new opportunities and effective energy-performance trade-offs, but also introducing new design challenges.

Network-on-Chip emerged in recent years as a viable solution for the design of manycore embedded systems of the next generation. However, communication infrastructure scalability, memory bottleneck and parallelization of tasks, just to cite few examples, are becoming the limiting factors that hardware designers and software developers will be facing in the upcoming years.

This Special Issue on “Emerging Network-on-Chip Architectures for Low Power Embedded Systems” will focus on emerging approaches and recent advances on architectures, design techniques, modeling and prototyping solutions for the design of power/performance efficient Network-on-Chip systems in the manycore era.

Prof. Dr. Davide Patti
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Power Management algorithms and strategies for manycore architectures
  • Novel architectures for embedded low power computing
  • Energy-aware Parallel architectures for high performance computing
  • Design Platforms and Tools for optimizing energy/performance tradeoffs
  • New trends in Network-on-Chip architectures

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Published Papers (6 papers)

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Editorial

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150 KiB  
Editorial
A Summary of the Special Issue “Emerging Network-on-Chip Architectures for Low Power Embedded Systems”
by Davide Patti
J. Low Power Electron. Appl. 2017, 7(3), 18; https://doi.org/10.3390/jlpea7030018 - 29 Jun 2017
Viewed by 7569
Abstract
The International Technology Roadmap for Semiconductors [1] foresees that the number of processing elements that will be integrated into a system-on-chip will be on the order of thousands by 2020.[...] Full article
(This article belongs to the Special Issue Emerging Network-on-Chip Architectures for Low Power Embedded Systems)

Research

Jump to: Editorial

610 KiB  
Article
Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer
by Emmanuel Ofori-Attah, Washington Bhebhe and Michael Opoku Agyeman
J. Low Power Electron. Appl. 2017, 7(2), 14; https://doi.org/10.3390/jlpea7020014 - 29 May 2017
Cited by 14 | Viewed by 11149
Abstract
The disparity between memory and CPU have been ameliorated by the introduction of Network-on-Chip-based Chip-Multiprocessors (NoC-based CMPS). However, power consumption continues to be an aggressive stumbling block halting the progress of technology. Miniaturized transistors invoke many-core integration at the cost of high power [...] Read more.
The disparity between memory and CPU have been ameliorated by the introduction of Network-on-Chip-based Chip-Multiprocessors (NoC-based CMPS). However, power consumption continues to be an aggressive stumbling block halting the progress of technology. Miniaturized transistors invoke many-core integration at the cost of high power consumption caused by the components in NoC-based CMPs; particularly caches and routers. If NoC-based CMPs are to be standardised as the future of technology design, it is imperative that the power demands of its components are optimized. Much research effort has been put into finding techniques that can improve the power efficiency for both cache and router architectures. This work presents a survey of power-saving techniques for efficient NoC designs with a focus on the cache and router components, such as the buffer and crossbar. Nonetheless, the aim of this work is to compile a quick reference guide of power-saving techniques for engineers and researchers. Full article
(This article belongs to the Special Issue Emerging Network-on-Chip Architectures for Low Power Embedded Systems)
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852 KiB  
Article
Global Adaptation Controlled by an Interactive Consistency Protocol
by Alina Lenz and Roman Obermaisser
J. Low Power Electron. Appl. 2017, 7(2), 13; https://doi.org/10.3390/jlpea7020013 - 28 May 2017
Cited by 6 | Viewed by 8160
Abstract
Static schedules for systems can lead to an inefficient usage of the resources, because the system’s behavior cannot be adapted at runtime. To improve the runtime system performance in current time-triggered Multi-Processor System on Chip (MPSoC), a dynamic reaction to events is performed [...] Read more.
Static schedules for systems can lead to an inefficient usage of the resources, because the system’s behavior cannot be adapted at runtime. To improve the runtime system performance in current time-triggered Multi-Processor System on Chip (MPSoC), a dynamic reaction to events is performed locally on the cores. The effects of this optimization can be increased by coordinating the changes globally. To perform such global changes, a consistent view on the system state is needed, on which to base the adaptation decisions. This paper proposes such an interactive consistency protocol with low impact on the system w.r.t. latency and overhead. We show that an energy optimizing adaptation controlled by the protocol can enable a system to save up to 43% compared to a system without adaptation. Full article
(This article belongs to the Special Issue Emerging Network-on-Chip Architectures for Low Power Embedded Systems)
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2001 KiB  
Article
Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity
by Michael Opoku Agyeman, Wen Zong, Alex Yakovlev, Kin-Fai Tong and Terrence Mak
J. Low Power Electron. Appl. 2017, 7(2), 8; https://doi.org/10.3390/jlpea7020008 - 26 Apr 2017
Cited by 13 | Viewed by 8371
Abstract
To meet the performance and scalability demands of the fast-paced technological growth towards exascale and big data processing with the performance bottleneck of conventional metal-based interconnects (wireline), alternative interconnect fabrics, such as inhomogeneous three-dimensional integrated network-on-chip (3D NoC) and hybrid wired-wireless network-on-chip (WiNoC), [...] Read more.
To meet the performance and scalability demands of the fast-paced technological growth towards exascale and big data processing with the performance bottleneck of conventional metal-based interconnects (wireline), alternative interconnect fabrics, such as inhomogeneous three-dimensional integrated network-on-chip (3D NoC) and hybrid wired-wireless network-on-chip (WiNoC), have emanated as a cost-effective solution for emerging system-on-chip (SoC) design. However, these interconnects trade off optimized performance for cost by restricting the number of area and power hungry 3D routers and wireless nodes. Moreover, the non-uniform distributed traffic in a chip multiprocessor (CMP) demands an on-chip communication infrastructure that can avoid congestion under high traffic conditions while possessing minimal pipeline delay at low-load conditions. To this end, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in such emerging hybrid NoCs. The proposed router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath at low-loads. When the output port required for intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a non-speculative low-latency pipeline. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able to balance the traffic in hybrid NoCs to achieve low-latency communication under various traffic loads. Simulation shows that the proposed router can reduce applications’ execution time by an average of 16.9% compared to low-latency routers, such as SWIFT. By reducing the latency between 2D routers (or wired nodes) and 3D routers (or wireless nodes), the proposed router can improve the performance efficiency in terms of average packet delay by an average of 45 % (or 50 % ) in 3D NoCs (or WiNoCs). Full article
(This article belongs to the Special Issue Emerging Network-on-Chip Architectures for Low Power Embedded Systems)
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1187 KiB  
Article
Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications
by Fernando Gutierrez
J. Low Power Electron. Appl. 2017, 7(2), 6; https://doi.org/10.3390/jlpea7020006 - 29 Mar 2017
Cited by 9 | Viewed by 9159
Abstract
To allow fast communication—at several Gb/s—of multimedia content among processors and memories in a multi-processor system-on-chip, a new approach is emerging in literature: Wireless Network-on-Chip (WiNoC). With reference to this scenario, this paper presents the design of the key element of the WiNoC: [...] Read more.
To allow fast communication—at several Gb/s—of multimedia content among processors and memories in a multi-processor system-on-chip, a new approach is emerging in literature: Wireless Network-on-Chip (WiNoC). With reference to this scenario, this paper presents the design of the key element of the WiNoC: the antenna. Specifically, a bow-tie antenna is proposed, which operates at mm-waves and can be implemented on-chip using the top metal layer of a conventional silicon CMOS (Complementary Metal Oxide Semiconductor) technology. The antenna performance is discussed in the paper and is compared to the state-of-the-art, including the zig-zag antenna topology that is typically used in literature as a reference for WiNoC. The proposed bow-tie antenna design for WiNoC stands out for its good trade-off among bandwidth, gain, size and beamwidth vs. the state-of-the-art. Full article
(This article belongs to the Special Issue Emerging Network-on-Chip Architectures for Low Power Embedded Systems)
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1178 KiB  
Article
Energy Efficiency Effects of Vectorization in Data Reuse Transformations for Many-Core Processors—A Case Study †
by Abdullah Al Hasib, Lasse Natvig, Per Gunnar Kjeldsberg and Juan M. Cebrián
J. Low Power Electron. Appl. 2017, 7(1), 5; https://doi.org/10.3390/jlpea7010005 - 22 Feb 2017
Cited by 6 | Viewed by 8783
Abstract
Thread-level and data-level parallel architectures have become the design of choice in many of today’s energy-efficient computing systems. However, these architectures put substantially higher requirements on the memory subsystem than scalar architectures, making memory latency and bandwidth critical in their overall efficiency. Data [...] Read more.
Thread-level and data-level parallel architectures have become the design of choice in many of today’s energy-efficient computing systems. However, these architectures put substantially higher requirements on the memory subsystem than scalar architectures, making memory latency and bandwidth critical in their overall efficiency. Data reuse exploration aims at reducing the pressure on the memory subsystem by exploiting the temporal locality in data accesses. In this paper, we investigate the effects on performance and energy from a data reuse methodology combined with parallelization and vectorization in multi- and many-core processors. As a test case, a full-search motion estimation kernel is evaluated on Intel® CoreTM i7-4700K (Haswell) and i7-2600K (Sandy Bridge) multi-core processors, as well as on an Intel® Xeon PhiTM many-core processor (Knights Landing) with Streaming Single Instruction Multiple Data (SIMD) Extensions (SSE) and Advanced Vector Extensions (AVX) instruction sets. Results using a single-threaded execution on the Haswell and Sandy Bridge systems show that performance and EDP (Energy Delay Product) can be improved through data reuse transformations on the scalar code by a factor of ≈3× and ≈6×, respectively. Compared to scalar code without data reuse optimization, the SSE/AVX2 version achieves ≈10×/17× better performance and ≈92×/307× better EDP, respectively. These results can be improved by 10% to 15% using data reuse techniques. Finally, the most optimized version using data reuse and AVX512 achieves a speedup of ≈35× and an EDP improvement of ≈1192× on the Xeon Phi system. While single-threaded execution serves as a common reference point for all architectures to analyze the effects of data reuse on both scalar and vector codes, scalability with thread count is also discussed in the paper. Full article
(This article belongs to the Special Issue Emerging Network-on-Chip Architectures for Low Power Embedded Systems)
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