Advanced Packaging for Microsystem Applications, 3rd Edition

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "A:Physics".

Deadline for manuscript submissions: 31 March 2025 | Viewed by 11315

Special Issue Editors


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Guest Editor
School of Electro-Mechanical Engineering, Xidian University, Xi’an 710000, China
Interests: MEMS technology; electronic packaging and microassembly technology
Special Issues, Collections and Topics in MDPI journals

E-Mail Website
Guest Editor
School of Electro-Mechanical Engineering, Xidian University, Xi’an 710000, China
Interests: MEMS technology; electronic packaging and microassembly technology; smart materials
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

In line with the fast-moving trends of microelectronic technology, recent years have seen the optimization of microsystems and their different electronic components towards reduced size, high performance, high frequency, and high reliability. However, significant challenges have arisen in the application of advanced packaging materials and techniques in MEMS/NEMS. For example, complex operating environments can significantly affect mechanical and electrical properties, greatly influencing the reliability of these devices and systems. Consequently, the physical properties, design, and preparation of novel packaging materials and techniques need further study to optimize micro-/nanodevices. The design and manufacturing process can directly affect the reliability, cost, and performance of these products. However, the modeling and simulation of electronic packaging, in lieu of experimentation, can overcome many of these problems.

Accordingly, this Special Issue seeks to showcase research papers and review articles that focus on advanced packaging, materials, microsystems, the reliability of devices and systems, and micro-/nanodevices. Topics of interest might include, but are not limited to, the following:

  • Advanced packaging technology;
  • The reliability of devices and systems;
  • Advanced packaging materials;
  • MEMS/NEMS;
  • Microsystems.

Prof. Dr. Wenchao Tian
Dr. Yongkun Wang
Guest Editors

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Keywords

  • advanced packaging technology
  • MEMS
  • reliability
  • NEMS
  • packaging materials
  • modeling and simulation
  • design and manufacturing process
  • microsystems

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Published Papers (3 papers)

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Research

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15 pages, 2370 KiB  
Article
Design and Optimization of a Fan-Out Wafer-Level Packaging- Based Integrated Passive Device Structure for FMCW Radar Applications
by Jiajie Yang, Lixin Xu and Ke Yang
Micromachines 2024, 15(11), 1311; https://doi.org/10.3390/mi15111311 - 29 Oct 2024
Viewed by 498
Abstract
This paper presents an integrated passive device (IPD) structure based on fan-out wafer-level packaging (FOWLP) for the front end of frequency-modulated continuous wave (FMCW) radar systems, focusing on enhancing the integration efficiency and performance of large passive components like antennas. Additionally, a new [...] Read more.
This paper presents an integrated passive device (IPD) structure based on fan-out wafer-level packaging (FOWLP) for the front end of frequency-modulated continuous wave (FMCW) radar systems, focusing on enhancing the integration efficiency and performance of large passive components like antennas. Additionally, a new metric is introduced to assess this structure’s effect on the average noise figure in FMCW systems. Using this metric as a loss function, we apply the support vector machine (SVM) for electromagnetic simulation and the genetic algorithm (GA) for optimization. The sample fitting variance is 2.42 dB, reducing computation time from 12 min to under 1 millisecond, with the entire optimization completed in less than 100 s. The optimized IPD structure is 0.7 × 0.9 × 0.014 λ03 in size and achieves over 35 dB isolation between the transmitter and receiver. Compared to the IPD model calculated by empirical formulas, the optimized device lowers the average noise figure by 15.2 dB and increases maximum gain by 4.19 dB. Full article
(This article belongs to the Special Issue Advanced Packaging for Microsystem Applications, 3rd Edition)
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10 pages, 3947 KiB  
Article
Influence of Normal-to-High Anodizing Voltage on AAO Surface Hardness from 1050 Aluminum Alloy in Oxalic Acid
by Chin-An Ku, Chen-Chieh Wu, Chia-Wei Hung and Chen-Kuei Chung
Micromachines 2024, 15(6), 683; https://doi.org/10.3390/mi15060683 - 23 May 2024
Viewed by 3423
Abstract
Anodic aluminum oxide (AAO) has been widely applied for the surface protection of electronic component packaging through a pore-sealing process, with the enhanced hardness value reaching around 400 Vickers hardness (HV). However, the traditional AAO fabrication at 0~10 °C for surface protection takes [...] Read more.
Anodic aluminum oxide (AAO) has been widely applied for the surface protection of electronic component packaging through a pore-sealing process, with the enhanced hardness value reaching around 400 Vickers hardness (HV). However, the traditional AAO fabrication at 0~10 °C for surface protection takes at least 3–6 h for the reaction or other complicated methods used for the pore-sealing process, including boiling-water sealing, oil sealing, or salt-compound sealing. With the increasing development of nanostructured AAO, there is a growing interest in improving hardness without pore sealing, in order to leverage the characteristics of porous AAO and surface protection properties simultaneously. Here, we investigate the effect of voltage on hardness under the same AAO thickness conditions in oxalic acid at room temperature from a normal level of 40 V to a high level of 100 V and found a positive correlation between surface hardness and voltage. The surface hardness values of AAO formed at 100 V reach about 423 HV without pore sealing in 30 min. By employing a hybrid pulse anodization (HPA) method, we are able to prevent the high-voltage burning effect and complete the anodization process at room temperature. The mechanism behind this can be explained by the porosity and photoluminescence (PL) intensity of AAO. For the same thickness of AAO from 40~100 V, increasing the anodizing voltage decreases both the porosity and PL intensity, indicating a reduction in pores, as well as anion and oxygen vacancy defects, due to rapid AAO growth. This reduction in defects in the AAO film leads to an increase in hardness, allowing us to significantly enhance AAO hardness without a pore-sealing process. This offers an effective hardness enhancement in AAO under economically feasible conditions for the application of hard coatings and protective films. Full article
(This article belongs to the Special Issue Advanced Packaging for Microsystem Applications, 3rd Edition)
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Review

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24 pages, 7449 KiB  
Review
Progress in Research on Co-Packaged Optics
by Wenchao Tian, Huahua Hou, Haojie Dang, Xinxin Cao, Dexin Li, Si Chen and Bingxu Ma
Micromachines 2024, 15(10), 1211; https://doi.org/10.3390/mi15101211 - 29 Sep 2024
Viewed by 4571
Abstract
In the 5G era, the demand for high-bandwidth computing, transmission, and storage has led to the development of optoelectronic interconnect technology. This technology has evolved from traditional board-edge optical modules to smaller and more integrated solutions. Co-packaged optics (CPO) has evolved as a [...] Read more.
In the 5G era, the demand for high-bandwidth computing, transmission, and storage has led to the development of optoelectronic interconnect technology. This technology has evolved from traditional board-edge optical modules to smaller and more integrated solutions. Co-packaged optics (CPO) has evolved as a solution to meet the growing demand for data. Compared to typical optoelectronic connectivity technology, CPO presents distinct benefits in terms of bandwidth, size, weight, and power consumption. This study presents an overview of CPO, highlighting its fundamental principles, advantages, and distinctive features. Additionally, it examines the current research progress of two distinct approaches utilizing Vertical-Cavity Surface-Emitting Laser (VCSEL) and silicon photonics integration technology. Additionally, it provides a concise overview of the many application situations of CPO. Expanding on this, the analysis focuses on the CPO using 2D, 2.5D, and 3D packaging techniques. Lastly, taking into account the present technological environment, the scientific obstacles encountered by CPO are analyzed, and its future progress is predicted. Full article
(This article belongs to the Special Issue Advanced Packaging for Microsystem Applications, 3rd Edition)
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