New Developments for Circuit Design: Synthesis, Modeling, Simulation, and Applications

Topic Information

Dear Colleagues,

This Topic will present New Developments for Circuit Design: Synthesis, Modeling, Simulation, and Applications. These developments include modeling, simulation, and synthesis for Analog, Mixed-signal, RF (AMS/RF), and multi-domain (nanoelectronics, biological, MEMS, optoelectronics, etc.) integrated circuits and systems, as well as, emerging technologies and applications. Open-source tools and methods for IC design and experiences with modeling, simulation, and synthesis techniques in diverse application areas are also welcomed. Objective technologies include CMOS, beyond CMOS, and More-than-Moore such as MEMs, power devices, sensors, passives, etc.

This topic seeks to publish original reviews, original articles or communications. We encourage submissions of manuscripts focusing on, but not limited to, current research, novel concepts, technologies and approaches in basic and advanced aspects of Circuit Design.

1. CAD and EDA methodologies and tools for AMS systems (CAD/EDA)

Synthesis, Sizing and Optimization

• Multi-level Synthesis Methods
• Physical Synthesis Methods
• High-frequency Circuits and Systems Design
• Low-Power and Energy-Aware Design
• Parasitic-Aware Design
• Variability-aware & Reliability-Aware Design
• Sizing and Optimization Methods
• Procedural Design Methods

Modeling

• Performance Modeling
• Power and Electro-thermal Modeling
• Reliability and Variability Modeling
• RF/microwave/mm-wave Modeling
• Model Order Reduction
• Modeling for Signal Integrity / Power Integrity
• Electromagnetic Compatibility and Signal Integrity
• Electromagnetic Theory and Modeling
• Transmission Line Theory and Modeling
• Automated Model Generation

Simulation, Verification and Test

• Behavioral Simulation
• Numerical and Symbolic Simulation Methods
• RF Circuit Simulation Methods
• Multilevel Simulation Techniques
• Analysis of Variability Effects
• Simulation for Signal Integrity/Power Integrity
• Formal and Functional Verification
• Functional Safety
• Test and Design-for-Test Techniques

2. Emerging technologies and applications (ETA)

CAD for/using Emerging Technologies

• CAD for Bio-Electronic Devices, Bio-Sensors
• CAD for Multi-Domain Devices and Circuits
• CAD for Nanophotonics and Optical Devices / Interconnects
• CAD using AI and ML Algorithms
• CAD using Cloud Computing
• AMS CAS Soft and Hard IP Blocks Generating Methodologies

Emerging Devices and Paradigms

• Emerging Device Modeling (Steep-Slope, TFET, NCFET, PTM, Memristor)
• Design Strategies using Emerging Devices
• Emerging Devices in Security
• Devices, Hardware and Methods for Bio-Inspired and Neuromorphic Computing

Hardware Security

• Hardware Security primitives (PUFs, RNGs, ...)
• Attacks and Countermeasures
• Anticounterfeiting
• Methods, Architectures and Tools for Secure Design

3. AMS ICs and multi-domain design applications (DES)

Design Applications

• Internet of Everything
• Automotive Systems
• Biomedical and Bio-inspired CAS
• Low-Power Low Voltage CAS
• Sensors and Sensing Systems
• Security Systems
• Aerospace Systems
• Renewable Energy Systems

Dr. Nestor Evmorfopoulos
Prof. Dr. Alkiviadis Hatzopoulos
Prof. Dr. George I. Stamoulis
Topic Editors

Keywords

Participating Journals

Journal Name	Impact Factor	CiteScore	Launched Year	First Decision (median)	APC
Automation automation	-	2.9	2020	20.6 Days	CHF 1000	Submit
Electronics electronics	2.6	5.3	2012	16.8 Days	CHF 2400	Submit
Eng eng	-	2.1	2020	28.3 Days	CHF 1200	Submit
Hardware hardware	-	-	2023	15.0 days *	CHF 1000	Submit
Micromachines micromachines	3.0	5.2	2010	17.7 Days	CHF 2600	Submit
Signals signals	-	3.2	2020	26.1 Days	CHF 1000	Submit

* Median value for all MDPI journals in the first half of 2024.

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Published Papers (8 papers)

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All Automation Electronics Eng Hardware Micromachines Signals

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13 pages, 4866 KiB  

Open AccessArticle

Design of a Low-Cost and High-Precision Measurement System Suitable for Organic Transistors

by Vratislav Režo and Martin Weis

Electronics 2024, 13(22), 4475; https://doi.org/10.3390/electronics13224475 - 14 Nov 2024

Viewed by 450

Abstract

Organic field-effect transistors (OFETs) require ultra-precise electrical measurements due to their unique charge transport mechanisms and sensitivity to environmental factors, yet commercial semiconductor parameter analysers capable of such measurements are prohibitively expensive for many research laboratories. This study introduces a novel, cost-effective, and [...] Read more.

Organic field-effect transistors (OFETs) require ultra-precise electrical measurements due to their unique charge transport mechanisms and sensitivity to environmental factors, yet commercial semiconductor parameter analysers capable of such measurements are prohibitively expensive for many research laboratories. This study introduces a novel, cost-effective, and portable setup for high-precision OFET characterisation that addresses this critical need, providing a feasible substitute for conventional analysers costing tens of thousands of dollars. The suggested system incorporates measurement, data processing, and graphical visualisation capabilities, together with Bluetooth connectivity for local operation and Wi-Fi functionality for remote data monitoring. The device consists of a motherboard and specialised cards for low-current measurement, voltage measurement, and voltage generation, providing comprehensive OFET characterisation, including transfer and output characteristics, in accordance with IEEE-1620 standards. The system can measure current from picoamperes to milliamperes, with voltage measurements supported by high input resistance (>100 MΩ) and a voltage generation range of −30 V to +30 V. This versatile and accessible approach greatly improves the opportunities for future OFET research and development. Full article

(This article belongs to the Topic New Developments for Circuit Design: Synthesis, Modeling, Simulation, and Applications)

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15 pages, 13605 KiB  

Open AccessArticle

Dynamic Performance and Power Optimization with Heterogeneous Processing-in-Memory for AI Applications on Edge Devices

by Sangmin Jeon, Kangju Lee, Kyeongwon Lee and Woojoo Lee

Micromachines 2024, 15(10), 1222; https://doi.org/10.3390/mi15101222 - 30 Sep 2024

Viewed by 1402

Abstract

The rapid advancement of artificial intelligence (AI) technology, combined with the widespread proliferation of Internet of Things (IoT) devices, has significantly expanded the scope of AI applications, from data centers to edge devices. Running AI applications on edge devices requires a careful balance [...] Read more.

The rapid advancement of artificial intelligence (AI) technology, combined with the widespread proliferation of Internet of Things (IoT) devices, has significantly expanded the scope of AI applications, from data centers to edge devices. Running AI applications on edge devices requires a careful balance between data processing performance and energy efficiency. This challenge becomes even more critical when the computational load of applications dynamically changes over time, making it difficult to maintain optimal performance and energy efficiency simultaneously. To address these challenges, we propose a novel processing-in-memory (PIM) technology that dynamically optimizes performance and power consumption in response to real-time workload variations in AI applications. Our proposed solution consists of a new PIM architecture and an operational algorithm designed to maximize its effectiveness. The PIM architecture follows a well-established structure known for effectively handling data-centric tasks in AI applications. However, unlike conventional designs, it features a heterogeneous configuration of high-performance PIM (HP-PIM) modules and low-power PIM (LP-PIM) modules. This enables the system to dynamically adjust data processing based on varying computational load, optimizing energy efficiency according to the application’s workload demands. In addition, we present a data placement optimization algorithm to fully leverage the potential of the heterogeneous PIM architecture. This algorithm predicts changes in application workloads and optimally allocates data to the HP-PIM and LP-PIM modules, improving energy efficiency. To validate and evaluate the proposed technology, we implemented the PIM architecture and developed an embedded processor that integrates this architecture. We performed FPGA prototyping of the processor, and functional verification was successfully completed. Experimental results from running applications with varying workload demands on the prototype PIM processor demonstrate that the proposed technology achieves up to 29.54% energy savings. Full article

(This article belongs to the Topic New Developments for Circuit Design: Synthesis, Modeling, Simulation, and Applications)

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32 pages, 3732 KiB  

Open AccessArticle

ALPRI-FI: A Framework for Early Assessment of Hardware Fault Resiliency of DNN Accelerators

by Karim Mahmoud and Nicola Nicolici

Electronics 2024, 13(16), 3243; https://doi.org/10.3390/electronics13163243 - 15 Aug 2024

Viewed by 758

Abstract

Understanding how faulty hardware affects machine learning models is important to both safety-critical systems and the cloud infrastructure. Since most machine learning models, like Deep Neural Networks (DNNs), are highly computationally intensive, specialized hardware accelerators are developed to improve performance and energy efficiency. [...] Read more.

Understanding how faulty hardware affects machine learning models is important to both safety-critical systems and the cloud infrastructure. Since most machine learning models, like Deep Neural Networks (DNNs), are highly computationally intensive, specialized hardware accelerators are developed to improve performance and energy efficiency. Evaluating the fault resilience of these DNN accelerators during early design and implementation stages provides timely feedback, making it less costly to revise designs and address potential reliability concerns. To this end, we introduce Architecture-Level Pre-Register-Transfer-Level Implementation Fault Injection (ALPRI-FI), which is a comprehensive framework for assessing the fault resilience of DNN models deployed on hardware accelerators. Full article

(This article belongs to the Topic New Developments for Circuit Design: Synthesis, Modeling, Simulation, and Applications)

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15 pages, 3105 KiB  

Open AccessArticle

Temperature Characteristics Modeling for GaN PA Based on PSO-ELM

by Qian Lin and Meiqian Wang

Micromachines 2024, 15(8), 1008; https://doi.org/10.3390/mi15081008 - 5 Aug 2024

Viewed by 831

Abstract

In order to solve the performance prediction and design optimization of power amplifiers (PAs), the performance parameters of Gallium Nitride high-electron-mobility transistor (GaN HEMT) PAs at different temperatures are modeled based on the particle swarm optimization–extreme learning machine (PSO-ELM) and extreme learning machine [...] Read more.

In order to solve the performance prediction and design optimization of power amplifiers (PAs), the performance parameters of Gallium Nitride high-electron-mobility transistor (GaN HEMT) PAs at different temperatures are modeled based on the particle swarm optimization–extreme learning machine (PSO-ELM) and extreme learning machine (ELM) in this paper. Then, it can be seen that the prediction accuracy of the PSO-ELM model is superior to that of ELM with a minimum mean square error (MSE) of 0.0006, which indicates the PSO-ELM model has a stronger generalization ability when dealing with the nonlinear relationship between temperature and PA performance. Therefore, this investigation can provide vital theoretical support for the performance optimization of PA design. Full article

(This article belongs to the Topic New Developments for Circuit Design: Synthesis, Modeling, Simulation, and Applications)

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8 pages, 4241 KiB  

Open AccessArticle

Design of X-Band Circulator and Isolator for High-Peak-Power Applications

by Tao Tang, Xiexun Zhang, Maged A. Aldhaeebi and Thamer S. Almoneef

Micromachines 2024, 15(7), 916; https://doi.org/10.3390/mi15070916 - 16 Jul 2024

Viewed by 953

Abstract

This paper presents a design of a X-band circulator–isolator for handling high-peak-power applications. The device consists of two cascade-connected ferrite circulators, with one dedicated to transmission and the other to small-signal reception coupled with high-power signal isolation. To improve the power capacity, a [...] Read more.

This paper presents a design of a X-band circulator–isolator for handling high-peak-power applications. The device consists of two cascade-connected ferrite circulators, with one dedicated to transmission and the other to small-signal reception coupled with high-power signal isolation. To improve the power capacity, a layer of poly-tetra fluoroethylene (PTFE) film is placed above and below the circulator’s and the isolator’s center conductors. Measurement results show that the device is capable of withstanding a peak power of 7000 W, with an insertion loss of <0.3 dB at the transmitting port. Similarly, it sustains a peak power of 6000 W with an insertion loss of <0.5 dB at the reception port. Moreover, the proposed design achieved isolation between the transmitting and receiving ends of >20 dB with a VSWR < 1.2 at each port. Thermal analysis shows that the maximum relative ambient temperature rise is 15.11 ${ }^{\circ }$C. These findings show that the proposed device achieves low-loss transmission of high-peak-power signals in the transmit channel and reverse isolation of high-peak-power signals in the receive channel. Full article

(This article belongs to the Topic New Developments for Circuit Design: Synthesis, Modeling, Simulation, and Applications)

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15 pages, 8399 KiB  

Open AccessArticle

A Low Mismatch Current Charge Pump Applied to Phase-Locked Loops

by Min Guo, Lixin Wang, Shixin Wang, Jiacheng Lu and Mengyao Cui

Micromachines 2024, 15(7), 913; https://doi.org/10.3390/mi15070913 - 14 Jul 2024

Viewed by 1347

Abstract

This paper presents a charge pump circuit with a wide output range and low current mismatch applied to phase-locked loops. In this designed structure, T-shaped analog switches are adopted to suppress the non-ideal effects of clock feedthrough, switching time mismatch, and charge injection. [...] Read more.

This paper presents a charge pump circuit with a wide output range and low current mismatch applied to phase-locked loops. In this designed structure, T-shaped analog switches are adopted to suppress the non-ideal effects of clock feedthrough, switching time mismatch, and charge injection. A source follower and current splitting circuits are proposed to improve the matching accuracy of the charging and discharging currents and reduce the current mismatch rate. A rail-to-rail high-gain amplifier with a negative feedback connection is introduced to suppress the charge-sharing effect of the charge pump. A cascode current mirror with a high output impedance is used to provide the charge and discharge currents for the charge pump, which not only improves the current accuracy of the charge pump but also increases the output voltage range. The proposed charge pump is designed and simulated based on a 65 nm CMOS process. The results show that when the power supply voltage is 1.2 V, the output current of the charge pump is 100 μA, the output voltage is in the range of 0.2~1 V, and the maximum current mismatch rate and current variation rate are only 0.21% and 1.4%, respectively. Full article

(This article belongs to the Topic New Developments for Circuit Design: Synthesis, Modeling, Simulation, and Applications)

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23 pages, 29672 KiB  

Open AccessArticle

Improved Implementation of Chua’s Circuit on an Active Inductor and Non-Autonomous System

by Ziqi Zhang, Yiming Wen, Yafei Ning, Zirui Zhang, Hu Li and Yuhan Xia

Electronics 2024, 13(13), 2637; https://doi.org/10.3390/electronics13132637 - 4 Jul 2024

Viewed by 720

Abstract

Chua’s circuit is a well-established model for studying chaotic phenomena and is extensively implemented in fields like encrypted communication. However, a traditional Chua’s circuit has large volume, high component precision requirements and limited adjustable parameter range, which are not conducive to application. In [...] Read more.

Chua’s circuit is a well-established model for studying chaotic phenomena and is extensively implemented in fields like encrypted communication. However, a traditional Chua’s circuit has large volume, high component precision requirements and limited adjustable parameter range, which are not conducive to application. In order to solve these problems, we propose an improved implementation of Chua’s circuit on an active inductor and non-autonomous system. First, we adopt the strategy of using active inductors instead of traditional passive inductors, achieving the miniaturization of the circuit and improving the accuracy of inductance. In addition, we present the theory of substituting non-autonomous systems for classical autonomous systems to reduce the requirements for the accuracy of components and improve the robustness of the circuit. Lastly, we connect the extension resistor in parallel with Chua’s diode to optimize circuit structure, thereby increasing the range of the adjustable parameter. Based on the three improvements above, experiments have shown that the average maximum error tolerance of components of our improved design has been increased from 1.88% to 7.38% when generating a single vortex, and from 4.73% to 12.61% when generating a double vortex, compared with the traditional Chua’s circuit. The range of the adjustable parameter has been increased by 195.83% and 36.98%, respectively, when generating a single vortex and double vortex. In summary, our improved circuit is more practical than the traditional Chua’s circuit and has good application value. Full article

(This article belongs to the Topic New Developments for Circuit Design: Synthesis, Modeling, Simulation, and Applications)

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13 pages, 2910 KiB  

Open AccessArticle

Deterministic Multi-Objective Optimization of Analog Circuits

by Zihan Xu, Zhenxin Zhao and Jun Liu

Electronics 2024, 13(13), 2510; https://doi.org/10.3390/electronics13132510 - 26 Jun 2024

Viewed by 1235

Abstract

Stochastic optimization approaches benefit from random variance to produce a solution in a reasonable time frame that is good enough for solving the problem. Compared with them, deterministic optimization methods feature faster convergence rates and better reproducibility but may get stuck at a [...] Read more.

Stochastic optimization approaches benefit from random variance to produce a solution in a reasonable time frame that is good enough for solving the problem. Compared with them, deterministic optimization methods feature faster convergence rates and better reproducibility but may get stuck at a local optimum that is insufficient to solve the problem. In this paper, we propose a group-based deterministic optimization method, which can efficiently achieve comparable performance to heuristic optimization algorithms, such as particle swarm optimization. Moreover, the weighted sum method (WSM) is employed to further improve our deterministic optimization method to be multi-objective optimization, making it able to seek a balance among multiple conflicting circuit performance metrics. With a case study of three common analog circuits tested for our optimization methodology, the experimental results demonstrate that our proposed method can more efficiently reach a better estimation of the Pareto front compared to NSGA-II, a well-known multi-objective optimization approach. Full article

(This article belongs to the Topic New Developments for Circuit Design: Synthesis, Modeling, Simulation, and Applications)

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