Chips, Volume 3, Issue 4 (December 2024) – 6 articles

We have developed SWA: SoftWare for Analog design automation. Its commands can describe analog and mixed-signal (AMS) layouts and schematics to replace the graphic editor with a program reflecting the knowledge of design experts. Also, it is able to utilize variables to parameterize schematics and layouts to fulfill design needs. We programmed a 10b 1 GS/s DAC using SWA with 8.3 K lines of code, which is about 1/10 compared with conventional programs. The programmed DAC is configurable with multiple voltages and multiple resolutions from 4 to 12 bits. The DAC schematic and layout generation with DRC and LVS SWA API can be finished in about 1 min. Full article

This paper presents an advanced Controller Area Network (CAN) bus transceiver designed to enhance security using frame-level authentication with the concept of a nonphysical virtual auxiliary data channel. We describe the newly conceived transceiver security features and provide results concerning the design, implementation, fabrication and test of the transceiver to validate its functionality and robust operation in the presence of systemic error sources including Process, Voltage, and Temperature (PVT) variations. The virtual auxiliary channel integrates CAN frame authentication signatures into the primary data payload via phase modulation while also providing compatibility with existing CAN protocols, interoperability with non-enhanced systems and requiring no network or software modifications. Enhanced rail converters are designed to facilitate single-rail to dual-rail data conversion and vice versa, preserving phase information and minimizing phase errors across various nonideal effects such as frequency drift, Process, Voltage, and Temperature (PVT) variations, and cable phase mismatch. This ensures reliable data transmission and robust authentication in the presence of adversarial cyberattacks such as packet injection. The receiver recovers both the CAN frame data and the security signature, comparing the latter with an authorized signature to provide a real-time “GO/NO_GO” signal for verifying packet authenticity and without exceeding the CAN clock jitter specifications. Full article

FPGAs are popular in many fields but have yet to gain wide acceptance for accelerating HPC codes. A major cause is that whilst the growth of High-Level Synthesis (HLS), enabling the use of C or C++, has increased accessibility, without widespread algorithmic changes these tools only provide correct-by-construction rather than fast-by-construction programming. The fundamental issue is that HLS presents a Von Neumann-based execution model that is poorly suited to FPGAs, resulting in a significant disconnect between HLS’s language semantics and how experienced FPGA programmers structure dataflow algorithms to exploit hardware. We have developed the high-level language Lucent which builds on principles previously developed for programming general-purpose dataflow architectures. Using Lucent as a vehicle, in this paper we explore appropriate abstractions for developing application-specific dataflow machines on reconfigurable architectures. The result is an approach enabling fast-by-construction programming for FPGAs, delivering competitive performance against hand-optimised HLS codes whilst significantly enhancing programmer productivity. Full article

Physical side-channel attacks utilize power, electromagnetic (EM), or timing signatures from cryptographic implementations during operation to retrieve sensitive information from security-critical devices. This paper provides a comprehensive review of these potent attacks against cryptographic hardware implementations, with a particular emphasis on pre-silicon leakage assessment methodologies. We explore the intricacies of cryptographic algorithms, various side-channel attacks, and the latest mitigation techniques. Although leakage assessment techniques are widely adopted in the post-silicon phase, pre-silicon leakage assessment is an emerging field that addresses the inherent limitations of its post-silicon counterpart. We scrutinize established post-silicon techniques and provide a detailed comparative analysis of pre-silicon leakage assessment across different abstraction levels in the hardware design and verification flow. Furthermore, we categorize and discuss existing pre-silicon power and electromagnetic modeling techniques for leakage detection and mitigation that can be integrated with electronic design automation (EDA) tools to automate security assessments. Lastly, we offer insights into the future trajectory of physical side-channel leakage assessment techniques in the pre-silicon stages, highlighting the need for further research and development in this critical area of cybersecurity. Full article

The noise-shaping (NS) successive-approximation-register (SAR) is a promising analog-to-digital converter (ADC) architecture which combines the benefits of SAR and Delta-Sigma ($\mathsf{\Delta }\Sigma$) ADCs. Among the various NS-SAR approaches, the recent emerged one with capacitor stacking and buffering exhibits excellent energy efficiency. This paper presents a tutorial for the design of NS-SAR ADC with capacitor stacking and buffering. The fundamental principle of the NS-SAR loop filter is analyzed, an ADC design example is provided, and the circuit implementation details with considerations on the non-idealities and trade-offs are discussed. This paper can be used as a tutorial for designing high-resolution and high-order NS-SAR ADC. Full article

With the development of artificial intelligence and edge computing, the demand for high-performance non-volatile memory devices has been rapidly increasing. Two-dimensional materials have ultrathin bodies, ultra-flattened surfaces, and superior physics properties, and are promising to be used in non-volatile memory devices. Various kinds of advanced non-volatile memory devices with semiconductor, insulator, ferroelectric, magnetic, and phase-change two-dimensional materials have been investigated in recent years to promote performance enhancement and functionality extension. In this article, the recent advances in two-dimensional material-based non-volatile memory devices are reviewed. Performance criteria and strategies of high-performance two-dimensional non-volatile memory devices are analyzed. Two-dimensional non-volatile memory array structures and their applications in compute-in-memory architectures are discussed. Finally, a summary of this article and future outlooks of two-dimensional non-volatile memory device developments are given. Full article