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Cryptography
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Emerging Topics in Hardware Security
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Emerging Topics in Hardware Security

A special issue of Cryptography (ISSN 2410-387X). This special issue belongs to the section "Hardware Security".

Deadline for manuscript submissions: 10 December 2025 | Viewed by 8463

Special Issue Editor

Prof. Dr. Jim Plusquellic

E-Mail Website
Guest Editor
Department of Electrical and Computer Engineering, University of New Mexico, Albuquerque, NM 87131, USA
Interests: hardware security and trust and design for manufacturability
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

We welcome authors to submit research papers on topics related to hardware-based authentication; encryption and secure boot protocols for resource-constrained embedded systems, on novel side-channel analysis attacks and countermeasures, on PUFs for ICs and printed circuit boards (PCBs) capable of providing security, trust and detection of tamper, on hardware Trojan attacks, analysis, detection methods and countermeasures, on supply-chain authentication and hardware assurance methods, on hardware-based security and trust primitives for RFID (radio frequency identification); IoT; autonomous vehicles; embedded medical; and industrial control; communication and other types of critical infrastructure; and on reverse engineering techniques and countermeasures to protect ICs and IPs through obfuscation and active metering schemes.

Prof. Dr. Jim Plusquellic
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Cryptography is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • hardware security and trust
  • physical unclonable functions
  • side channel attacks and countermeasures
  • microprocessor security

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Related Special Issue

Published Papers (6 papers)

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Research

23 pages, 21467 KiB  
Article
Protecting Dynamically Obfuscated Scan Chain Architecture from DOSCrack with Trivium Pseudo-Random Number Generation
by Jiaming Wu, Olivia Dizon-Paradis, Sazadur Rahman, Damon L. Woodard and Domenic Forte
Cryptography 2025, 9(1), 6; https://doi.org/10.3390/cryptography9010006 - 14 Jan 2025
Viewed by 394
Abstract
Design-for-test/debug (DfT/D) introduces scan chain testing to increase testability and fault coverage by inserting scan flip-flops. However, these scan chains are also known to be a liability for security primitives. In previous research, the dynamically obfuscated scan chain (DOSC) was introduced to protect [...] Read more.
Design-for-test/debug (DfT/D) introduces scan chain testing to increase testability and fault coverage by inserting scan flip-flops. However, these scan chains are also known to be a liability for security primitives. In previous research, the dynamically obfuscated scan chain (DOSC) was introduced to protect logic-locking keys from scan-based attacks by obscuring test patterns and responses. In this paper, we present DOSCrack, an oracle-guided attack to de-obfuscate DOSC using symbolic execution and binary clustering, which significantly reduces the candidate seed space to a manageable quantity. Our symbolic execution engine employs scan mode simulation and satisfiability modulo theories (SMT) solvers to reduce the possible seed space, while obfuscation key clustering allows us to effectively rule out a group of seeds that share similarities. An integral component of our approach is the use of sequential equivalence checking (SEC), which aids in identifying distinct simulation patterns to differentiate between potential obfuscation keys. We experimentally applied our DOSCrack framework on four different sizes of DOSC benchmarks and compared their runtime and complexity. Finally, we propose a low-cost countermeasure to DOSCrack which incorporates a nonlinear feedback shift register (NLFSR) to increase the effort of symbolic execution modeling and serves as an effective defense against our DOSCrack framework. Our research effectively addresses a critical vulnerability in scan-chain obfuscation methodologies, offering insights into DfT/D and logic locking for both academic research and industrial applications. Our framework highlights the need to craft robust and adaptable defense mechanisms to counter evolving scan-based attacks. Full article
(This article belongs to the Special Issue Emerging Topics in Hardware Security)
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26 pages, 4448 KiB  
Article
Leveraging Neural Trojan Side-Channels for Output Exfiltration
by Vincent Meyers, Michael Hefenbrock, Dennis Gnad and Mehdi Tahoori
Cryptography 2025, 9(1), 5; https://doi.org/10.3390/cryptography9010005 - 7 Jan 2025
Viewed by 475
Abstract
Neural networks have become pivotal in advancing applications across various domains, including healthcare, finance, surveillance, and autonomous systems. To achieve low latency and high efficiency, field-programmable gate arrays (FPGAs) are increasingly being employed as accelerators for neural network inference in cloud and edge [...] Read more.
Neural networks have become pivotal in advancing applications across various domains, including healthcare, finance, surveillance, and autonomous systems. To achieve low latency and high efficiency, field-programmable gate arrays (FPGAs) are increasingly being employed as accelerators for neural network inference in cloud and edge devices. However, the rising costs and complexity of neural network training have led to the widespread use of outsourcing of training, pre-trained models, and machine learning services, raising significant concerns about security and trust. Specifically, malicious actors may embed neural Trojans within NNs, exploiting them to leak sensitive data through side-channel analysis. This paper builds upon our prior work, where we demonstrated the feasibility of embedding Trojan side-channels in neural network weights, enabling the extraction of classification results via remote power side-channel attacks. In this expanded study, we introduced a broader range of experiments to evaluate the robustness and effectiveness of this attack vector. We detail a novel training methodology that enhanced the correlation between power consumption and network output, achieving up to a 33% improvement in reconstruction accuracy over benign models. Our approach eliminates the need for additional hardware, making it stealthier and more resistant to conventional hardware Trojan detection methods. We provide comprehensive analyses of attack scenarios in both controlled and variable environmental conditions, demonstrating the scalability and adaptability of our technique across diverse neural network architectures, such as MLPs and CNNs. Additionally, we explore countermeasures and discuss their implications for the design of secure neural network accelerators. To the best of our knowledge, this work is the first to present a passive output recovery attack on neural network accelerators, without explicit trigger mechanisms. The findings emphasize the urgent need to integrate hardware-aware security protocols in the development and deployment of neural network accelerators. Full article
(This article belongs to the Special Issue Emerging Topics in Hardware Security)
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17 pages, 749 KiB  
Article
Implantable Medical Device Security
by Luigi Catuogno and Clemente Galdi
Cryptography 2024, 8(4), 53; https://doi.org/10.3390/cryptography8040053 - 15 Nov 2024
Viewed by 1261
Abstract
Implantable medical devices, or IMDs for short, are medical instruments that are placed into the human body through surgery. IMDs are typically used for treating chronic diseases. Currently available IMDs are capable of communicating using wireless channels with other devices, either in close [...] Read more.
Implantable medical devices, or IMDs for short, are medical instruments that are placed into the human body through surgery. IMDs are typically used for treating chronic diseases. Currently available IMDs are capable of communicating using wireless channels with other devices, either in close proximity or even connected to the Internet, making IMDs part of the Internet of Medical Things. This capability opens the possibility of developing a wide range of services, like remote patient data control, localization in case of emergency, or telemedicine, which can improve patients’ lifestyle. On the other hand, given the limited resources of such tiny devices, and the access to the Internet, there are numerous security issues to be considered when designing and deploying IMDs and their support infrastructures. In this paper, we highlight security problems related to Internet-connected IMDs, and survey some solutions that have been presented in the literature. Full article
(This article belongs to the Special Issue Emerging Topics in Hardware Security)
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19 pages, 1303 KiB  
Article
Natural Language Processing for Hardware Security: Case of Hardware Trojan Detection in FPGAs
by Jaya Dofe, Wafi Danesh, Vaishnavi More and Aaditya Chaudhari
Cryptography 2024, 8(3), 36; https://doi.org/10.3390/cryptography8030036 - 8 Aug 2024
Cited by 1 | Viewed by 2238
Abstract
Field-programmable gate arrays (FPGAs) offer the inherent ability to reconfigure at runtime, making them ideal for applications such as data centers, cloud computing, and edge computing. This reconfiguration, often achieved through remote access, enables efficient resource utilization but also introduces critical security vulnerabilities. [...] Read more.
Field-programmable gate arrays (FPGAs) offer the inherent ability to reconfigure at runtime, making them ideal for applications such as data centers, cloud computing, and edge computing. This reconfiguration, often achieved through remote access, enables efficient resource utilization but also introduces critical security vulnerabilities. An adversary could exploit this access to insert a dormant hardware trojan (HT) into the configuration bitstream, bypassing conventional security and verification measures. To address this security threat, we propose a supervised learning approach using deep recurrent neural networks (RNNs) for HT detection within FPGA configuration bitstreams. We explore two RNN architectures: basic RNN and long short-term memory (LSTM) networks. Our proposed method analyzes bitstream patterns, to identify anomalies indicative of malicious modifications. We evaluated the effectiveness on ISCAS 85 benchmark circuits of varying sizes and topologies, implemented on a Xilinx Artix-7 FPGA. The experimental results revealed that the basic RNN model showed lower accuracy in identifying HT-compromised bitstreams for most circuits. In contrast, the LSTM model achieved a significantly higher average accuracy of 93.5%. These results demonstrate that the LSTM model is more successful for HT detection in FPGA bitstreams. This research paves the way for using RNN architectures for HT detection in FPGAs, eliminating the need for time-consuming and resource-intensive reverse engineering or performance-degrading bitstream conversions. Full article
(This article belongs to the Special Issue Emerging Topics in Hardware Security)
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18 pages, 2962 KiB  
Article
A Novel Two-Level Protection Scheme against Hardware Trojans on a Reconfigurable CNN Accelerator
by Zichu Liu, Jia Hou, Jianfei Wang and Chen Yang
Cryptography 2024, 8(3), 34; https://doi.org/10.3390/cryptography8030034 - 4 Aug 2024
Viewed by 1868
Abstract
With the boom in artificial intelligence (AI), numerous reconfigurable convolution neural network (CNN) accelerators have emerged within both industry and academia, aiming to enhance AI computing capabilities. However, this rapid landscape has also witnessed a rise in hardware Trojan attacks targeted at CNN [...] Read more.
With the boom in artificial intelligence (AI), numerous reconfigurable convolution neural network (CNN) accelerators have emerged within both industry and academia, aiming to enhance AI computing capabilities. However, this rapid landscape has also witnessed a rise in hardware Trojan attacks targeted at CNN accelerators, thereby posing substantial threats to the reliability and security of these reconfigurable systems. Despite this escalating concern, there exists a scarcity of security protection schemes explicitly tailored to counteract hardware Trojans embedded in reconfigurable CNN accelerators, and those that do exist exhibit notable deficiencies. Addressing these gaps, this paper introduces a dedicated security scheme designed to mitigate the vulnerabilities associated with hardware Trojans implanted in reconfigurable CNN accelerators. The proposed security protection scheme operates at two distinct levels: the first level is geared towards preventing the triggering of the hardware Trojan, while the second level focuses on detecting the presence of a hardware Trojan post-triggering and subsequently neutralizing its potential harm. Through experimental evaluation, our results demonstrate that this two-level protection scheme is capable of mitigating at least 99.88% of the harm cause by three different types of hardware Trojan (i.e., Trojan within RI, MAC and ReLU) within reconfigurable CNN accelerators. Furthermore, this scheme can prevent hardware Trojans from triggering whose trigger signal is derived from a processing element (PE). Notably, the proposed scheme is implemented and validated on a Xilinx Zynq XC7Z100 platform. Full article
(This article belongs to the Special Issue Emerging Topics in Hardware Security)
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15 pages, 1401 KiB  
Article
Entropy Analysis of FPGA Interconnect and Switch Matrices for Physical Unclonable Functions
by Jenilee Jao, Ian Wilcox, Jim Plusquellic, Biliana Paskaleva and Pavel Bochev
Cryptography 2024, 8(3), 32; https://doi.org/10.3390/cryptography8030032 - 15 Jul 2024
Viewed by 1305
Abstract
Random variations in microelectronic circuit structures represent the source of entropy for physical unclonable functions (PUFs). In this paper, we investigate delay variations that occur through the routing network and switch matrices of a field-programmable gate array (FPGA). The delay variations are isolated [...] Read more.
Random variations in microelectronic circuit structures represent the source of entropy for physical unclonable functions (PUFs). In this paper, we investigate delay variations that occur through the routing network and switch matrices of a field-programmable gate array (FPGA). The delay variations are isolated from other components of the programmable logic, e.g., look-up tables (LUTs), flip-flops (FFs), etc., using a feature of Xilinx FPGAs called dynamic partial reconfiguration (DPR). A set of partial designs is created to fix the placement of a time-to-digital converter (TDC) and supporting infrastructure to enable the path delays through the target interconnect and switch matrices to be extracted by subtracting out common-mode delay components. Delay variations are analyzed in the different levels of routing resources available within FPGAs, i.e., local routing and across-chip routing. Data are collected from a set of Xilinx Zynq 7010 devices, and a statistical analysis of within-die variations in delay through a set of the randomly-generated and hand-crafted interconnects is presented. Full article
(This article belongs to the Special Issue Emerging Topics in Hardware Security)
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