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JLPEA
Special Issues
Industrial Aspects of Low Power Design Recent Trends and Methods
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Industrial Aspects of Low Power Design Recent Trends and Methods

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (15 August 2011) | Viewed by 52322

Special Issue Editors

Dr. Arkadiy Morgenshtein

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Guest Editor
Core CAD Technologies Group, Intel Corporation, Haifa 31015, Israel
Interests: VLSI design; low-power circuits and power optimization
Dr. Israel A. Wagner

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Guest Editor
Circuit Technologies Group, IBM Haifa Research Lab, MATAM, Haifa 31905, Israel
Interests: VLSI Design
Prof. Dr. Yakov Roizin

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Guest Editor
TowerJazz Semiconductors, Migdal HaEmek, Israel
Interests: non-volatile memories and sensors for embedded CMOS technologies
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

The Journal of Low Power Electronics and Applications (JLPEA) is seeking original contributions for the forthcoming issue on Industrial Aspects of Low Power Design Recent Trends and Methods. This issue is scheduled for publication in September, 2011. The aim of this issue is to present recent advances and trends of low power methodologies and applications in industry.

Dr. Arkadiy Morgenshtein
Dr. Israel A. Wagner
Prof. Dr. Yakov Roizin
Guest Editors

Keywords

  • fabrication process advances for low power
  • emerging technologies and devices for low power
  • low power circuits and systems design
  • energy efficient processors and DSPs
  • verification for low power
  • EDA tools for power optimization and estimation, recent advances in CAD low-power methodologies
  • low power memories and arrays
  • low power algorithms and architectures
  • applications - case studies of specific low power applications, power-saving enabling solutions

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Published Papers (5 papers)

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Research

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5588 KiB  
Article
Multi-Functional Micro Projection Device as Screen Substitute for Low Power Consumption Computing
by Yuval Kapellner and Zeev Zalevsky
J. Low Power Electron. Appl. 2012, 2(1), 79-97; https://doi.org/10.3390/jlpea2010079 - 5 Mar 2012
Cited by 1 | Viewed by 8128
Abstract
One of the major power consuming components in a computer is its display unit. On average the screen consumes ten times more power than the DSP processor itself. Thus, reducing the power consumption should be one of the most important tasks in the [...] Read more.
One of the major power consuming components in a computer is its display unit. On average the screen consumes ten times more power than the DSP processor itself. Thus, reducing the power consumption should be one of the most important tasks in the development of low power consumption computing systems. In this paper we present one possible solution involving micro projection device based upon lasers and a digital light processing (DLP) matrix which is a matrix of electrically controllable mirrors capable of translating electrical signal to a time varying projected image. It can serve to substitute a screen and consume ten times less power than a conventional screen. The described device is a multifunctional highly efficient customized DLP light engine being capable of serving as an image projector and simultaneously to support range and topography estimation measurements. Full article
(This article belongs to the Special Issue Industrial Aspects of Low Power Design Recent Trends and Methods)
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573 KiB  
Article
Short-Circuit Power Reduction by Using High-Threshold Transistors
by Arkadiy Morgenshtein
J. Low Power Electron. Appl. 2012, 2(1), 69-78; https://doi.org/10.3390/jlpea2010069 - 1 Mar 2012
Cited by 13 | Viewed by 10366
Abstract
In this brief paper, the dependency of short-circuit power on threshold voltage is analyzed and utilized for short circuit (SC) power reduction in multi-threshold (MTCMOS) processes. Analytical expressions are developed for estimation of the change of ratio between short-circuit power and dynamic power [...] Read more.
In this brief paper, the dependency of short-circuit power on threshold voltage is analyzed and utilized for short circuit (SC) power reduction in multi-threshold (MTCMOS) processes. Analytical expressions are developed for estimation of the change of ratio between short-circuit power and dynamic power (PSC/Pdyn) while changing the design process. The analysis shows that the PSC/Pdyn ratio can increase significantly if the VT/Vdd ratio in new process decreases. An analytical expression is also derived for estimation of potential SC power reduction in MTCMOS processes by replacing low-VT transistors by high-VT devices in the same process. The proposed technique allows significant reduction of SC power without the need for process shift. The simulation results show good correlation with the analytical estimation at cell level, while demonstrating an average SC power saving of 36%. The performance impact is also validated, showing that timing degradation is minor and controllable. The proposed optimization technique is applicable to any multi-threshold process. The technique is simple for implementation, and can be easily integrated in the existing optimization tools. Full article
(This article belongs to the Special Issue Industrial Aspects of Low Power Design Recent Trends and Methods)
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251 KiB  
Article
Low Power Testing—What Can Commercial Design-for-Test Tools Provide?
by Xijiang Lin
J. Low Power Electron. Appl. 2011, 1(3), 357-372; https://doi.org/10.3390/jlpea1030357 - 9 Dec 2011
Cited by 3 | Viewed by 7643
Abstract
Minimizing power consumption during functional operation and during manufacturing tests has become one of the dominant requirements for the semiconductor designs in the past decade. From commercial design-for-test (DFT) tools’ point of view, this paper describes how DFT tools can help to achieve [...] Read more.
Minimizing power consumption during functional operation and during manufacturing tests has become one of the dominant requirements for the semiconductor designs in the past decade. From commercial design-for-test (DFT) tools’ point of view, this paper describes how DFT tools can help to achieve comprehensive testing of low power designs and reduce test power consumption during test application. Full article
(This article belongs to the Special Issue Industrial Aspects of Low Power Design Recent Trends and Methods)
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Review

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2808 KiB  
Review
CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations
by Eitan N. Shauly
J. Low Power Electron. Appl. 2012, 2(1), 1-29; https://doi.org/10.3390/jlpea2010001 - 27 Jan 2012
Cited by 40 | Viewed by 18703
Abstract
Power reduction in CMOS platforms is essential for any application technology. This is a direct result of both lateral scaling—smaller features at higher density, and vertical scaling—shallower junctions and thinner layers. For achieving this power reduction, solutions based on process-device and process-integration improvements, [...] Read more.
Power reduction in CMOS platforms is essential for any application technology. This is a direct result of both lateral scaling—smaller features at higher density, and vertical scaling—shallower junctions and thinner layers. For achieving this power reduction, solutions based on process-device and process-integration improvements, on careful layout modification as well as on circuit design are in use. However, the drawbacks of these solutions, in terms of greater manufacturing complexity (and higher cost) and speed degradation, call for “optimized” solutions. This paper reviews the issues associated with transistor scaling and related solutions for leakage and power reduction in terms of topological design rules and layout optimization for digital and analog transistors. For standard cells and SRAMs cells, leakage aware layout optimization techniques considering transistor configuration, stressors, line-edge-roughness and more are presented. Finally, different techniques for leakage and power reduction at the circuit level are discussed. Full article
(This article belongs to the Special Issue Industrial Aspects of Low Power Design Recent Trends and Methods)
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Other

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3262 KiB  
Technical Note
Quartz Resonator Based, 0.12 μW, 32768 Hz Oscillator with ±100 ppm Frequency Accuracy
by Oleg Nizhnik, Kohei Higuchi and Kazusuke Maenaka
J. Low Power Electron. Appl. 2011, 1(2), 327-333; https://doi.org/10.3390/jlpea1020327 - 20 Sep 2011
Cited by 5 | Viewed by 6760
Abstract
A 0.12 μW power dissipation quartz oscillator with 32,768 Hz frequency was designed and fabricated. Stability of the oscillator versus power supply and temperature variations was measured. The design is suitable for the role of the RTC (real-time clock) or main system clock [...] Read more.
A 0.12 μW power dissipation quartz oscillator with 32,768 Hz frequency was designed and fabricated. Stability of the oscillator versus power supply and temperature variations was measured. The design is suitable for the role of the RTC (real-time clock) or main system clock in low-power, battery-powered and energy harvesting systems. Full article
(This article belongs to the Special Issue Industrial Aspects of Low Power Design Recent Trends and Methods)
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