Search for Articles:
Title / Keyword
Author / Affiliation / Email
Journal
Article Type
 
 
Advanced Search
 
Section
Special Issue
Volume
Issue
Number
Page
 
5.8
3.1
Journals
Materials
Special Issues
Nanostructure-Based Memory Devices
materials-logo
Submit to Materials Review for Materials Propose a Special Issue

Journal Menu

► Journal Menu

Journal Browser

► Journal Browser
share announcement

Nanostructure-Based Memory Devices

A special issue of Materials (ISSN 1996-1944). This special issue belongs to the section "Electronic Materials".

Deadline for manuscript submissions: closed (31 December 2020) | Viewed by 9085

Special Issue Editor

Dr. Panagiotis Dimitrakis

E-Mail Website
Guest Editor
Institute of Nanoscience and Nanotechnology, NCSR Demokritos, 15341 Aghia Paraskevi, Greece
Interests: nonvolatile memories; charge-trapping memories; resistive memories; nanowire-based devices; graphene and 2D devices; memristors; quantum devices

Special Issue Information

Dear Colleagues,

Electronic memory devices have been leading the microelectronics technology for years, having a critical and crucial role in the current computing machines. Today, electronic memory is found in any device we use in our everyday life, starting from coffee and white machines and ending to cars and spacecrafts. Thus, memories affect every facet of our social life, our health, our security, our transportation, our environment, etc.

Since we are living in the period of nanotechnology and nanoelectronics blossom, the size of the electronic devices has shrunk, allowing nanostructured memories to play a significant role. Furthermore, the new nanofabrication techniques and tools allow the utilization of nanoparticles, single molecules, and DNA as materials suitable for information storage. Nanotechnology has revealed new features of materials and devices: the physical and electronic properties of nanoparticles are different from those of bulk materials, and the operation of nanowire transistors becomes more complicated than that of the planar elements. The new nanomaterials and nanodevices developed recently, such as memristors, inspire scientists to think of new computing paradigms that are not compatible with the standard von Neumann computer architecture. The most well-known paradigm is the in-memory computing or logic-in-memory computing. The field of nanostructured-based memories is advancing rapidly, laying the foundations for an age closer to the “internet of things”, artificial intelligence and neuromorphic computing.

High-quality papers on all the above-mentioned types of memory, topics, and open issues should be written and collected in a special volume. This is the aim of this Special Issue in Materials. It is my pleasure to invite you to submit a manuscript for this Special Issue. Communications, full, and review papers are all welcome.

Dr. Panagiotis Dimitrakis
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Materials is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • nanowire-based memories
  • nanoparticle-based memories
  • graphene and 2D materials memories
  • nanocrossbar memories
  • nanoscale resistive switching memories
  • nanoscale MRAM and FRAM
  • molecular memories
  • hybrid silicon/polymer memories
  • vertical and 3D memories

Benefits of Publishing in a Special Issue

  • Ease of navigation: Grouping papers by topic helps scholars navigate broad scope journals more efficiently.
  • Greater discoverability: Special Issues support the reach and impact of scientific research. Articles in Special Issues are more discoverable and cited more frequently.
  • Expansion of research network: Special Issues facilitate connections among authors, fostering scientific collaborations.
  • External promotion: Articles in Special Issues are often promoted through the journal's social media, increasing their visibility.
  • e-Book format: Special Issues with more than 10 articles can be published as dedicated e-books, ensuring wide and rapid dissemination.

Further information on MDPI's Special Issue polices can be found here.

Published Papers (3 papers)

Download All Papers
Order results
Result details
Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:

Research

15 pages, 773 KiB  
Article
Quantum Memristors in Frequency-Entangled Optical Fields
by Tasio Gonzalez-Raya, Joseph M. Lukens, Lucas C. Céleri and Mikel Sanz
Materials 2020, 13(4), 864; https://doi.org/10.3390/ma13040864 - 14 Feb 2020
Cited by 13 | Viewed by 3707
Abstract
A quantum memristor is a passive resistive circuit element with memory, engineered in a given quantum platform. It can be represented by a quantum system coupled to a dissipative environment, in which a system–bath coupling is mediated through a weak measurement scheme and [...] Read more.
A quantum memristor is a passive resistive circuit element with memory, engineered in a given quantum platform. It can be represented by a quantum system coupled to a dissipative environment, in which a system–bath coupling is mediated through a weak measurement scheme and classical feedback on the system. In quantum photonics, such a device can be designed from a beam splitter with tunable reflectivity, which is modified depending on the results of measurements in one of the outgoing beams. Here, we show that a similar implementation can be achieved with frequency-entangled optical fields and a frequency mixer that, working similarly to a beam splitter, produces state superpositions. We show that the characteristic hysteretic behavior of memristors can be reproduced when analyzing the response of the system with respect to the control, for different experimentally attainable states. Since memory effects in memristors can be exploited for classical and neuromorphic computation, the results presented in this work could be a building block for constructing quantum neural networks in quantum photonics, when scaling up. Full article
(This article belongs to the Special Issue Nanostructure-Based Memory Devices)
►▼ Show Figures

Figure 1

12 pages, 2464 KiB  
Article
Impact of Line Edge Roughness on ReRAM Uniformity and Scaling
by Vassilios Constantoudis, George Papavieros, Panagiotis Karakolis, Ali Khiat, Themistoklis Prodromakis and Panagiotis Dimitrakis
Materials 2019, 12(23), 3972; https://doi.org/10.3390/ma12233972 - 30 Nov 2019
Cited by 2 | Viewed by 2514
Abstract
We investigate the effects of Line Edge Roughness (LER) of electrode lines on the uniformity of Resistive Random Access Memory (ReRAM) device areas in cross-point architectures. To this end, a modeling approach is implemented based on the generation of 2D cross-point patterns with [...] Read more.
We investigate the effects of Line Edge Roughness (LER) of electrode lines on the uniformity of Resistive Random Access Memory (ReRAM) device areas in cross-point architectures. To this end, a modeling approach is implemented based on the generation of 2D cross-point patterns with predefined and controlled LER and pattern parameters. The aim is to evaluate the significance of LER in the variability of device areas and their performances and to pinpoint the most critical parameters and conditions. It is found that conventional LER parameters may induce >10% area variability depending on pattern dimensions and cross edge/line correlations. Increased edge correlations in lines such as those that appeared in Double Patterning and Directed Self-assembly Lithography techniques lead to reduced area variability. Finally, a theoretical formula is derived to explain the numerical dependencies of the modeling method. Full article
(This article belongs to the Special Issue Nanostructure-Based Memory Devices)
►▼ Show Figures

Figure 1

7 pages, 1628 KiB  
Article
Fabrication of Sn@Al2O3 Core-shell Nanoparticles for Stable Nonvolatile Memory Applications
by Jong-Hwan Yoon
Materials 2019, 12(19), 3111; https://doi.org/10.3390/ma12193111 - 24 Sep 2019
Cited by 3 | Viewed by 2230
Abstract
Sn@Al2O3 core-shell nanoparticles (NPs) with narrow spatial distributions were synthesized in silicon dioxide (SiO2). These Sn@Al2O3 core-shell NPs were self-assembled by thermally annealing a stacked structure of SiOx/Al/Sn/Al/SiOx sandwiched between two SiO [...] Read more.
Sn@Al2O3 core-shell nanoparticles (NPs) with narrow spatial distributions were synthesized in silicon dioxide (SiO2). These Sn@Al2O3 core-shell NPs were self-assembled by thermally annealing a stacked structure of SiOx/Al/Sn/Al/SiOx sandwiched between two SiO2 layers at low temperatures. The resultant structure provided a well-defined Sn NP floating gate with a SiO2/Al2O3 dielectric stacked tunneling barrier. Capacitance-voltage (C-V) measurements on a metal-oxide-semiconductor (MOS) capacitor with a Sn@Al2O3 core-shell NP floating gate confirmed an ultra-high charge storage stability, and the multiple trapping of electron at the NPs, as expected from low-k/high-k dielectric stacked tunneling layers and metallic NPs, respectively. Full article
(This article belongs to the Special Issue Nanostructure-Based Memory Devices)
►▼ Show Figures

Figure 1

Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:
 
Displaying articles 1-3
Back to TopTop