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3 pages, 141 KiB

Open AccessEditorial

Editorial for the Special Issue on Emerging Memory and Computing Devices in the Era of Intelligent Machines

by Pedram Khalili Amiri

Micromachines 2020, 11(1), 73; https://doi.org/10.3390/mi11010073 - 9 Jan 2020

Viewed by 1727

Abstract

Computing systems are undergoing a transformation from logic-centric toward memory-centric architectures, where overall performance and energy efficiency at the system level are determined by the density, bandwidth, latency, and energy efficiency of the memory, rather than the logic sub-system [...] Full article

(This article belongs to the Special Issue Emerging Memory and Computing Devices in the Era of Intelligent Machines)

Research

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11 pages, 1650 KiB

Open AccessArticle

Compensating Circuit to Reduce the Impact of Wire Resistance in a Memristor Crossbar-Based Perceptron Neural Network

by Son Ngoc Truong

Micromachines 2019, 10(10), 671; https://doi.org/10.3390/mi10100671 - 2 Oct 2019

Cited by 9 | Viewed by 2608

Abstract

Wire resistance in metal wire is one of the factors that degrade the performance of memristor crossbar circuits. In this paper, an analysis of the impact of wire resistance in a memristor crossbar is performed and a compensating circuit is proposed to reduce [...] Read more.

Wire resistance in metal wire is one of the factors that degrade the performance of memristor crossbar circuits. In this paper, an analysis of the impact of wire resistance in a memristor crossbar is performed and a compensating circuit is proposed to reduce the impact of wire resistance in a memristor crossbar-based perceptron neural network. The goal of the analysis is to figure out how wire resistance influences the output voltage of a memristor crossbar. It emerges that the wire resistance on horizontal lines causes the neuron’s output voltage to vary more than the wire resistance on vertical lines. More interesting, the voltage variation caused by wire resistance on horizontal lines increases proportionally to the length of metal wire. The first column has small voltage variation whereas the last column has large voltage variation. In addition, two adjacent columns have almost the same amount of voltage variation. Under these observations, a memristor crossbar-based perceptron neural network with compensating circuit is proposed. The neuron’s outputs of two columns are put into a subtractor circuit to eliminate the voltage variation caused by the wire resistance. The proposed memristor crossbar-based perceptron neural network is trained to recognize the 26 characters. The proposed memristor crossbar shows better recognition rate compared to the previous work when wire resistance is taken into account. The proposed memristor crossbar circuit can maintain the recognition rate as high as 100% when wire resistance is as high as 2.5 Ω. By contrast, the recognition rate of the memristor crossbar without the compensating circuit decreases by 1%, 5%, and 19% when wire resistance is set to be 1.5, 2.0, and 2.5 Ω, respectively. Full article

(This article belongs to the Special Issue Emerging Memory and Computing Devices in the Era of Intelligent Machines)

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15 pages, 4160 KiB

Open AccessArticle

Comparison of the Electrical Response of Cu and Ag Ion-Conducting SDC Memristors Over the Temperature Range 6 K to 300 K

by Kolton Drake, Tonglin Lu, Md. Kamrul H. Majumdar and Kristy A. Campbell

Micromachines 2019, 10(10), 663; https://doi.org/10.3390/mi10100663 - 30 Sep 2019

Cited by 9 | Viewed by 3534

Abstract

Electrical performance of self-directed channel (SDC) ion-conducting memristors which use Ag and Cu as the mobile ion source are compared over the temperature range of 6 K to 300 K. The Cu-based SDC memristors operate at temperatures as low as 6 K, whereas [...] Read more.

Electrical performance of self-directed channel (SDC) ion-conducting memristors which use Ag and Cu as the mobile ion source are compared over the temperature range of 6 K to 300 K. The Cu-based SDC memristors operate at temperatures as low as 6 K, whereas Ag-based SDC memristors are damaged if operated below 125 K. It is also observed that Cu reversibly diffuses into the active Ge₂Se₃ layer during normal device shelf-life, thus changing the state of a Cu-based memristor over time. This was not observed for the Ag-based SDC devices. The response of each device type to sinusoidal excitation is provided and shows that the Cu-based devices exhibit hysteresis lobe collapse at lower frequencies than the Ag-based devices. In addition, the pulsed response of the device types is presented. Full article

(This article belongs to the Special Issue Emerging Memory and Computing Devices in the Era of Intelligent Machines)

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9 pages, 2619 KiB

Open AccessArticle

A Floating Gate Memory with U-Shape Recessed Channel for Neuromorphic Computing and MCU Applications

by Lu-Rong Gan, Ya-Rong Wang, Lin Chen, Hao Zhu and Qing-Qing Sun

Micromachines 2019, 10(9), 558; https://doi.org/10.3390/mi10090558 - 23 Aug 2019

Cited by 4 | Viewed by 3701

Abstract

We have simulated a U-shape recessed channel floating gate memory by Sentaurus TCAD tools. Since the floating gate (FG) is vertically placed between source (S) and drain (D), and control gate (CG) and HfO₂ high-k dielectric extend above source and drain, the [...] Read more.

We have simulated a U-shape recessed channel floating gate memory by Sentaurus TCAD tools. Since the floating gate (FG) is vertically placed between source (S) and drain (D), and control gate (CG) and HfO₂ high-k dielectric extend above source and drain, the integrated density can be well improved, while the erasing and programming speed of the device are respectively decreased to 75 ns and 50 ns. In addition, comprehensive synaptic abilities including long-term potentiation (LTP) and long-term depression (LTD) are demonstrated in our U-shape recessed channel FG memory, highly resembling the biological synapses. These simulation results show that our device has the potential to be well used as embedded memory in neuromorphic computing and MCU (Micro Controller Unit) applications. Full article

(This article belongs to the Special Issue Emerging Memory and Computing Devices in the Era of Intelligent Machines)

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16 pages, 3860 KiB

Open AccessArticle

A RISC-V Processor with Area-Efficient Memristor-Based In-Memory Computing for Hash Algorithm in Blockchain Applications

by Xiaoyong Xue, Chenzedai Wang, Wenjun Liu, Hangbing Lv, Mingyu Wang and Xiaoyang Zeng

Micromachines 2019, 10(8), 541; https://doi.org/10.3390/mi10080541 - 16 Aug 2019

Cited by 11 | Viewed by 5990

Abstract

Blockchain technology is increasingly being used in Internet of things (IoT) devices for information security and data integrity. However, it is challenging to implement complex hash algorithms with limited resources in IoT devices owing to large energy consumption and a long processing time. [...] Read more.

Blockchain technology is increasingly being used in Internet of things (IoT) devices for information security and data integrity. However, it is challenging to implement complex hash algorithms with limited resources in IoT devices owing to large energy consumption and a long processing time. This paper proposes a RISC-V processor with memristor-based in-memory computing (IMC) for blockchain technology in IoT applications. The IMC-adapted instructions were designed for the Keccak hash algorithm by virtue of the extendibility of the RISC-V instruction set architecture (ISA). Then, a RISC-V processor with area-efficient memristor-based IMC was developed based on an open-source core for IoT applications, Hummingbird E200. The general compiling policy with the data allocation method is also disclosed for the IMC implementation of the Keccak hash algorithm. An evaluation shows that >70% improvements in both performance and energy saving were achieved with limited area overhead after introducing IMC in the RISC-V processor. Full article

(This article belongs to the Special Issue Emerging Memory and Computing Devices in the Era of Intelligent Machines)

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16 pages, 2174 KiB

Open AccessArticle

An Ultra-Area-Efficient 1024-Point In-Memory FFT Processor

by Hasan Erdem Yantir, Wenzhe Guo, Ahmed M. Eltawil, Fadi J. Kurdahi and Khaled Nabil Salama

Micromachines 2019, 10(8), 509; https://doi.org/10.3390/mi10080509 - 31 Jul 2019

Cited by 17 | Viewed by 4389

Abstract

Current computation architectures rely on more processor-centric design principles. On the other hand, the inevitable increase in the amount of data that applications need forces researchers to design novel processor architectures that are more data-centric. By following this principle, this study proposes an [...] Read more.

Current computation architectures rely on more processor-centric design principles. On the other hand, the inevitable increase in the amount of data that applications need forces researchers to design novel processor architectures that are more data-centric. By following this principle, this study proposes an area-efficient Fast Fourier Transform (FFT) processor through in-memory computing. The proposed architecture occupies the smallest footprint of around 0.1

{mm}^{2}

inside its class together with acceptable power efficiency. According to the results, the processor exhibits the highest area efficiency (

FFT / s / area

) among the existing FFT processors in the current literature. Full article

(This article belongs to the Special Issue Emerging Memory and Computing Devices in the Era of Intelligent Machines)

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13 pages, 13214 KiB

Open AccessArticle

Speeding Up the Write Operation for Multi-Level Cell Phase Change Memory with Programmable Ramp-Down Current Pulses

by Chenchen Xie, Xi Li, Houpeng Chen, Yang Li, Yuanguang Liu, Qian Wang, Kun Ren and Zhitang Song

Micromachines 2019, 10(7), 461; https://doi.org/10.3390/mi10070461 - 8 Jul 2019

Cited by 6 | Viewed by 3953

Abstract

Multi-level cell (MLC) phase change memory (PCM) can not only effectively multiply the memory capacity while maintaining the cell area, but also has infinite potential in the application of the artificial neural network. The write and verify scheme is usually adopted to reduce [...] Read more.

Multi-level cell (MLC) phase change memory (PCM) can not only effectively multiply the memory capacity while maintaining the cell area, but also has infinite potential in the application of the artificial neural network. The write and verify scheme is usually adopted to reduce the impact of device-to-device variability at the expense of a greater operation time and more power consumption. This paper proposes a novel write operation for multi-level cell phase change memory: Programmable ramp-down current pulses are utilized to program the RESET initialized memory cells to the expected resistance levels. In addition, a fully differential read circuit with an optional reference current source is employed to complete the readout operation. Eventually, a 2-bit/cell phase change memory chip is presented with a more efficient write operation of a single current pulse and a read access time of 65 ns. Some experiments are implemented to demonstrate the resistance distribution and the drift. Full article

(This article belongs to the Special Issue Emerging Memory and Computing Devices in the Era of Intelligent Machines)

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12 pages, 2029 KiB

Open AccessArticle

Effect of Annealing Temperature for Ni/AlO_x/Pt RRAM Devices Fabricated with Solution-Based Dielectric

by Zongjie Shen, Yanfei Qi, Ivona Z. Mitrovic, Cezhou Zhao, Steve Hall, Li Yang, Tian Luo, Yanbo Huang and Chun Zhao

Micromachines 2019, 10(7), 446; https://doi.org/10.3390/mi10070446 - 2 Jul 2019

Cited by 37 | Viewed by 5565

Abstract

Resistive random access memory (RRAM) devices with Ni/AlO_x/Pt-structure were manufactured by deposition of a solution-based aluminum oxide (AlO_x) dielectric layer which was subsequently annealed at temperatures from 200 °C to 300 °C, in increments of 25 °C. The devices [...] Read more.

Resistive random access memory (RRAM) devices with Ni/AlO_x/Pt-structure were manufactured by deposition of a solution-based aluminum oxide (AlO_x) dielectric layer which was subsequently annealed at temperatures from 200 °C to 300 °C, in increments of 25 °C. The devices displayed typical bipolar resistive switching characteristics. Investigations were carried out on the effect of different annealing temperatures for associated RRAM devices to show that performance was correlated with changes of hydroxyl group concentration in the AlO_x thin films. The annealing temperature of 250 °C was found to be optimal for the dielectric layer, exhibiting superior performance of the RRAM devices with the lowest operation voltage (<1.5 V), the highest ON/OFF ratio (>10⁴), the narrowest resistance distribution, the longest retention time (>10⁴ s) and the most endurance cycles (>150). Full article

(This article belongs to the Special Issue Emerging Memory and Computing Devices in the Era of Intelligent Machines)

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10 pages, 440 KiB

Open AccessArticle

Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop

by Jaeyoung Park and Young Uk Yim

Micromachines 2019, 10(6), 411; https://doi.org/10.3390/mi10060411 - 20 Jun 2019

Cited by 6 | Viewed by 3418 | Correction

Abstract

An area-efficient non-volatile flip flop (NVFF) is proposed. Two minimum-sized Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and two magnetic tunnel junction (MTJ) devices are added on top of a conventional D flip-flop for temporary storage during the power-down. An area overhead of the temporary storage [...] Read more.

An area-efficient non-volatile flip flop (NVFF) is proposed. Two minimum-sized Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and two magnetic tunnel junction (MTJ) devices are added on top of a conventional D flip-flop for temporary storage during the power-down. An area overhead of the temporary storage is minimized by reusing a part of the D flip-flop and an energy overhead is reduced by a current-reuse technique. In addition, two optimization strategies of the use of the proposed NVFF are proposed: (1) A module-based placement in a design phase for minimizing the area overhead; and (2) a dynamic write pulse modulation at runtime for reducing the energy overhead. We evaluated the proposed NVFF circuit using a compact MTJ model targeting an implementation in a 10 nm technology node. Results indicate that area overhead is

6.9 %

normalized to the conventional flip flop. Compared to the best previously known NVFFs, the proposed circuit succeeded in reducing the area by

4.1 \times

and the energy by

1.5 \times

. The proposed placement strategy of the NVFF shows an improvement of nearly a factor of 2–18 in terms of area and energy, and the pulse duration modulation provides a further energy reduction depending on fault tolerance of programs. Full article

(This article belongs to the Special Issue Emerging Memory and Computing Devices in the Era of Intelligent Machines)

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11 pages, 1887 KiB

Open AccessArticle

Memristor Neural Network Training with Clock Synchronous Neuromorphic System

by Sumin Jo, Wookyung Sun, Bokyung Kim, Sunhee Kim, Junhee Park and Hyungsoon Shin

Micromachines 2019, 10(6), 384; https://doi.org/10.3390/mi10060384 - 8 Jun 2019

Cited by 12 | Viewed by 3875

Abstract

Memristor devices are considered to have the potential to implement unsupervised learning, especially spike timing-dependent plasticity (STDP), in the field of neuromorphic hardware research. In this study, a neuromorphic hardware system for multilayer unsupervised learning was designed, and unsupervised learning was performed with [...] Read more.

Memristor devices are considered to have the potential to implement unsupervised learning, especially spike timing-dependent plasticity (STDP), in the field of neuromorphic hardware research. In this study, a neuromorphic hardware system for multilayer unsupervised learning was designed, and unsupervised learning was performed with a memristor neural network. We showed that the nonlinear characteristic memristor neural network can be trained by unsupervised learning only with the correlation between inputs and outputs. Moreover, a method to train nonlinear memristor devices in a supervised manner, named guide training, was devised. Memristor devices have a nonlinear characteristic, which makes implementing machine learning algorithms, such as backpropagation, difficult. The guide-training algorithm devised in this paper updates the synaptic weights by only using the correlations between inputs and outputs, and therefore, neither complex mathematical formulas nor computations are required during the training. Thus, it is considered appropriate to train a nonlinear memristor neural network. All training and inference simulations were performed using the designed neuromorphic hardware system. With the system and memristor neural network, the image classification was successfully done using both the Hebbian unsupervised training and guide supervised training methods. Full article

(This article belongs to the Special Issue Emerging Memory and Computing Devices in the Era of Intelligent Machines)

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12 pages, 2467 KiB

Open AccessArticle

Tight Evaluation of Real-Time Task Schedulability for Processor’s DVS and Nonvolatile Memory Allocation

by Sunhwa A. Nam, Kyungwoon Cho and Hyokyung Bahn

Micromachines 2019, 10(6), 371; https://doi.org/10.3390/mi10060371 - 3 Jun 2019

Cited by 8 | Viewed by 2768

Abstract

A power-saving approach for real-time systems that combines processor voltage scaling and task placement in hybrid memory is presented. The proposed approach incorporates the task’s memory placement problem between the DRAM (dynamic random access memory) and NVRAM (nonvolatile random access memory) into the [...] Read more.

A power-saving approach for real-time systems that combines processor voltage scaling and task placement in hybrid memory is presented. The proposed approach incorporates the task’s memory placement problem between the DRAM (dynamic random access memory) and NVRAM (nonvolatile random access memory) into the task model of the processor’s voltage scaling and adopts power-saving techniques for processor and memory selectively without violating the deadline constraints. Unlike previous work, our model tightly evaluates the worst-case execution time of a task, considering the time delay that may overlap between the processor and memory, thereby reducing the power consumption of real-time systems by 18–88%. Full article

(This article belongs to the Special Issue Emerging Memory and Computing Devices in the Era of Intelligent Machines)

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10 pages, 2681 KiB

Open AccessArticle

Resistance Switching Statistics and Mechanisms of Pt Dispersed Silicon Oxide-Based Memristors

by Xiaojuan Lian, Xinyi Shen, Liqun Lu, Nan He, Xiang Wan, Subhranu Samanta and Yi Tong

Micromachines 2019, 10(6), 369; https://doi.org/10.3390/mi10060369 - 1 Jun 2019

Cited by 7 | Viewed by 4227

Abstract

Silicon oxide-based memristors have been extensively studied due to their compatibility with the dominant silicon complementary metal–oxide–semiconductor (CMOS) fabrication technology. However, the variability of resistance switching (RS) parameters is one of the major challenges for commercialization applications. Owing to the filamentary nature of [...] Read more.

Silicon oxide-based memristors have been extensively studied due to their compatibility with the dominant silicon complementary metal–oxide–semiconductor (CMOS) fabrication technology. However, the variability of resistance switching (RS) parameters is one of the major challenges for commercialization applications. Owing to the filamentary nature of most RS devices, the variability of RS parameters can be reduced by doping in the RS region, where conductive filaments (CFs) can grow along the locations of impurities. In this work, we have successfully obtained RS characteristics in Pt dispersed silicon oxide-based memristors. The RS variabilities and mechanisms have been analyzed by screening the statistical data into different resistance ranges, and the distributions are shown to be compatible with a Weibull distribution. Additionally, a quantum points contact (QPC) model has been validated to account for the conductive mechanism and further sheds light on the evolution of the CFs during RS processes. Full article

(This article belongs to the Special Issue Emerging Memory and Computing Devices in the Era of Intelligent Machines)

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24 pages, 10888 KiB

Open AccessArticle

New Logic-In-Memory Paradigms: An Architectural and Technological Perspective

by Giulia Santoro, Giovanna Turvani and Mariagrazia Graziano

Micromachines 2019, 10(6), 368; https://doi.org/10.3390/mi10060368 - 31 May 2019

Cited by 42 | Viewed by 7114

Abstract

Processing systems are in continuous evolution thanks to the constant technological advancement and architectural progress. Over the years, computing systems have become more and more powerful, providing support for applications, such as Machine Learning, that require high computational power. However, the growing complexity [...] Read more.

Processing systems are in continuous evolution thanks to the constant technological advancement and architectural progress. Over the years, computing systems have become more and more powerful, providing support for applications, such as Machine Learning, that require high computational power. However, the growing complexity of modern computing units and applications has had a strong impact on power consumption. In addition, the memory plays a key role on the overall power consumption of the system, especially when considering data-intensive applications. These applications, in fact, require a lot of data movement between the memory and the computing unit. The consequence is twofold: Memory accesses are expensive in terms of energy and a lot of time is wasted in accessing the memory, rather than processing, because of the performance gap that exists between memories and processing units. This gap is known as the memory wall or the von Neumann bottleneck and is due to the different rate of progress between complementary metal–oxide semiconductor (CMOS) technology and memories. However, CMOS scaling is also reaching a limit where it would not be possible to make further progress. This work addresses all these problems from an architectural and technological point of view by: (1) Proposing a novel Configurable Logic-in-Memory Architecture that exploits the in-memory computing paradigm to reduce the memory wall problem while also providing high performance thanks to its flexibility and parallelism; (2) exploring a non-CMOS technology as possible candidate technology for the Logic-in-Memory paradigm. Full article

(This article belongs to the Special Issue Emerging Memory and Computing Devices in the Era of Intelligent Machines)

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15 pages, 2508 KiB

Open AccessArticle

A Flexible Hybrid BCH Decoder for Modern NAND Flash Memories Using General Purpose Graphical Processing Units (GPGPUs)

by Arul Subbiah and Tokunbo Ogunfunmi

Micromachines 2019, 10(6), 365; https://doi.org/10.3390/mi10060365 - 31 May 2019

Cited by 12 | Viewed by 4335

Abstract

Bose–Chaudhuri–Hocquenghem (BCH) codes are broadly used to correct errors in flash memory systems and digital communications. These codes are cyclic block codes and have their arithmetic fixed over the splitting field of their generator polynomial. There are many solutions proposed using CPUs, hardware, [...] Read more.

Bose–Chaudhuri–Hocquenghem (BCH) codes are broadly used to correct errors in flash memory systems and digital communications. These codes are cyclic block codes and have their arithmetic fixed over the splitting field of their generator polynomial. There are many solutions proposed using CPUs, hardware, and Graphical Processing Units (GPUs) for the BCH decoders. The performance of these BCH decoders is of ultimate importance for systems involving flash memory. However, it is essential to have a flexible solution to correct multiple bit errors over the different finite fields (GF(2

^{m}

)). In this paper, we propose a pragmatic approach to decode BCH codes over the different finite fields using hardware circuits and GPUs in tandem. We propose to employ hardware design for a modified syndrome generator and GPUs for a key-equation solver and an error corrector. Using the above partition, we have shown the ability to support multiple bit errors across different BCH block codes without compromising on the performance. Furthermore, the proposed method to generate modified syndrome has zero latency for scenarios where there are no errors. When there is an error detected, the GPUs are deployed to correct the errors using the iBM and Chien search algorithm. The results have shown that using the modified syndrome approach, we can support different multiple finite fields with high throughput. Full article

(This article belongs to the Special Issue Emerging Memory and Computing Devices in the Era of Intelligent Machines)

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7 pages, 2436 KiB

Open AccessArticle

Investigation of Intra-Nitride Charge Migration Suppression in SONOS Flash Memory

by Seung-Dong Yang, Jun-Kyo Jung, Jae-Gab Lim, Seong-gye Park, Hi-Deok Lee and Ga-Won Lee

Micromachines 2019, 10(6), 356; https://doi.org/10.3390/mi10060356 - 29 May 2019

Cited by 4 | Viewed by 4606

Abstract

In order to suppress the intra-nitride charge spreading in 3D Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) flash memory where the charge trapping layer silicon nitride is shared along the cell string, N₂ plasma treated on the silicon nitride is proposed. Experimental results show that the charge [...] Read more.

In order to suppress the intra-nitride charge spreading in 3D Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) flash memory where the charge trapping layer silicon nitride is shared along the cell string, N₂ plasma treated on the silicon nitride is proposed. Experimental results show that the charge loss decreased in the plasma treated device after baking at 300 °C for 2 h. To extract trap density according to the location in the trapping layer, capacitance-voltage analysis was used and N₂ plasma treatment was shown to be effective to restrain the interface trap formation between blocking oxide and silicon nitride. Moreover, from X-ray Photoelectron Spectroscopy, the reduction of Si-O-N bonding was observed. Full article

(This article belongs to the Special Issue Emerging Memory and Computing Devices in the Era of Intelligent Machines)

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8 pages, 1864 KiB

Open AccessArticle

Matrix Mapping on Crossbar Memory Arrays with Resistive Interconnects and Its Use in In-Memory Compression of Biosignals

by Yoon Kyeung Lee, Jeong Woo Jeon, Eui-Sang Park, Chanyoung Yoo, Woohyun Kim, Manick Ha and Cheol Seong Hwang

Micromachines 2019, 10(5), 306; https://doi.org/10.3390/mi10050306 - 7 May 2019

Cited by 18 | Viewed by 4567

Abstract

Recent advances in nanoscale resistive memory devices offer promising opportunities for in-memory computing with their capability of simultaneous information storage and processing. The relationship between current and memory conductance can be utilized to perform matrix-vector multiplication for data-intensive tasks, such as training and [...] Read more.

Recent advances in nanoscale resistive memory devices offer promising opportunities for in-memory computing with their capability of simultaneous information storage and processing. The relationship between current and memory conductance can be utilized to perform matrix-vector multiplication for data-intensive tasks, such as training and inference in machine learning and analysis of continuous data stream. This work implements a mapping algorithm of memory conductance for matrix-vector multiplication using a realistic crossbar model with finite cell-to-cell resistance. An iterative simulation calculates the matrix-specific local junction voltages at each crosspoint, and systematically compensates the voltage drop by multiplying the memory conductance with the ratio between the applied and real junction potential. The calibration factors depend both on the location of the crosspoints and the matrix structure. This modification enabled the compression of Electrocardiographic signals, which was not possible with uncalibrated conductance. The results suggest potential utilities of the calibration scheme in the processing of data generated from mobile sensing or communication devices that requires energy/areal efficiencies. Full article

(This article belongs to the Special Issue Emerging Memory and Computing Devices in the Era of Intelligent Machines)

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15 pages, 1795 KiB

Open AccessArticle

In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs

by Ho Hyun Shin and Eui-Young Chung

Micromachines 2019, 10(2), 124; https://doi.org/10.3390/mi10020124 - 14 Feb 2019

Cited by 3 | Viewed by 4750

Abstract

Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations. However, it also suffers from memory wall problems due to long latency, such as with typical 2D-DRAMs. Although there are various cache management techniques [...] Read more.

Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations. However, it also suffers from memory wall problems due to long latency, such as with typical 2D-DRAMs. Although there are various cache management techniques and latency hiding schemes to reduce DRAM access time, in a high-performance system using high-capacity 3D-stacked DRAM, it is ultimately essential to reduce the latency of the DRAM itself. To solve this problem, various asymmetric in-DRAM cache structures have recently been proposed, which are more attractive for high-capacity DRAMs because they can be implemented at a lower cost in 3D-stacked DRAMs. However, most research mainly focuses on the architecture of the in-DRAM cache itself and does not pay much attention to proper management methods. In this paper, we propose two new management algorithms for the in-DRAM caches to achieve a low-latency and low-power 3D-stacked DRAM device. Through the computing system simulation, we demonstrate the improvement of energy delay product up to 67%. Full article

(This article belongs to the Special Issue Emerging Memory and Computing Devices in the Era of Intelligent Machines)

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18 pages, 3841 KiB

Open AccessReview

Development of Bioelectronic Devices Using Bionanohybrid Materials for Biocomputation System

by Jinho Yoon, Taek Lee and Jeong-Woo Choi

Micromachines 2019, 10(5), 347; https://doi.org/10.3390/mi10050347 - 27 May 2019

Cited by 15 | Viewed by 4441

Abstract

Bioelectronic devices have been researched widely because of their potential applications, such as information storage devices, biosensors, diagnosis systems, organism-mimicking processing system cell chips, and neural-mimicking systems. Introducing biomolecules including proteins, DNA, and RNA on silicon-based substrates has shown the powerful potential for [...] Read more.

Bioelectronic devices have been researched widely because of their potential applications, such as information storage devices, biosensors, diagnosis systems, organism-mimicking processing system cell chips, and neural-mimicking systems. Introducing biomolecules including proteins, DNA, and RNA on silicon-based substrates has shown the powerful potential for granting various functional properties to chips, including specific functional electronic properties. Until now, to extend and improve their properties and performance, organic and inorganic materials such as graphene and gold nanoparticles have been combined with biomolecules. In particular, bionanohybrid materials that are composed of biomolecules and other materials have been researched because they can perform core roles of information storage and signal processing in bioelectronic devices using the unique properties derived from biomolecules. This review discusses bioelectronic devices related to computation systems such as biomemory, biologic gates, and bioprocessors based on bionanohybrid materials with a selective overview of recent research. This review contains a new direction for the development of bioelectronic devices to develop biocomputation systems using biomolecules in the future. Full article

(This article belongs to the Special Issue Emerging Memory and Computing Devices in the Era of Intelligent Machines)

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31 pages, 9481 KiB

Open AccessFeature PaperReview

Recent Progress in the Voltage-Controlled Magnetic Anisotropy Effect and the Challenges Faced in Developing Voltage-Torque MRAM

by Takayuki Nozaki, Tatsuya Yamamoto, Shinji Miwa, Masahito Tsujikawa, Masafumi Shirai, Shinji Yuasa and Yoshishige Suzuki

Micromachines 2019, 10(5), 327; https://doi.org/10.3390/mi10050327 - 15 May 2019

Cited by 113 | Viewed by 9382

Abstract

The electron spin degree of freedom can provide the functionality of “nonvolatility” in electronic devices. For example, magnetoresistive random access memory (MRAM) is expected as an ideal nonvolatile working memory, with high speed response, high write endurance, and good compatibility with complementary metal-oxide-semiconductor [...] Read more.

The electron spin degree of freedom can provide the functionality of “nonvolatility” in electronic devices. For example, magnetoresistive random access memory (MRAM) is expected as an ideal nonvolatile working memory, with high speed response, high write endurance, and good compatibility with complementary metal-oxide-semiconductor (CMOS) technologies. However, a challenging technical issue is to reduce the operating power. With the present technology, an electrical current is required to control the direction and dynamics of the spin. This consumes high energy when compared with electric-field controlled devices, such as those that are used in the semiconductor industry. A novel approach to overcome this problem is to use the voltage-controlled magnetic anisotropy (VCMA) effect, which draws attention to the development of a new type of MRAM that is controlled by voltage (voltage-torque MRAM). This paper reviews recent progress in experimental demonstrations of the VCMA effect. First, we present an overview of the early experimental observations of the VCMA effect in all-solid state devices, and follow this with an introduction of the concept of the voltage-induced dynamic switching technique. Subsequently, we describe recent progress in understanding of physical origin of the VCMA effect. Finally, new materials research to realize a highly-efficient VCMA effect and the verification of reliable voltage-induced dynamic switching with a low write error rate are introduced, followed by a discussion of the technical challenges that will be encountered in the future development of voltage-torque MRAM. Full article

(This article belongs to the Special Issue Emerging Memory and Computing Devices in the Era of Intelligent Machines)

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