Journal of Low Power Electronics and Applications

15 pages, 2215 KiB

Open AccessArticle

A New Physical Design Flow for a Selective State Retention Based Approach

by Joseph Rabinowicz and Shlomo Greenberg

J. Low Power Electron. Appl. 2021, 11(3), 35; https://doi.org/10.3390/jlpea11030035 - 13 Sep 2021

Cited by 2 | Viewed by 3828

This research presents a novel approach for physical design implementation aimed for a System on Chip (SoC) based on Selective State Retention techniques. Leakage current has become a dominant factor in Very Large Scale Integration (VLSI) design. Power Gating (PG) techniques were first [...] Read more.

This research presents a novel approach for physical design implementation aimed for a System on Chip (SoC) based on Selective State Retention techniques. Leakage current has become a dominant factor in Very Large Scale Integration (VLSI) design. Power Gating (PG) techniques were first developed to mitigate these leakage currents, but they result in longer SoC wake-up periods due to loss of state. The common State Retention Power Gating (SRPG) approach was developed to overcome the PG technique’s loss of state drawback. However, SRPG resulted in a costly expense of die area overhead due to the additional state retention logic required to keep the design state when power is gated. Moreover, the physical design implementation of SRPG presents additional wiring due to the extra power supply network and power-gating controls for the state retention logic. This results in increased implementation complexity for the physical design tools, and therefore increases runtime and limits the ability to handle large designs. Recently published works on Selective State Retention Power Gating (SSRPG) techniques allow reducing the total amount of retention logic and their leakage currents. Although the SSRPG approach mitigates the overhead area and power limitations of the conventional SRPG technique, still both SRPG and SSRPG approaches require a similar extra power grid network for the retention cells, and the effect of the selective approach on the complexity of the physical design has not been yet investigated. Therefore, this paper introduces further analysis of the physical design flow for the SSRPG design, which is required for optimal cell placement and power grid allocation. This significantly increases the potential routing area, which directly improves the convergence time of the Place and Route tools. Full article

(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)

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14 pages, 6098 KiB

Open AccessArticle

Implementation of Multi-Exit Neural-Network Inferences for an Image-Based Sensing System with Energy Harvesting

by Yuyang Li, Yuxin Gao, Minghe Shao, Joseph T. Tonecha, Yawen Wu, Jingtong Hu and Inhee Lee

J. Low Power Electron. Appl. 2021, 11(3), 34; https://doi.org/10.3390/jlpea11030034 - 4 Sep 2021

Cited by 5 | Viewed by 3765

Abstract

Wireless sensor systems powered by batteries are widely used in a variety of applications. For applications with space limitation, their size was reduced, limiting battery energy capacity and memory storage size. A multi-exit neural network enables to overcome these limitations by filtering out [...] Read more.

Wireless sensor systems powered by batteries are widely used in a variety of applications. For applications with space limitation, their size was reduced, limiting battery energy capacity and memory storage size. A multi-exit neural network enables to overcome these limitations by filtering out data without objects of interest, thereby avoiding computing the entire neural network. This paper proposes to implement a multi-exit convolutional neural network on the ESP32-CAM embedded platform as an image-sensing system with an energy constraint. The multi-exit design saves energy by 42.7% compared with the single-exit condition. A simulation result, based on an exemplary natural outdoor light profile and measured energy consumption of the proposed system, shows that the system can sustain its operation with a 3.2 kJ (275 mAh @ 3.2 V) battery by scarifying the accuracy only by 2.7%. Full article

(This article belongs to the Special Issue Hardware for Machine Learning)

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16 pages, 6073 KiB

Open AccessArticle

Comparative Modelling and Thermal Analysis of AlGaN/GaN Power Devices

by Mahesh B. Manandhar and Mohammad A. Matin

J. Low Power Electron. Appl. 2021, 11(3), 33; https://doi.org/10.3390/jlpea11030033 - 3 Sep 2021

Cited by 3 | Viewed by 4141

Abstract

The use of Aluminum Gallium Nitride (AlGaN) as a power switching device material has been a promising topic of research in recent years. Along with Silicon Carbide (SiC) and Gallium Nitride (GaN), AlGaN is categorized as a Wideband Gap (WBG) material with intrinsic [...] Read more.

The use of Aluminum Gallium Nitride (AlGaN) as a power switching device material has been a promising topic of research in recent years. Along with Silicon Carbide (SiC) and Gallium Nitride (GaN), AlGaN is categorized as a Wideband Gap (WBG) material with intrinsic properties best suited for high power switching applications. This paper simulates and compares the thermal and electrical performance of AlGaN and Silicon (Si) MOSFETs, modeled in COMSOL Multiphysics. Comparisons between similar AlGaN/GaN and Si power modules are made in terms of heatsink requirements. The temperatures for the same operating voltage are found to be significantly lower for the AlGaN MOSFETs structures, compared to Si. The heatsink size for the AlGaN/GaN is found to be smaller compared to Si for the power modules. Full article

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25 pages, 1814 KiB

Open AccessArticle

A Dynamic Reconfigurable Architecture for Hybrid Spiking and Convolutional FPGA-Based Neural Network Designs

by Hasan Irmak, Federico Corradi, Paul Detterer, Nikolaos Alachiotis and Daniel Ziener

J. Low Power Electron. Appl. 2021, 11(3), 32; https://doi.org/10.3390/jlpea11030032 - 17 Aug 2021

Cited by 20 | Viewed by 5638

Abstract

This work presents a dynamically reconfigurable architecture for Neural Network (NN) accelerators implemented in Field-Programmable Gate Array (FPGA) that can be applied in a variety of application scenarios. Although the concept of Dynamic Partial Reconfiguration (DPR) is increasingly used in NN accelerators, the [...] Read more.

This work presents a dynamically reconfigurable architecture for Neural Network (NN) accelerators implemented in Field-Programmable Gate Array (FPGA) that can be applied in a variety of application scenarios. Although the concept of Dynamic Partial Reconfiguration (DPR) is increasingly used in NN accelerators, the throughput is usually lower than pure static designs. This work presents a dynamically reconfigurable energy-efficient accelerator architecture that does not sacrifice throughput performance. The proposed accelerator comprises reconfigurable processing engines and dynamically utilizes the device resources according to model parameters. Using the proposed architecture with DPR, different NN types and architectures can be realized on the same FPGA. Moreover, the proposed architecture maximizes throughput performance with design optimizations while considering the available resources on the hardware platform. We evaluate our design with different NN architectures for two different tasks. The first task is the image classification of two distinct datasets, and this requires switching between Convolutional Neural Network (CNN) architectures having different layer structures. The second task requires switching between NN architectures, namely a CNN architecture with high accuracy and throughput and a hybrid architecture that combines convolutional layers and an optimized Spiking Neural Network (SNN) architecture. We demonstrate throughput results from quickly reprogramming only a tiny part of the FPGA hardware using DPR. Experimental results show that the implemented designs achieve a 7× faster frame rate than current FPGA accelerators while being extremely flexible and using comparable resources. Full article

(This article belongs to the Special Issue Hardware for Machine Learning)

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13 pages, 4189 KiB

Open AccessArticle

Implementation of Power-Efficient Class AB Miller Amplifiers Using Resistive Local Common-Mode Feedback

by Anindita Paul, Mario Renteria-Pinon, Jaime Ramirez-Angulo, Ricardo Bolaños-Pérez, Héctor Vázquez-Leal, Jesús Huerta-Chua and Alejandro Diaz-Sánchez

J. Low Power Electron. Appl. 2021, 11(3), 31; https://doi.org/10.3390/jlpea11030031 - 26 Jul 2021

Cited by 4 | Viewed by 4076

Abstract

An approach to implement single-ended power-efficient static class-AB Miller op-amps with symmetrical and significantly enhanced slew-rate and accurately controlled output quiescent current is introduced. The proposed op-amp can drive a wide range of resistive and capacitive loads. The output positive and negative currents [...] Read more.

An approach to implement single-ended power-efficient static class-AB Miller op-amps with symmetrical and significantly enhanced slew-rate and accurately controlled output quiescent current is introduced. The proposed op-amp can drive a wide range of resistive and capacitive loads. The output positive and negative currents can be much higher than the total op-amp quiescent current. The enhanced performance is achieved by utilizing a simple low-power auxiliary amplifier with resistive local common-mode feedback that increases the quiescent power dissipation by less than 10%. The proposed class AB op-amp is characterized by significantly enhanced large-signal dynamic, static current efficiency, and small-signal figures of merits. The dynamic current efficiency is 15.6 higher, the static current efficiency is 10.6 times higher, and the small-signal figure of merit is 2.3 times higher than the conventional class-A op-amp. A global figure of merit that determines an op-amp’s ultimate speed is 6.33 times higher than the conventional class A op-amp. Full article

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17 pages, 3244 KiB

Open AccessArticle

A New VCII Application: Sinusoidal Oscillators

by Vincenzo Stornelli, Gianluca Barile, Leonardo Pantoli, Massimo Scarsella, Giuseppe Ferri, Francesco Centurelli, Pasquale Tommasino and Alessandro Trifiletti

J. Low Power Electron. Appl. 2021, 11(3), 30; https://doi.org/10.3390/jlpea11030030 - 8 Jul 2021

Cited by 19 | Viewed by 4489

Abstract

The aim of this paper is to prove that, through a canonic approach, sinusoidal oscillators based on second-generation voltage conveyor (VCII) can be implemented. The investigation demonstrates the feasibility of the design results in a pair of new canonic oscillators based on negative [...] Read more.

The aim of this paper is to prove that, through a canonic approach, sinusoidal oscillators based on second-generation voltage conveyor (VCII) can be implemented. The investigation demonstrates the feasibility of the design results in a pair of new canonic oscillators based on negative type VCII (VCII⁻). Interestingly, the same analysis shows that no canonic oscillator configuration can be achieved using positive type VCII (VCII⁺), since a single VCII⁺ does not present the correct port conditions to implement such a device. From this analysis, it comes about that, for 5-node networks, the two presented oscillator configurations are the only possible ones and make use of two resistors, two capacitors and a single VCII⁻. Notably, the produced sinusoidal output signal is easily available through the low output impedance Z port of VCII, removing the need for additional voltage buffer for practical use, which is one of the main limitations of the current mode (CM) approach. The presented theory is substantiated by both LTSpice simulations and measurement results using the commercially available AD844 from Analog Devices, the latter being in a close agreement with the theory. Moreover, low values of THD are given for a wide frequency range. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things)

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18 pages, 2199 KiB

Open AccessArticle

Energy-Efficient Non-Von Neumann Computing Architecture Supporting Multiple Computing Paradigms for Logic and Binarized Neural Networks

by Tommaso Zanotti, Francesco Maria Puglisi and Paolo Pavan

J. Low Power Electron. Appl. 2021, 11(3), 29; https://doi.org/10.3390/jlpea11030029 - 6 Jul 2021

Cited by 8 | Viewed by 4998

Abstract

Different in-memory computing paradigms enabled by emerging non-volatile memory technologies are promising solutions for the development of ultra-low-power hardware for edge computing. Among these, SIMPLY, a smart logic-in-memory architecture, provides high reconfigurability and enables the in-memory computation of both logic operations and binarized [...] Read more.

Different in-memory computing paradigms enabled by emerging non-volatile memory technologies are promising solutions for the development of ultra-low-power hardware for edge computing. Among these, SIMPLY, a smart logic-in-memory architecture, provides high reconfigurability and enables the in-memory computation of both logic operations and binarized neural networks (BNNs) inference. However, operation-specific hardware accelerators can result in better performance for a particular task, such as the analog computation of the multiply and accumulate operation for BNN inference, but lack reconfigurability. Nonetheless, a solution providing the flexibility of SIMPLY while also achieving the high performance of BNN-specific analog hardware accelerators is missing. In this work, we propose a novel in-memory architecture based on 1T1R crossbar arrays, which enables the coexistence on the same crossbar array of both SIMPLY computing paradigm and the analog acceleration of the multiply and accumulate operation for BNN inference. We also highlight the main design tradeoffs and opportunities enabled by different emerging non-volatile memory technologies. Finally, by using a physics-based Resistive Random Access Memory (RRAM) compact model calibrated on data from the literature, we show that the proposed architecture improves the energy delay product by >10³ times when performing a BNN inference task with respect to a SIMPLY implementation. Full article

(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)

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13 pages, 522 KiB

Open AccessArticle

Dynamic Compilation for Transprecision Applications on Heterogeneous Platform

by Julie Dumas, Henri-Pierre Charles, Kévin Mambu and Maha Kooli

J. Low Power Electron. Appl. 2021, 11(3), 28; https://doi.org/10.3390/jlpea11030028 - 29 Jun 2021

Cited by 1 | Viewed by 3483

Abstract

This article describes a software environment called HybroGen, which helps to experiment binary code generation at run time. As computing architectures are getting more complex, the application performance is becoming data-dependent. The proposed experimental platform is helpful in programming applications that can [...] Read more.

This article describes a software environment called HybroGen, which helps to experiment binary code generation at run time. As computing architectures are getting more complex, the application performance is becoming data-dependent. The proposed experimental platform is helpful in programming applications that can be reconfigured at run time in order to be adapted for a new data environment. The HybroGen platform is adapted to heterogeneous architectures and can generate instructions for different targets. This platform allows to go farther than classical JIT compilation in many directions: the code generator is smaller by three orders of magnitude and faster by three orders of magnitude, compared to JIT (Just-In-Time) platforms, and allows making code transformation that is impossible in traditional compilation schemes, such as code generation for non von Neumann accelerators or dynamic code transformations for transprecision. The latter is illustrated in a code example: the square root with Newton’s algorithm. We also illustrate the proposed HybroGen platform with two other examples: a multiplication with a specialization on a value determined at run time, and a conversion of degrees Celsius to degrees Fahrenheit. This article presents a proof of concept of the proposed HybroGen platform in terms of its functionalities, and demonstrates the working status. Full article

(This article belongs to the Special Issue Advances in Programming Parallel and Heterogeneous Computing for Cyber-Physical Systems)

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J. Low Power Electron. Appl., Volume 11, Issue 3 (September 2021) – 8 articles

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