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Embedded Systems: Fundamentals, Design and Practical Applications
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Embedded Systems: Fundamentals, Design and Practical Applications

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (15 September 2024) | Viewed by 49702

Special Issue Editors

Prof. Dr. Alexander Barkalov

E-Mail Website
Guest Editor
Institute of Metrology, Electronics and Computer Science, University of Zielona Gora, 65-417 Zielona Gora, Poland
Interests: logic synthesis; FSM design; FPGA; ASIC; CPLD; embedded systems
Special Issues, Collections and Topics in MDPI journals
Prof. Dr. Larysa Titarenko

E-Mail Website
Guest Editor
Institute of Metrology, Electronics and Computer Science, University of Zielona Gora, 65-417 Zielona Gora, Poland
Interests: logic synthesis; FSM design; FPGA; ASIC; telecommunications; antenna arrays; hardware-software co-design; CAD of VLSI-based digital systems
Special Issues, Collections and Topics in MDPI journals
Prof. Dr. Dariusz Kania

E-Mail Website
Guest Editor
Faculty of Automatic Control, Electronics and Computer Science, Silesian University of Technology, 44-100 Gliwice, Poland
Interests: programmable devices and systems logic synthesis; technology-dependent partitioning; technology mapping dedicated to a wide range of programmable logic devices (FPGA, pSoC); cyber-physical systems; globally asynchronous locally synchronous digital circuits; hardware description languages (Verilog, VHDL); low power implementation of digital circuits; posturography in postural control diagnostics; motor functions rehabilitation
Special Issues, Collections and Topics in MDPI journals
Prof. Dr. Remigiusz Wiśniewski

E-Mail Website
Guest Editor
Institute of Control and Computation Engineering, University of Zielona Góra, Prof. Z. Szafrana 2, 65-516 Zielona Góra, Poland
Interests: Petri nets; FPGA; cyber–physical systems; concurrent systems; design, analysis, and modeling of CPS; cybersecurity
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Recent years have witnessed the ever-more widespread use of embedded systems in increasingly diverse areas of human activity. Suffice to say, about 99% of all manufactured microprocessors are used in embedded systems. With the development of the Internet of Things, the automation of production, and the increasing utilization of various robots, enhancing the intelligence of the material world around us would be unthinkable without the use of embedded systems. Modern embedded systems are implemented both on the basis of fairly simple microcontrollers, and on the basis of complex integrated circuits consisting of billions of transistors. In many cases, embedded systems are real-time cyber–physical systems that monitor and control complex physical objects. Such systems should be sufficiently reliable and secure. Failures in the operation of such systems should not lead to fatal consequences associated with a threat to life and/or the environment. In response to increasingly frequent hacking attacks, such systems should have strong protection against unauthorized access. The solution to this problem requires the development of implemented cryptographic protection methods, for example, in embedded systems. In the case of distributed embedded systems, effective methods of interaction of their components are of paramount importance.  The incredible complexity of modern embedded systems requires the development of effective methods for specification and automation of the design process. This is only a small part of one of the existing problems associated with the development and implementation of embedded systems. These problems provide a wide field for the theoretical research and practical implementations of embedded systems.

The aim of this Special Issue is to collate scientific manuscripts on the practical and theoretical aspects associated with theoretical and practical aspects of implementing efficient embedded systems. The key focus is to present theoretical advances, as well as new specification, design and verification methods, in order to improve the main characteristics of embedded systems.

Topics may include, but are not limited to, the following:

  1. Theoretical foundations of embedded systems;
  2. Sensors and actuators for embedded systems;
  3. Real-time embedded systems and real-time operating systems (RTOS);
  4. Scheduling algorithms in embedded systems;
  5. Techniques of low-power design in embedded systems;
  6. Improving security and dependability of embedded systems;
  7. Development of efficient analog-to-digital and digital-to-analog converters for embedded systems;
  8. Hardware-software co-design: methods and CAD tools;
  9. Design of embedded systems based on microcontrollers;
  10. User interfaces in embedded systems;
  11. Improving communication channels and communication protocols;
  12. Using embedded systems in Internet of Things and Internet of Battle Things applications;
  13. Methods of specification and development of distributed embedded systems;
  14. Methods of the implementation of mobile and autonomous embedded systems;
  15. Development of standard hardware platforms for implementing embedded systems (including reprogrammable devices, e.g., FPGAs);
  16. Methodology of platform-based design (PBD) for embedded systems;
  17. Design methodology based on models (model-driven design);
  18. Soft and hard IP cores in embedded system design;
  19. Dynamic voltage and frequency scaling, HW and SW dynamic power management;
  20. Approximate computing, low-power arithmetic;
  21. Algorithm-level optimization, low-complexity algorithm for low-power digital systems;
  22. Parallel/high-throughput processing techniques for low-power digital systems;
  23. Design space exploration techniques, with special emphasis on power/energy estimations and power minimization methodologies;
  24. Design of self-energy aware systems;
  25. High-level synthesis and HW/SW co-design techniques for low-power digital systems;
  26. Cybersecurity aspects in embedded systems;
  27. Graphical modelling of embedded systems (including Petri nets, UML, etc.);
  28. Verification and analysis methods of embedded systems (including formal methods);
  29. Validation techniques of embedded systems.

Prof. Dr. Alexander Barkalov
Prof. Dr. Larysa Titarenko
Prof. Dr. Dariusz Kania
Prof. Dr. Remigiusz Wiśniewski
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • embedded systems
  • hardware-software co-design
  • microcontrollers
  • dependability
  • security and cybersecurity
  • distributed embedded systems
  • ASIC-based design of embedded systems
  • FPGA-based design of embedded systems
  • mobile and autonomous embedded systems
  • optimization of power consumption
  • communication channels

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Published Papers (23 papers)

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Research

15 pages, 1961 KiB  
Article
Multi-Level Sum of Product (SOP) Network Power Optimization Based on Switching Graph
by Marcin Kubica and Dariusz Kania
Electronics 2024, 13(20), 4011; https://doi.org/10.3390/electronics13204011 - 12 Oct 2024
Viewed by 567
Abstract
The article presents the methodology of optimization of technology mapping of a multi-output function implemented in the form of sum of product (SOP) networks. The optimization is based on the concept of reducing the switching activity of combinational circuits. The aim of reducing [...] Read more.
The article presents the methodology of optimization of technology mapping of a multi-output function implemented in the form of sum of product (SOP) networks. The optimization is based on the concept of reducing the switching activity of combinational circuits. The aim of reducing network switching is to limit the consumption of dynamic power. Since dynamic power is one of the components of the total power consumed by digital systems, this leads to an optimization focused on the energy efficiency of digital systems. The basis of the proposed method is the technology mapping using a modified output graph describing the result of minimizing the multi-output function. The modified output graph, in terms of parameters associated with dynamic power, is defined as a switching graph. It was assumed that the key parameter associated with dynamic power is the switching activity of individual nodes of the logic network. The article presents elements of switching graph optimization which lead to the improvement of parameters associated with the dynamic power of the circuit. The essence of the proposed optimization methods is the appropriate movement of products and connections occurring in the logic network. Reducing the number of logic network vertices is also extremely important. The effectiveness of the proposed method was confirmed by the results of experiments performed on selected benchmarks. A significant reduction in the total value of switching activity was obtained for the optimized structures. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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18 pages, 16340 KiB  
Article
Real-Time Embedded Control of Vehicle Dynamics Using ESP32: A Discrete Nonlinear Approach
by Antonio Navarrete Guzmán, Cuauhtémoc Acosta Lúa, J. A. García-Rodríguez, Carlos Vidrios-Serrano and Marco A. Meza-Aguilar
Electronics 2024, 13(19), 3967; https://doi.org/10.3390/electronics13193967 - 9 Oct 2024
Viewed by 1221
Abstract
This article explores the application of the Espressif ESP32 System-On-Chip (SoC) for managing vehicle dynamics through real-time digital proportional–integral (PI-like) control. We present the development of advanced driving assistance algorithms for Active Front Steering (AFS) and Rear Torque Vectoring (RTV) on this cost-effective, [...] Read more.
This article explores the application of the Espressif ESP32 System-On-Chip (SoC) for managing vehicle dynamics through real-time digital proportional–integral (PI-like) control. We present the development of advanced driving assistance algorithms for Active Front Steering (AFS) and Rear Torque Vectoring (RTV) on this cost-effective, commercially available embedded system. Using digital PI-like control algorithms designed for AFS and RTV, the primary ESP32 board receives and processes steering signals, executing a discrete-time control model of the vehicle dynamic to enable dynamic adjustments to steering and torque. To enhance simulation realism, a secondary ESP32 is employed to generate the steering signal, effectively mimicking a steer-by-wire system via its analog output ports. This configuration facilitates the simulation and evaluation of control algorithms in a realistic test environment, ensuring enhanced vehicle dynamic stability and maneuverability under various conditions. Additionally, simulations are conducted using MATLAB 2023a and CarSim 2017.1 to compare the efficacy and benefits of the implementation. Our objective is to establish a platform for evaluating discrete controllers capable of real-time vehicle operation. This methodology accelerates and reduces the cost of improving vehicle system stability and responsiveness, enabling the immediate verification and fine-tuning of control parameters as needed. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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15 pages, 2265 KiB  
Article
Pseudo-Normalization via Integer Fast Inverse Square Root and Its Application to Fast Computation without Division
by Takashi Kusaka and Takayuki Tanaka
Electronics 2024, 13(15), 2955; https://doi.org/10.3390/electronics13152955 - 26 Jul 2024
Viewed by 1515
Abstract
Vector normalization is an important process in several algorithms. It is used in classical physical calculations, mathematical techniques, and machine learning, which has witnessed significant advancements in recent years. Normalization and regularization ensure the stability of solutions and play an important role in [...] Read more.
Vector normalization is an important process in several algorithms. It is used in classical physical calculations, mathematical techniques, and machine learning, which has witnessed significant advancements in recent years. Normalization and regularization ensure the stability of solutions and play an important role in algorithm convergence. Normalization typically refers to the division of elements by their norm. Division should not be used in algorithmic implementations because its computational cost is considerably higher than that of multiply–add operations. Based on this, there is a well-known method referred to as the fast inverse square root (FISR) algorithm in floating-point calculations (IEEE754). In deeper-level embedded systems that require fast responses or power efficiency, integer instead of real number arithmetic (floating-point number arithmetic) should be used to increase speed. Conversely, in deeper-level embedded systems that require fast responses or power efficiency, integer arithmetic should be used instead of real number arithmetic (floating-point number arithmetic) to increase speed. Therefore, embedded engineers encounter problems in instances in which they use integer arithmetic for implementation, but real number arithmetic is required to compute vectors and other higher-dimensional algebra. There is no conventional normalization algorithm similar to the FISR algorithm for integer arithmetic; however, the proposed pseudo-normalization achieves vector normalization within a restricted domain using only multiply–add operations and bit shifts. This allows for fast and robust operations, even for low-performance MCUs that do not have power-efficient FPUs. As an example, this study demonstrates the computation of the arctangent (Arctan2 function; atan2(y, x)) with high precision using only integer multiply–add operations. In this study, we proposed a method of vector normalization using only integer arithmetic for embedded systems and confirmed its effectiveness by simulation using Verilog. The research results can contribute to various fields such as signal processing of IMU sensor data, faster artificial intelligence training, and efficient rendering of computer graphics. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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18 pages, 1011 KiB  
Article
Improving Real-Time Performance of Micro-ROS with Priority-Driven Chain-Aware Scheduling
by Zilong Wang, Songran Liu, Dong Ji and Wang Yi
Electronics 2024, 13(9), 1658; https://doi.org/10.3390/electronics13091658 - 25 Apr 2024
Viewed by 993
Abstract
Micro-ROS is widely used to bridge the performance gap between resource-constrained microcontrollers and powerful computing devices in ROS-based robotic applications. After modeling the callback scheduling module and the communication module in micro-ROS, we found that there are some design flaws that significantly impact [...] Read more.
Micro-ROS is widely used to bridge the performance gap between resource-constrained microcontrollers and powerful computing devices in ROS-based robotic applications. After modeling the callback scheduling module and the communication module in micro-ROS, we found that there are some design flaws that significantly impact the real-time performance of micro-ROS. To improve the timing predictability and run-time efficiency of micro-ROS, we design and implement a priority-driven chain-aware scheduling system (PoDS) based on the existing micro-ROS architecture. The experimental results demonstrate that our proposed PoDS exhibits significantly improved real-time performance compared to the default micro-ROS. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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22 pages, 1083 KiB  
Article
Robust Embedded PID Control Software Execution Based on Automatic Malfunction Profile Feedback
by Sanghoon Lee and Daejin Park
Electronics 2024, 13(8), 1526; https://doi.org/10.3390/electronics13081526 - 17 Apr 2024
Viewed by 764
Abstract
As the information technology (IT) industry advances, embedded systems are being applied in various industrial sectors. With the expansion of application areas, there is a growing demand for high-precision, high-specification embedded systems, leading to the increased complexity of embedded software. Consequently, software errors [...] Read more.
As the information technology (IT) industry advances, embedded systems are being applied in various industrial sectors. With the expansion of application areas, there is a growing demand for high-precision, high-specification embedded systems, leading to the increased complexity of embedded software. Consequently, software errors can cause system malfunctions, resulting in accidents such as airplane crashes and the sudden acceleration of cars, leading to significant loss of life and property damage. Therefore, measures to ensure the safety and stability of increasing embedded systems malfunctions are necessary. This paper proposes a system that monitors the operation of target embedded systems in real-time and compares the extracted normal operation current/voltage patterns with the current/voltage data of a target embedded system (TES). It compares the operation data of the TES with automatically generated normal operation patterns by forcibly exposing them. It suggests algorithms for immediately detecting and efficiently recovering from the TES malfunctions. The proposed system applies two algorithms. (a) Monitoring TES current: When a malfunction is detected, a monitoring embedded systme (MES) resets the TES to restore normal operation. If malfunctions persist, it controls TES by using an algorithm to shut it down. Additionally, a proportional integral derivation (PID) control is applied to stabilize the current state. (b) Monitoring TES voltage: If a voltage drop occurs, the MES immediately stops the TES operation to minimize damage. The proposed algorithms were validated through experiments. For a normal TES consuming up to 95 mA, an error detection rate of 20% was applied. The TES was reset if it consumed over 114 mA. It was confirmed that the TES was stopped upon detecting the third malfunction. Regarding voltage, when the normal operating voltage of the system was around 5 V, if the TES operating voltage dropped below 4.3 V, it was detected as a malfunction, and the algorithm to stop the TES operation was validated. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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20 pages, 690 KiB  
Article
Generative Design of the Architecture Platform in Multiprocessor System Design
by Luise Müller, Nico Schumacher, Lukas Steffen and Christian Haubelt
Electronics 2024, 13(7), 1404; https://doi.org/10.3390/electronics13071404 - 8 Apr 2024
Viewed by 993
Abstract
When designing a system at the Electronic System Level (ESL), designers are confronted with a very large number of design decisions, each affecting the characteristics of the resulting system. Simultaneously, the demands for the system’s performance, reliability, and energy consumption have increased drastically. [...] Read more.
When designing a system at the Electronic System Level (ESL), designers are confronted with a very large number of design decisions, each affecting the characteristics of the resulting system. Simultaneously, the demands for the system’s performance, reliability, and energy consumption have increased drastically. Design Space Exploration (DSE) aims to facilitate this complex task by automating the system synthesis and traversing the design space autonomously. Previous studies on DSE have mainly considered fixed architectures with a fixed set of hardware components only. In the paper at hand, we overcome this limitation to allow for a higher degree of freedom in the design of a multiprocessor system. Instead of a fixed architecture as input, we are using a resource library containing resource types whose instances can then be arbitrarily placed and connected. More specifically, we enable the exploration of the types, the number, and the positions of required processing-type instances in a grid-based topology template in addition to deciding on the remaining system synthesis tasks, namely, resource allocation, task binding, routing, and scheduling. We provide an extensible framework, based on Answer Set Programming (ASP) modulo Theories (ASPmT), for generating system architectures fulfilling predefined constraints. Our studies show that this higher degree of freedom, originating from fewer restrictions regarding the architecture, leads to an increased complexity of the problem. In extensive experiments, we show scalability trends for a set of parameters, demonstrating the capabilities and limits of our approach. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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16 pages, 478 KiB  
Article
On-Cloud Linking Approach Using a Linkable Glue Layer for Metamorphic Edge Devices
by Dongkyu Lee and Daejin Park
Electronics 2023, 12(24), 4901; https://doi.org/10.3390/electronics12244901 - 6 Dec 2023
Cited by 2 | Viewed by 1056
Abstract
As sensors operating at the edge continue to evolve, the amount of data that edge devices need to process is increasing. Cloud computing methods have been proposed to process complex data on edge devices that are powered by limited resources. However, the existing [...] Read more.
As sensors operating at the edge continue to evolve, the amount of data that edge devices need to process is increasing. Cloud computing methods have been proposed to process complex data on edge devices that are powered by limited resources. However, the existing cloud computing approach, which provides services from servers determined at the compile stage on the edge, is not suitable for the metamorphic edge device proposed in this paper. Therefore, we have realized the operation of metamorphic edge devices by changing the service that accelerates the application in real time according to the surrounding environmental conditions on the edge device. The on-cloud linking approach separates the code for communication from the edge and server into a linkable glue layer. The separated communication code in the linkable glue layer is reconfigured in real time according to the environment of the edge device. To verify the computational acceleration of cloud computing and the real-time service change of the metamorphic edge device, we operated services that perform matrix multiplication operations with one process, two processes, and four processes in parallel on the edge–cloud system based on the on-cloud linking approach. Through the experiments, it was confirmed that the on-cloud linking approach changes the service provided in real time according to changes in external environmental data without changing the code built into the edge. When a square matrix operation with 1000 rows was loaded onto the proposed platform, the size of the code embedded into the edge device decreased by 8.88% and the operation time decreased by 96.7%. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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23 pages, 1695 KiB  
Article
FPGA Implementation of IEC 61131-3-Based Hardware-Aided Timers for Programmable Logic Controllers
by Miroslaw Chmiel, Robert Czerwinski and Andrzej Malcher
Electronics 2023, 12(20), 4255; https://doi.org/10.3390/electronics12204255 - 14 Oct 2023
Viewed by 1817
Abstract
Designs of timer function blocks (FBs) are presented in the article. The developed modules are IEC 61131-3. An analysis of IEC 61131-3 in terms of timer functionality and implementation options is presented. Three types are presented, timer-on, timer-off, and timer-pulse, with each type [...] Read more.
Designs of timer function blocks (FBs) are presented in the article. The developed modules are IEC 61131-3. An analysis of IEC 61131-3 in terms of timer functionality and implementation options is presented. Three types are presented, timer-on, timer-off, and timer-pulse, with each type designed to be fully hardware or software-like. Both designs, hardware or software-like, can operate as multi-channel timers. Particularly noteworthy is the software-like design, for which a solution without edge detectors was achieved. Such a feature was obtained by reversing the method of time determination by counting the difference between the start and end times and by using specific features of the D flip-flops, that is, clock-enable inputs. The presented timers were written in Verilog language and implemented in an FPGA chip. Thanks to the universal design of the interface, the proposed FBs can be used for the hardware support of existing programmable logic controllers (PLCs) or as an integral part of newly built PLC CPUs. The idea of a CPU architecture with hardware support is proposed. The paper presents the results of the implementation in an FPGA of the Kintex UltraScale+ family from AMD-Xilinx. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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23 pages, 807 KiB  
Article
Open-Source HW/SW Co-Simulation Using QEMU and GHDL for VHDL-Based SoC Design
by Giorgio Biagetti, Laura Falaschetti, Paolo Crippa, Michele Alessandrini and Claudio Turchetti
Electronics 2023, 12(18), 3986; https://doi.org/10.3390/electronics12183986 - 21 Sep 2023
Cited by 2 | Viewed by 3526
Abstract
Hardware/software co-simulation is a technique that can help design and validate digital circuits controlled by embedded processors. Co-simulation has largely been applied to system-level models, and tools for SystemC or SystemVerilog are readily available, but they are either not compatible or very cumbersome [...] Read more.
Hardware/software co-simulation is a technique that can help design and validate digital circuits controlled by embedded processors. Co-simulation has largely been applied to system-level models, and tools for SystemC or SystemVerilog are readily available, but they are either not compatible or very cumbersome to use with VHDL, the most commonly used language for FPGA design. This paper presents a direct, simple-to-use solution to co-simulate a VHDL design together with the firmware (FW) that controls it. It aims to bring the power of co-simulation to every digital designer, so it uses open-source tools, and the developed code is also open. A small patch applied to the QEMU emulator allows it to communicate with a custom-written VHDL module that exposes a CPU bus to the digital design, controlled by the FW emulated in QEMU. No changes to FW code or VHDL device code are required: with our approach, it is possible to co-simulate the very same code base that would then be implemented into an FPGA, enabling debugging, verification, and tracing capabilities that would not be possible even with the real hardware. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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17 pages, 390 KiB  
Article
A New Approach for Implementing Finite State Machines with Input Multiplexing
by Ignacio Garcia-Vargas and Raouf Senhadji-Navarro
Electronics 2023, 12(18), 3763; https://doi.org/10.3390/electronics12183763 - 6 Sep 2023
Viewed by 1062
Abstract
The model called Finite State Machine with Input Multiplexing (FSMIM) was proposed as a mechanism for implementing Finite State Machines (FSMs) using ROM memory. This paper presents a novel approach for achieving more efficient FSMIM implementations in Field Programmable Gate Array (FPGA) devices. [...] Read more.
The model called Finite State Machine with Input Multiplexing (FSMIM) was proposed as a mechanism for implementing Finite State Machines (FSMs) using ROM memory. This paper presents a novel approach for achieving more efficient FSMIM implementations in Field Programmable Gate Array (FPGA) devices. The aim of the proposed approach is to obtain further reductions in the use of Embedded Memory Blocks (EMBs). Unlike previous works, the proposed approach reduces the depth of the ROM by grouping states before simplifying the input selectors of the FSMIM. For this purpose, a new strategy for grouping states is proposed, and its optimality is proven. In addition, a new variant of the Minimum Maximal k-Partial Matching (MMKPM) problem and its corresponding Integer Linear Programming (ILP) formulation are proposed for simplifying input selectors. The proposed approach requires a significantly smaller number of EMBs than the approaches proposed previously. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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21 pages, 5266 KiB  
Article
Secure Sensor Prototype Using Hardware Security Modules and Trusted Execution Environments in a Blockchain Application: Wine Logistic Use Case
by Antonio J. Cabrera-Gutiérrez, Encarnación Castillo, Antonio Escobar-Molero, Juan Cruz-Cozar, Diego P. Morales and Luis Parrilla
Electronics 2023, 12(13), 2987; https://doi.org/10.3390/electronics12132987 - 7 Jul 2023
Cited by 4 | Viewed by 2031
Abstract
The security of Industrial Internet of Things (IIoT) systems is a challenge that needs to be addressed immediately, as the increasing use of new communication paradigms and the abundant use of sensors opens up new opportunities to compromise these types of systems. In [...] Read more.
The security of Industrial Internet of Things (IIoT) systems is a challenge that needs to be addressed immediately, as the increasing use of new communication paradigms and the abundant use of sensors opens up new opportunities to compromise these types of systems. In this sense, technologies such as Trusted Execution Environments (TEEs) and Hardware Security Modules (HSMs) become crucial for adding new layers of security to IIoT systems, especially to edge nodes that incorporate sensors and perform continuous measurements. These technologies, coupled with new communication paradigms such as Blockchain, offer a high reliability, robustness and good interoperability between them. This paper proposes the design of a secure sensor incorporating the above mentioned technologies—HSMs and a TEE—in a hardware device based on a dual-core architecture. Through this combination of technologies, one of the cores collects the data extracted by the sensors and implements the security mechanisms to guarantee the integrity of these data, while the remaining core is responsible for sending these data through the appropriate communication protocol. This proposed approach fits into the Blockchain networks, which act as an Oracle. Finally, to illustrate the application of this concept, a use case applied to wine logistics is described, where this secure sensor is integrated into a Blockchain that collects data from the storage and transport of barrels, and a performance evaluation of the implemented prototype is provided. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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28 pages, 5675 KiB  
Article
Towards On-Board SAR Processing with FPGA Accelerators and a PCIe Interface
by Emilio Isaac Baungarten-Leon, Gustavo Daniel Martín-del-Campo-Becerra, Susana Ortega-Cisneros, Maron Schlemon, Jorge Rivera and Andreas Reigber
Electronics 2023, 12(12), 2558; https://doi.org/10.3390/electronics12122558 - 6 Jun 2023
Cited by 2 | Viewed by 2303
Abstract
This article addresses a novel methodology for the utilization of Field Programmable Gate Array (FPGA) accelerators in on-board Synthetic Aperture Radar (SAR) processing routines. The methodology consists of using High-Level Synthesis (HLS) to create Intellectual property (IP) blocks and using the Reusable Integration [...] Read more.
This article addresses a novel methodology for the utilization of Field Programmable Gate Array (FPGA) accelerators in on-board Synthetic Aperture Radar (SAR) processing routines. The methodology consists of using High-Level Synthesis (HLS) to create Intellectual property (IP) blocks and using the Reusable Integration Framework for FPGA Accelerators (RIFFA) to develop a Peripheral Component Interconnect express (PCIe) interface between the Central Processing Unit (CPU) and the FPGA, attaining transfer rates up to 15.7 GB/s. HLS and RIFFA reduce development time (between fivefold and tenfold) by using high-level programming languages (e.g., C/C++); moreover, HLS provides optimizations like pipeline, cyclic partition, and unroll. The proposed schematic also has the advantage of being highly flexible and scalable since the IPs can be exchanged to perform different processing routines, and since RIFFA allows employing up to five FPGAs, multiple IPs can be implemented in each FPGA. Since Fast Fourier Transform (FFT) is one of the main functions in SAR processing, we present a FPGA accelerator in charge of the reordering stage of VEC-FFT (an optimized version of FFT) as a proof of concept. Results are retrieved in reversed bit order, and the conventional reordering function may consume more than half of the total clock cycles. Next, to demonstrate flexibility, an IP for matrix transposition is implemented, another computationally expensive process in SAR due to memory access. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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16 pages, 12471 KiB  
Article
Control System for Indoor Safety Measures Using a Faster R-CNN Architecture
by Julio Vega
Electronics 2023, 12(11), 2378; https://doi.org/10.3390/electronics12112378 - 24 May 2023
Cited by 2 | Viewed by 1262
Abstract
This paper presents a control system for indoor safety measures using a Faster R-CNN (Region-based Convolutional Neural Network) architecture. The proposed system aims to ensure the safety of occupants in indoor environments by detecting and recognizing potential safety hazards in real time, such [...] Read more.
This paper presents a control system for indoor safety measures using a Faster R-CNN (Region-based Convolutional Neural Network) architecture. The proposed system aims to ensure the safety of occupants in indoor environments by detecting and recognizing potential safety hazards in real time, such as capacity control, social distancing, or mask use. Using deep learning techniques, the system detects these situations to be controlled, notifying the person in charge of the company if any of these are violated. The proposed system was tested in a real teaching environment at Rey Juan Carlos University, using Raspberry Pi 4 as a hardware platform together with an Intel Neural Stick board and a pair of PiCamera RGB (Red Green Blue) cameras to capture images of the environment and a Faster R-CNN architecture to detect and classify objects within the images. To evaluate the performance of the system, a dataset of indoor images was collected and annotated for object detection and classification. The system was trained using this dataset, and its performance was evaluated based on precision, recall, and F1 score. The results show that the proposed system achieved a high level of accuracy in detecting and classifying potential safety hazards in indoor environments. The proposed system includes an efficiently implemented software infrastructure to be launched on a low-cost hardware platform, which is affordable for any company, regardless of size or revenue, and it has the potential to be integrated into existing safety systems in indoor environments such as hospitals, warehouses, and factories, to provide real-time monitoring and alerts for safety hazards. Future work will focus on enhancing the system’s robustness and scalability to larger indoor environments with more complex safety hazards. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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13 pages, 2895 KiB  
Article
Research and Implementation of Low-Power Anomaly Recognition Method for Intelligent Manhole Covers
by Jiahu Guo, Kai Wang, Jianquan Sun and Youcheng Jia
Electronics 2023, 12(8), 1926; https://doi.org/10.3390/electronics12081926 - 19 Apr 2023
Cited by 4 | Viewed by 1497
Abstract
This paper addresses the difficulty of balancing a real-time response and low power consumption in intelligent manhole cover application scenarios. It proposes a method to distinguish normal and abnormal events by segmenting the boundary at which the acceleration of the intelligent manhole cover [...] Read more.
This paper addresses the difficulty of balancing a real-time response and low power consumption in intelligent manhole cover application scenarios. It proposes a method to distinguish normal and abnormal events by segmenting the boundary at which the acceleration of the intelligent manhole cover deviates from a set threshold and lasts for a certain period, based on the difference in the intelligent manhole cover’s vibration patterns when a normal event and an abnormal event occur. This paper uses the autonomous data fusion of digital output motion sensor data to implement a pattern recognition algorithm for the above-mentioned pattern, which reduces the MCU computing and working time and the overall power consumption of the system while meeting real-time response requirements. The test results demonstrate that the method has a high rate of anomaly recognition accuracy. The method ensures the system’s real-time response capability, and the actual low power consumption test demonstrates that the device can operate continuously for 9.5 years. The low power consumption index exceeds the requirements of the existing national standard, thereby resolving the issue that it is challenging to balance intelligent manhole cover abnormality recognition and low power consumption. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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15 pages, 604 KiB  
Article
Mapping Outputs and States Encoding Bits to Outputs Using Multiplexers in Finite State Machine Implementations
by Raouf Senhadji-Navarro and Ignacio Garcia-Vargas
Electronics 2023, 12(3), 502; https://doi.org/10.3390/electronics12030502 - 18 Jan 2023
Cited by 2 | Viewed by 1571
Abstract
This paper proposes a new technique for implementing Finite State Machines (FSMs) in Field Programmable Gate Arrays (FPGAs). The proposed approach extends the called column compaction in two ways. First, it is applied to the state-encoding bits in addition to the outputs, allowing [...] Read more.
This paper proposes a new technique for implementing Finite State Machines (FSMs) in Field Programmable Gate Arrays (FPGAs). The proposed approach extends the called column compaction in two ways. First, it is applied to the state-encoding bits in addition to the outputs, allowing a reduction in the number of logic functions required both by the state transition function and by the output function. Second, the technique exploits the dedicated multiplexers usually included in FPGAs to increase the number of columns that can be compacted. Unlike conventional state-encoding techniques, the proposed approach reduces the number of logic functions instead of their complexity. An Integer Linear Programming (ILP) formulation that maximizes the number of compacted columns has been proposed. In order to evaluate the effectiveness of the proposed approach, experimental results using standard benchmarks are presented. In most cases, the proposed approach reduces the number of used Look-Up Tables (LUTs) with respect to the conventional FSM implementation. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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18 pages, 2256 KiB  
Article
A Mixed Hardware-Software Implementation of a High-Performance PMSM Controller
by Adam Milik and Tomasz Rudnicki
Electronics 2023, 12(2), 440; https://doi.org/10.3390/electronics12020440 - 14 Jan 2023
Cited by 4 | Viewed by 1411
Abstract
Implementation of the permanent magnet synchronous motor vector control implies strong time dependencies. The control process requires precise measurement of motor shaft position and winding currents to establish correct driving. The tight time dependencies are difficult to achieve using a programmatic approach. Specific [...] Read more.
Implementation of the permanent magnet synchronous motor vector control implies strong time dependencies. The control process requires precise measurement of motor shaft position and winding currents to establish correct driving. The tight time dependencies are difficult to achieve using a programmatic approach. Specific controller architecture is proposed for programmable systems on chip architectures enabling operations precise timing and improved processing performance. The controller is decomposed into a dedicated hardware interface system and programmatic part for easy implementation and modification of the control algorithm. The proposed architecture offers precise and repeatable input-output operations timing and assures meeting tight time dependencies. The control algorithm is executed as an interrupt service requested by the interface system in a constant processing period with relatively weak time dependencies. Additionally, the interface system preprocesses input and output signals reducing the computation effort and saving time for algorithm computations. The specific implementation enabled improved measurement of the motor’s windings current with suppression of disturbances caused by inverter operation. There is shown an efficient implementation of Parke’s and Clarke’s transformations using specific resources of modern programmable logic devices. In opposite to the software-managed implementation presented implementation assures completing processing faster, using a minimal number of hardware resources of the FPGA platform and offering the highest flexibility of software part implementation. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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23 pages, 1188 KiB  
Article
Mutable Observation Used by Television Drone Pilots: Efficiency of Aerial Filming Regarding the Quality of Completed Shots
by Grzegorz Borowik, Monika Kożdoń-Dębecka and Sebastian Strzelecki
Electronics 2022, 11(23), 3881; https://doi.org/10.3390/electronics11233881 - 24 Nov 2022
Cited by 3 | Viewed by 1918
Abstract
Drones, as mobile media of the present day, increase the operational and narrative capabilities of television and accelerate the logistics of shooting. Unmanned aerial vehicles with a camera properly steered by a pilot are able, to some extent, to replace a jimmy jib/crane [...] Read more.
Drones, as mobile media of the present day, increase the operational and narrative capabilities of television and accelerate the logistics of shooting. Unmanned aerial vehicles with a camera properly steered by a pilot are able, to some extent, to replace a jimmy jib/crane and a dolly; basic technical devices, used in the studios, enabling the creation of narrative systems of pictures in film and television. Television is more and more often using drone footage to report events, broadcast live, as well as create coverage and television documentaries. In many productions, the pilot of the drone simultaneously acts as the drone camera operator, which can improve the effectiveness of shooting, but also carries some risks related to flight safety. The article describes and presents in the form of processed footage the real conditional ties of a Visual Line of Sight (VLOS) flight faced by pilots filming with a drone. VLOS is a type of air operation, which requires maintaining eye contact with the drone. In many countries, a drone visibility flight is legally sanctioned as VLOS Operation. An experiment was conducted to investigate the interactions between a human and a machine in airspace steered using a controller with a touchscreen. The drone pilot was considered an integral part of the drone’s flight system control Experimental data was collected with the use of a mobile eye-tracker, video cameras, surveys, and pilot declarations. During the experiment, eight television drone pilot operators recaptured a model shot under the regime of VLOS flight at low altitudes. They all show that both advanced and beginner pilots did not look at the UAV for over half the time of shot execution. The experiment allowed establishing two coefficients related to the effectiveness of a VLOS flight aiming at filming from the drone. The results point to clear differences in screen perception styles used by drone television pilots. The coefficients were described in the form of mathematical formulas and their limit values were determined. The research also determines the limits of pilots’ perception, within which they can film with a drone. The outcomes may help to optimize the process of aerial filming with the use of a drone, carried out for television, film, and other media, as well as in a simulation of such a flight for research and training. From the perspective of media science and social communication, the presented study included a technological component that can be accessed through information science, using statistical models and variable distributions. Media scholars can study the impact of the media without having to look into the metaphorical black box. Computer science opens up this possibility. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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19 pages, 3649 KiB  
Article
Efficient FPGA Implementation of an RFIR Filter Using the APC–OMS Technique with WTM for High-Throughput Signal Processing
by Kasarla Satish Reddy, Sowmya Madhavan, Przemysław Falkowski-Gilski, Parameshachari Bidare Divakarachari and Arun Mathiyalagan
Electronics 2022, 11(19), 3118; https://doi.org/10.3390/electronics11193118 - 29 Sep 2022
Cited by 9 | Viewed by 2374
Abstract
Nowadays, Finite Impulse Response (FIR) filters are used to change the attributes of a signal in the time or frequency domain. Among FIR filters, a reconfigurable filter has the advantage of changing the coefficient in real-time, while performing the operation. In this paper, [...] Read more.
Nowadays, Finite Impulse Response (FIR) filters are used to change the attributes of a signal in the time or frequency domain. Among FIR filters, a reconfigurable filter has the advantage of changing the coefficient in real-time, while performing the operation. In this paper, the Anti-Symmetric Product Coding (APC) and Odd Multiple Storage (OMS) modules are utilized to implement the reconfigurable FIR filter (RFIR–APC–OMS). Herein, the APC–OMS module is used to reduce the area of the RFIR architecture. The performance of the RFIR–APC–OMS is analyzed in terms of: area, power, delay, LUT, flip flop, slices, and frequency. RFIR–APC–OMS has reduced 3.44% of area compared to the existing RFIR architecture employing the Dynamic Reconfigurable Partial Product Generator (DRPPG) module. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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26 pages, 7151 KiB  
Article
Using a Double-Core Structure to Reduce the LUT Count in FPGA-Based Mealy FSMs
by Alexander Barkalov, Larysa Titarenko and Kazimierz Krzywicki
Electronics 2022, 11(19), 3089; https://doi.org/10.3390/electronics11193089 - 27 Sep 2022
Cited by 2 | Viewed by 1886
Abstract
A method is proposed which aims at reducing the numbers of look-up table (LUT) elements in logic circuits of Mealy finite state machines (FSMs). The FSMs with twofold state assignment are discussed. The reduction is achieved due to using two cores of LUTs [...] Read more.
A method is proposed which aims at reducing the numbers of look-up table (LUT) elements in logic circuits of Mealy finite state machines (FSMs). The FSMs with twofold state assignment are discussed. The reduction is achieved due to using two cores of LUTs for generating partial Boolean functions. One core is based on maximum binary state codes. The second core uses extended state codes. Such an approach allows reducing the number of LUTs in the block of state codes’ transformation. The proposed approach leads to LUT-based Mealy FSM circuits having three levels of logic blocks. Each partial function for any core is represented by a single-LUT circuit. A formal method is proposed for redistribution of states between these cores. An example of synthesis is shown to explain peculiarities of the proposed method. An example of state redistribution is given. The results of experiments conducted with standard benchmarks show that the double-core approach produces LUT-based FSM circuits with better area-temporal characteristics than they are for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, and twofold state assignment). Both the LUT counts and maximum operating frequencies are improved. The gain in LUT counts varies from 5.74% to 36.92%, and the gain in frequency varies from 5.42% to 12.4%. These improvements are connected with a very small growth of the power consumption (less than 1%). The advantages of the proposed approach increase as the number of FSM inputs and states increases. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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22 pages, 2802 KiB  
Article
A Knowledge Base Technique for Detecting Multiple High-Speed Serial Interface Synchronization Errors in Multiprocessor-Based Real-Time Embedded Systems
by Sabeen Masood, Shoab Ahmed Khan, Ali Hassan and Fatima Khalique
Electronics 2022, 11(18), 2945; https://doi.org/10.3390/electronics11182945 - 17 Sep 2022
Viewed by 1770
Abstract
The heterogeneity of the multiple processing elements (PEs) is a feature of real-time embedded systems. General-purpose processors and several embedded processors, as well as dedicated high-speed interfaces, are among these elements. Communication between the processors is among the most significant characteristics of developing [...] Read more.
The heterogeneity of the multiple processing elements (PEs) is a feature of real-time embedded systems. General-purpose processors and several embedded processors, as well as dedicated high-speed interfaces, are among these elements. Communication between the processors is among the most significant characteristics of developing such complex systems. Furthermore, synchronization is a common issue during interprocessor communication in embedded systems. Debugging and testing such systems is time-consuming, difficult, and laborious, with the majority of the complexities centered on debugging real-time interprocessor communication, such as synchronization in terms of timing and accuracy. While the hardware design features of heterogeneous multiprocessor real-time embedded systems have received a lot of attention, the design and development of software-based solutions still have the potential to be addressed. In particular, software-based testing becomes challenging due to interprocessor communication and the synchronization of real-time applications. A knowledge-based technique that aids in testing high-speed serial interfaces in multiprocessor-based real-time embedded systems is proposed that needs debugging in real time while an application is running. It is becoming much more important to test and validate these interfaces in real time as the demand for high data transmission rates increases. The presented work uses a technique to simulate, create and enhance the knowledge base used as correlation-based error detection that reduces the development time. The proposed technique helps in detecting synchronization-related errors that occur during communication among multiple high-speed serial interfaces. The presented work also lists a series of experiments to validate the effectiveness of the proposed technique. The results show that the presented techniques are effective for error identification in real-time embedded systems. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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20 pages, 3035 KiB  
Article
An Efficient Real-Time FPGA-Based ORB Feature Extraction for an UHD Video Stream for Embedded Visual SLAM
by Mateusz Wasala, Hubert Szolc and Tomasz Kryjak
Electronics 2022, 11(14), 2259; https://doi.org/10.3390/electronics11142259 - 20 Jul 2022
Cited by 9 | Viewed by 3781
Abstract
The detection and description of feature points are important components of many computer vision systems. For example, in the field of autonomous unmanned aerial vehicles (UAV), these methods form the basis of so-called Visual Odometry (VO) and Simultaneous Localisation and Mapping (SLAM) algorithms. [...] Read more.
The detection and description of feature points are important components of many computer vision systems. For example, in the field of autonomous unmanned aerial vehicles (UAV), these methods form the basis of so-called Visual Odometry (VO) and Simultaneous Localisation and Mapping (SLAM) algorithms. In this paper, we present a hardware feature points detection system able to process a 4K video stream in real-time. We use the ORB algorithm—Oriented FAST (Features from Accelerated Segment Test) and Rotated BRIEF (Binary Robust Independent Elementary Features)—to detect and describe feature points in the images. We make numerous modifications to the original ORB algorithm (among others, we use the RS-BRIEF instead of classic R-BRIEF) to adapt it to the high video resolution, make it computationally efficient, reduce the resource utilisation and achieve lower power consumption. Our hardware implementation supports a 4 ppc (pixels per clock) format (with simple adaptation to 2 ppc, 8 ppc, and more) and real-time processing of a 4K video stream (UHD—Ultra High Definition, 3840×2160 pixels) @ 60 frames per second (150 MHz clock). We verify our system using simulations in the Vivado IDE and implement it in hardware on the ZCU 104 evaluation board with the AMD Xilinx Zynq UltraScale+ MPSoC device. The proposed design consumes only 5 watts. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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24 pages, 27795 KiB  
Article
Real-Time CLAHE Algorithm Implementation in SoC FPGA Device for 4K UHD Video Stream
by Tomasz Kryjak, Krzysztof Blachut, Hubert Szolc and Mateusz Wasala
Electronics 2022, 11(14), 2248; https://doi.org/10.3390/electronics11142248 - 18 Jul 2022
Cited by 7 | Viewed by 7341
Abstract
One of the problems encountered in the field of computer vision and video data analysis is the extraction of information from low-contrast images. This problem can be addressed in several ways, including the use of histogram equalisation algorithms. In this work, a method [...] Read more.
One of the problems encountered in the field of computer vision and video data analysis is the extraction of information from low-contrast images. This problem can be addressed in several ways, including the use of histogram equalisation algorithms. In this work, a method designed for this purpose—the Contrast-Limited Adaptive Histogram Equalization (CLAHE) algorithm—is implemented in hardware. An FPGA platform is used for this purpose due to the ability to run parallel computations and very low power consumption. To enable the processing of a 4K resolution (UHD, 3840 × 2160 pixels) video stream at 60 fps (frames per second) by using the CLAHE method, it is necessary to use a vector data format and process multiple pixels simultaneously. The algorithm realised in this work can be a component of a larger vision system, such as in autonomous vehicles or drones, but it can also support the analysis of underwater, thermal, or medical images both by humans and in an automated system. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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26 pages, 449 KiB  
Article
Using Codes of Output Collections for Hardware Reduction in Circuits of LUT-Based Finite State Machines
by Alexander Barkalov, Larysa Titarenko, Kazimierz Krzywicki and Kamil Mielcarek
Electronics 2022, 11(13), 2050; https://doi.org/10.3390/electronics11132050 - 29 Jun 2022
Viewed by 2249
Abstract
A method is proposed which aims to reduce the hardware in FPGA-based circuits of Mealy finite state machines (FSMs). The proposed method is a type of structural decomposition method. Its main goal is the reducing the number of look-up table (LUT) elements in [...] Read more.
A method is proposed which aims to reduce the hardware in FPGA-based circuits of Mealy finite state machines (FSMs). The proposed method is a type of structural decomposition method. Its main goal is the reducing the number of look-up table (LUT) elements in FSM circuits compared to the three-block FSM circuit. The main idea of the proposed method is the using codes of collections of FSM outputs for replacing the FSM inputs and state variables. The interstate transitions are defined using collections of outputs generated in two adjacent cycles of synchronization. One, of output collection codes, is kept into a register. To optimize block-generating FSM outputs, a new type of state codes is proposed. A state is encoded as an element of some class of states. This approach allows both the number of logic levels and inter-level interconnections in LUT-based FSM circuit to be diminished. An example of an LUT-based Mealy FSM circuit with the proposed method applied is shown. Moreover, the results of our research are represented. The research was conducted using the CAD tool Vivado by Xilinx. The experiments prove that the proposed approach allows the reduction of hardware compared with such known methods as Auto and One-hot of Vivado, and JEDI. Moreover, the proposed approach gives better results than a method based on the simultaneous replacement of inputs and encoding collections of outputs. Compared to circuits of the three-block FSMs, the LUT counts are reduced by an average of 10.07% without significant reduction in the value of operating frequency. The gain in LUT counts increases with the increasing the numbers of FSM states and inputs. Full article
(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)
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