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Volume 8
Issue 4
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J. Low Power Electron. Appl., Volume 8, Issue 4 (December 2018) – 18 articles

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23 pages, 6403 KiB  
Article
Design and Evaluation of an Electrical Bioimpedance Device Based on DIBS for Myography during Isotonic Exercises
by Vinicius Sirtoli, Kaue Morcelles, John Gomez and Pedro Bertemes-Filho
J. Low Power Electron. Appl. 2018, 8(4), 50; https://doi.org/10.3390/jlpea8040050 - 15 Dec 2018
Cited by 9 | Viewed by 7379
Abstract
Electrical Bioimpedance Spectroscopy (EIS) is a technique used to assess passive electrical properties of biological materials. EIS detects physiological and pathological conditions in animal tissues. Recently, the introduction of broadband excitation signals has reduced the measuring time for application techniques such as Electrical [...] Read more.
Electrical Bioimpedance Spectroscopy (EIS) is a technique used to assess passive electrical properties of biological materials. EIS detects physiological and pathological conditions in animal tissues. Recently, the introduction of broadband excitation signals has reduced the measuring time for application techniques such as Electrical Bioimpedance Myography. Therefore, this work is aimed at proposing a prototype by using discrete interval binary sequences (DIBS), which is based on a system that holds a current source, impedance acquisition system, microcontroller and graphical user interface. Measurements between 5 Ω to 5 kΩ had impedance acquisition and phase angle errors of aproximately 2% and were lower than 3 degrees, respectively. Based on a proposed circuit, bioimpedance of the chest muscle (Pectoralis Major) was measured during isotonic exercise (push-up). As a result, our analyses have detected tiredness and fatigue. We have explored and proposed new parameters which assess such conditions, as both the maximum magnitude and tiredness coefficient. These parameters decrease exponentially with consecutive push-ups and were convergent in the majority of the sixteen days of measurement. Full article
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15 pages, 2790 KiB  
Article
Enhancing Reliability of Tactical MANETs by Improving Routing Decisions
by Salman M. Al-Shehri and Pavel Loskot
J. Low Power Electron. Appl. 2018, 8(4), 49; https://doi.org/10.3390/jlpea8040049 - 28 Nov 2018
Cited by 4 | Viewed by 7124
Abstract
Mobile ad-hoc networks (MANETs) have been primarily designed to enhance tactical communications in a battlefield. They provide dynamic connectivity without requiring any pre-existing infrastructure. Their multi-hop capabilities can improve radio coverage significantly. The nature of tactical MANET operations requires more specialized routing protocols [...] Read more.
Mobile ad-hoc networks (MANETs) have been primarily designed to enhance tactical communications in a battlefield. They provide dynamic connectivity without requiring any pre-existing infrastructure. Their multi-hop capabilities can improve radio coverage significantly. The nature of tactical MANET operations requires more specialized routing protocols compared to the ones which are used in commercial MANET. Routing decisions in MANETs are usually conditioned on signal-to-interference-plus-noise ratio (SINR) measurements. In order to improve routing decisions for use in highly dynamic tactical MANETs, this paper proposes to combine two different metrics to achieve reliable multicast in multi-hop ad hoc networks. The resulting protocol combining received signal strength (RSS) with SINR to make routing decisions is referred to as Link Quality Aware Ad-hoc On-Demand Distance Vector (LQA-AODV) routing. The proposed routing protocol can quickly adapt to dynamic changes in network topology and link quality variations often encountered in tactical field operations. Using computer simulations, the performance of proposed protocol is shown to outperform other widely used reactive routing protocols assuming several performance metrics. Full article
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15 pages, 1748 KiB  
Article
Towards Energy-Efficient and Secure Computing Systems
by Zhiming Zhang and Qiaoyan Yu
J. Low Power Electron. Appl. 2018, 8(4), 48; https://doi.org/10.3390/jlpea8040048 - 27 Nov 2018
Cited by 1 | Viewed by 6677
Abstract
Countermeasures against diverse security threats typically incur noticeable hardware cost and power overhead, which may become the obstacle for those countermeasures to be applicable in energy-efficient computing systems. This work presents a summary of energy-efficiency techniques that have been applied in security primitives [...] Read more.
Countermeasures against diverse security threats typically incur noticeable hardware cost and power overhead, which may become the obstacle for those countermeasures to be applicable in energy-efficient computing systems. This work presents a summary of energy-efficiency techniques that have been applied in security primitives or mechanisms to ensure computing systems’ resilience against various security threats on hardware. This work also uses examples to discuss practical methods for securing the hardware for computing systems to achieve energy efficiency. Full article
(This article belongs to the Special Issue Emerging Interconnection Networks Across Scales)
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24 pages, 1141 KiB  
Article
Enabling Energy-Efficient Physical Computing through Analog Abstraction and IP Reuse
by Jennifer Hasler, Aishwarya Natarajan and Sihwan Kim
J. Low Power Electron. Appl. 2018, 8(4), 47; https://doi.org/10.3390/jlpea8040047 - 24 Nov 2018
Cited by 12 | Viewed by 7495
Abstract
This paper shows the first step in analog (and mixed signal) abstraction utilized in large-scale Field Programmable Analog Arrays (FPAA), encoded in the open-source SciLab/Xcos based toolset. Having any opportunity of a wide-scale utilization of ultra-low power technology both requires programmability/reconfigurability as well [...] Read more.
This paper shows the first step in analog (and mixed signal) abstraction utilized in large-scale Field Programmable Analog Arrays (FPAA), encoded in the open-source SciLab/Xcos based toolset. Having any opportunity of a wide-scale utilization of ultra-low power technology both requires programmability/reconfigurability as well as abstractable tools. Abstraction is essential both make systems rapidly, as well as reduce the barrier for a number of users to use ultra-low power physical computing techniques. Analog devices, circuits, and systems are abstractable and retain their energy efficient opportunities compared with custom digital hardware. We will present the analog (and mixed signal) abstraction developed for the open-source toolkit used for the SoC FPAAs. Abstraction of Blocks in the FPAA block library makes the SoC FPAA ecosystem accessible to system-level designers while still enabling circuit designers the freedom to build at a low level. Multiple working test cases of various levels of complexity illustrate the analog abstraction capability. The FPAA block library provides a starting point for discussing the fundamental block concepts of analog computational approaches. Full article
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26 pages, 2327 KiB  
Article
Low-Complexity Loeffler DCT Approximations for Image and Video Coding
by Diego F. G. Coelho, Renato J. Cintra, Fábio M. Bayer, Sunera Kulasekera, Arjuna Madanayake, Paulo Martinez, Thiago L. T. Silveira, Raíza S. Oliveira and Vassil S. Dimitrov
J. Low Power Electron. Appl. 2018, 8(4), 46; https://doi.org/10.3390/jlpea8040046 - 22 Nov 2018
Cited by 10 | Viewed by 7963
Abstract
This paper introduced a matrix parametrization method based on the Loeffler discrete cosine transform (DCT) algorithm. As a result, a new class of 8-point DCT approximations was proposed, capable of unifying the mathematical formalism of several 8-point DCT approximations archived in the literature. [...] Read more.
This paper introduced a matrix parametrization method based on the Loeffler discrete cosine transform (DCT) algorithm. As a result, a new class of 8-point DCT approximations was proposed, capable of unifying the mathematical formalism of several 8-point DCT approximations archived in the literature. Pareto-efficient DCT approximations are obtained through multicriteria optimization, where computational complexity, proximity, and coding performance are considered. Efficient approximations and their scaled 16- and 32-point versions are embedded into image and video encoders, including a JPEG-like codec and H.264/AVC and H.265/HEVC standards. Results are compared to the unmodified standard codecs. Efficient approximations are mapped and implemented on a Xilinx VLX240T FPGA and evaluated for area, speed, and power consumption. Full article
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7 pages, 3068 KiB  
Communication
Including Liquid Metal into Porous Elastomeric Films for Flexible and Enzyme-Free Glucose Fuel Cells: A Preliminary Evaluation
by Denis Desmaële, Francesco La Malfa, Francesco Rizzi, Antonio Qualtieri and Massimo De Vittorio
J. Low Power Electron. Appl. 2018, 8(4), 45; https://doi.org/10.3390/jlpea8040045 - 22 Nov 2018
Cited by 6 | Viewed by 6623
Abstract
This communication introduces a new flexible elastomeric composite film, which can directly convert the chemical energy of glucose into electricity. The fabrication process is simple, and no specific equipment is required. Notably, the liquid metal Galinstan is exploited with a two-fold objective: (i) [...] Read more.
This communication introduces a new flexible elastomeric composite film, which can directly convert the chemical energy of glucose into electricity. The fabrication process is simple, and no specific equipment is required. Notably, the liquid metal Galinstan is exploited with a two-fold objective: (i) Galinstan particles are mixed with polydimethylsiloxane to obtain a highly conductive porous thick film scaffold; (ii) the presence of Galinstan in the composite film enables the direct growth of highly catalytic gold structures. As a first proof of concept, we demonstrate that when immersed in a 20 mM glucose solution, a 5 mm-long, 5 mm-wide and 2 mm-thick sample can generate a volumetric power density up to 3.6 mW·cm − 3 at 7 mA·cm − 3 and 0.51 V without using any enzymes. Full article
(This article belongs to the Special Issue Flexible Electronics and Self-Powered Systems)
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17 pages, 3748 KiB  
Review
A Recent Progress of Spintronics Devices for Integrated Circuit Applications
by Tetsuo Endoh and Hiroaki Honjo
J. Low Power Electron. Appl. 2018, 8(4), 44; https://doi.org/10.3390/jlpea8040044 - 13 Nov 2018
Cited by 50 | Viewed by 12108
Abstract
Nonvolatile (NV) memory is a key element for future high-performance and low-power microelectronics. Among the proposed NV memories, spintronics-based ones are particularly attractive for applications, owing to their low-voltage and high-speed operation capability in addition to their high-endurance feature. There are three types [...] Read more.
Nonvolatile (NV) memory is a key element for future high-performance and low-power microelectronics. Among the proposed NV memories, spintronics-based ones are particularly attractive for applications, owing to their low-voltage and high-speed operation capability in addition to their high-endurance feature. There are three types of spintronics devices with different writing schemes: spin-transfer torque (STT), spin-orbit torque (SOT), and electric field (E-field) effect on magnetic anisotropy. The NV memories using STT have been studied and developed most actively and are about to enter into the market by major semiconductor foundry companies. On the other hand, a development of the NV memories using other writing schemes are now underway. In this review article, first, the recent advancement of the spintronics device using STT and the NV memories using them are reviewed. Next, spintronics devices using the other two writing schemes (SOT and E-field) are briefly reviewed, including issues to be addressed for the NV memories application. Full article
(This article belongs to the Special Issue Spin-Orbit Torque/Voltage-Controlled MRAM and Low Power Application)
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13 pages, 902 KiB  
Article
Low-Cost Low-Power Acceleration of a Microwave Imaging Algorithm for Brain Stroke Monitoring
by Imran Sarwar, Giovanna Turvani, Mario R. Casu, Jorge A. Tobon, Francesca Vipiana, Rosa Scapaticci and Lorenzo Crocco
J. Low Power Electron. Appl. 2018, 8(4), 43; https://doi.org/10.3390/jlpea8040043 - 1 Nov 2018
Cited by 18 | Viewed by 7108
Abstract
Microwave imaging can effectively image the evolution of a hemorrhagic stroke thanks to the dielectric contrast between the blood and the surrounding brain tissues. To keep low both the form factor and the power consumption in a bedside device, we propose implementing a [...] Read more.
Microwave imaging can effectively image the evolution of a hemorrhagic stroke thanks to the dielectric contrast between the blood and the surrounding brain tissues. To keep low both the form factor and the power consumption in a bedside device, we propose implementing a microwave imaging algorithm for stroke monitoring in a programmable system-on-chip, in which a simple ARM-based CPU offloads to an FPGA the heavy part of the computation. Compared to a full-software implementation in the ARM CPU, we obtain a 5× speed increase with hardware acceleration without loss in accuracy and precision. Full article
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13 pages, 4287 KiB  
Article
A 0.7 V, Ultra-Wideband Common Gate LNA with Feedback Body Bias Topology for Wireless Applications
by Vikram Singh, Sandeep K. Arya and Manoj Kumar
J. Low Power Electron. Appl. 2018, 8(4), 42; https://doi.org/10.3390/jlpea8040042 - 26 Oct 2018
Cited by 7 | Viewed by 8409
Abstract
An ultra-wideband (UWB) low noise amplifier (LNA) for 3.3–13.0 GHz wireless applications using 90 nm CMOS is proposed in this paper. The proposed LNA uses an improved common-gate (CG) topology utilizing feedback body biasing (FBB), which improves noise figure (NF) by a considerable [...] Read more.
An ultra-wideband (UWB) low noise amplifier (LNA) for 3.3–13.0 GHz wireless applications using 90 nm CMOS is proposed in this paper. The proposed LNA uses an improved common-gate (CG) topology utilizing feedback body biasing (FBB), which improves noise figure (NF) by a considerable amount. Parallel-series tuned LC network was used between the common-gate first stage and the cascoded common-source (CS) stage to achieve the maximum signal flow from CG to CS stage. Improved CS topology with a series inductor at the drain terminal in the second stage connected and cascoded CS third stage provides high power gain (S21) and bandwidth enhancement throughout the complete UWB. A common-drain buffer stage at the output provides high output reflection coefficient (S22). It achieves an average power gain (S21) of 14.7 ± 0.5 dB with a noise figure (NF) of 3.0–3.7 dB. It has an input reflection coefficient (S11) less than −11.7 dB for 3.3–13.0 GHz frequency and output reflection coefficient (S22) of less than −10.6 dB with a very high reversion isolation (S12) of less than −72.4 dB. It consumes only 5.2 mW from a 0.7 V power supply. Full article
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13 pages, 6401 KiB  
Article
A Novel Approach to Design SRAM Cells for Low Leakage and Improved Stability
by Tripti Tripathi, Durg Singh Chauhan and Sanjay Kumar Singh
J. Low Power Electron. Appl. 2018, 8(4), 41; https://doi.org/10.3390/jlpea8040041 - 24 Oct 2018
Cited by 12 | Viewed by 10824
Abstract
The semiconductor electronic industry is advancing at a very fast pace. The size of portable and handheld devices are shrinking day by day and the demand for longer battery backup is also increasing. With these requirements, the leakage power in stand-by mode becomes [...] Read more.
The semiconductor electronic industry is advancing at a very fast pace. The size of portable and handheld devices are shrinking day by day and the demand for longer battery backup is also increasing. With these requirements, the leakage power in stand-by mode becomes a critical concern for researchers. In most of these devices, memory is an integral part and its size also scales down as the device size is reduced. So, low power and high speed memory design is a prime concern. Another crucial factor is the stability of static random-access memory (SRAM) cells. This paper combines multi threshold and fingering techniques to propose a modified 6T SRAM cell which has high speed, improved stability and low leakage current in stand-by mode of the memory cell. The simulations are done using the Cadence Virtuoso tool on UMC 55 nm technology. Full article
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2 pages, 132 KiB  
Editorial
Editorial for the Special Issue on “Quantum-Dot Cellular Automata (QCA) and Low Power Application”
by Stefania Perri
J. Low Power Electron. Appl. 2018, 8(4), 40; https://doi.org/10.3390/jlpea8040040 - 23 Oct 2018
Viewed by 5573
Abstract
Challenges created by the trend of increasingly reducing the size of transistors have made necessary innovative technologies to limit undesirable impacts on the performance speed and power consumption of future designs. [...] Full article
16 pages, 4190 KiB  
Article
Ray Tracing Modeling of Electromagnetic Propagation for On-Chip Wireless Optical Communications
by Franco Fuschini, Marina Barbiroli, Marco Zoli, Gaetano Bellanca, Giovanna Calò, Paolo Bassi and Vincenzo Petruzzelli
J. Low Power Electron. Appl. 2018, 8(4), 39; https://doi.org/10.3390/jlpea8040039 - 17 Oct 2018
Cited by 17 | Viewed by 8101
Abstract
Multi-core processors are likely to be a point of no return to meet the unending demand for increasing computational power. Nevertheless, the physical interconnection of many cores might currently represent the bottleneck toward kilo-core architectures. Optical wireless networks on-chip are therefore being considered [...] Read more.
Multi-core processors are likely to be a point of no return to meet the unending demand for increasing computational power. Nevertheless, the physical interconnection of many cores might currently represent the bottleneck toward kilo-core architectures. Optical wireless networks on-chip are therefore being considered as promising solutions to overcome the technological limits of wired interconnects. In this work, the spatial properties of the on-chip wireless channel are investigated through a ray tracing approach applied to a layered representation of the chip structure, highlighting the relationship between path loss, antenna positions and radiation properties. Full article
(This article belongs to the Special Issue Emerging Interconnection Networks Across Scales)
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27 pages, 1744 KiB  
Article
MB-CNN: Memristive Binary Convolutional Neural Networks for Embedded Mobile Devices
by Arjun Pal Chowdhury, Pranav Kulkarni and Mahdi Nazm Bojnordi
J. Low Power Electron. Appl. 2018, 8(4), 38; https://doi.org/10.3390/jlpea8040038 - 13 Oct 2018
Cited by 14 | Viewed by 10487
Abstract
Applications of neural networks have gained significant importance in embedded mobile devices and Internet of Things (IoT) nodes. In particular, convolutional neural networks have emerged as one of the most powerful techniques in computer vision, speech recognition, and AI applications that can improve [...] Read more.
Applications of neural networks have gained significant importance in embedded mobile devices and Internet of Things (IoT) nodes. In particular, convolutional neural networks have emerged as one of the most powerful techniques in computer vision, speech recognition, and AI applications that can improve the mobile user experience. However, satisfying all power and performance requirements of such low power devices is a significant challenge. Recent work has shown that binarizing a neural network can significantly improve the memory requirements of mobile devices at the cost of minor loss in accuracy. This paper proposes MB-CNN, a memristive accelerator for binary convolutional neural networks that perform XNOR convolution in-situ novel 2R memristive data blocks to improve power, performance, and memory requirements of embedded mobile devices. The proposed accelerator achieves at least 13.26 × , 5.91 × , and 3.18 × improvements in the system energy efficiency (computed by energy × delay) over the state-of-the-art software, GPU, and PIM architectures, respectively. The solution architecture which integrates CPU, GPU and MB-CNN outperforms every other configuration in terms of system energy and execution time. Full article
(This article belongs to the Special Issue Energy-Aware Neuromorphic Hardware)
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15 pages, 4643 KiB  
Article
Physical Simulations of High Speed and Low Power NanoMagnet Logic Circuits
by Giovanna Turvani, Laura D’Alessandro and Marco Vacca
J. Low Power Electron. Appl. 2018, 8(4), 37; https://doi.org/10.3390/jlpea8040037 - 8 Oct 2018
Cited by 3 | Viewed by 6427
Abstract
Among all “beyond CMOS” solutions currently under investigation, nanomagnetic logic (NML) technology is considered to be one of the most promising. In this technology, nanoscale magnets are rectangularly shaped and are characterized by the intrinsic capability of enabling logic and memory functions in [...] Read more.
Among all “beyond CMOS” solutions currently under investigation, nanomagnetic logic (NML) technology is considered to be one of the most promising. In this technology, nanoscale magnets are rectangularly shaped and are characterized by the intrinsic capability of enabling logic and memory functions in the same device. The design of logic architectures is accomplished by the use of a clocking mechanism that is needed to properly propagate information. Previous works demonstrated that the magneto-elastic effect can be exploited to implement the clocking mechanism by altering the magnetization of magnets. With this paper, we present a novel clocking mechanism enabling the independent control of each single nanodevice exploiting the magneto-elastic effect and enabling high-speed NML circuits. We prove the effectiveness of this approach by performing several micromagnetic simulations. We characterized a chain of nanomagnets in different conditions (e.g., different distance among cells, different electrical fields, and different magnet geometries). This solution improves NML, the reliability of circuits, the fabrication process, and the operating frequency of circuits while keeping the energy consumption at an extremely low level. Full article
(This article belongs to the Special Issue Quantum-Dot Cellular Automata (QCA) and Low Power Application)
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21 pages, 8267 KiB  
Article
An Experimental Characterization for Injection Quantity of a High-pressure Injector in GDI Engines
by Wen-Chang Tsai and Tung-Sheng Zhan
J. Low Power Electron. Appl. 2018, 8(4), 36; https://doi.org/10.3390/jlpea8040036 - 3 Oct 2018
Cited by 8 | Viewed by 10542
Abstract
The high-pressure (HP) injector is a highly dynamic component requiring careful voltage and pressure input modulation to achieve the required fuel injection quantities of gasoline direct injection (GDI) engines. Accurate fuel injection curves are a key influence for this technology, and therefore, will [...] Read more.
The high-pressure (HP) injector is a highly dynamic component requiring careful voltage and pressure input modulation to achieve the required fuel injection quantities of gasoline direct injection (GDI) engines. Accurate fuel injection curves are a key influence for this technology, and therefore, will require an accurate estimation of fuel flow rate to be realized. In order to be driven to rapid response with respect to solenoid valve coils, HP injectors typically require to be designed to be capable of rapid response in GDI engines. In this paper, the design and analysis of the proposed injector drive circuit are presented. Next, the effects of total pulse width, injector supply voltage, fuel system pressure, and pulse width modulation (PWM) operation on fuel injection quantities of an HP injector are measured for achieving robust performance and stability in the presence of bounded errors of the GDI injectors due to total pulse width, injector’s supply voltage, fuel pressure and PWM operation. Additionally, the fuel injection quantities of the HP injector are measured by tuning the parameters of the injector drive circuit with the PWM operation. These are defined as the fuel injection curves. Finally, experimental results are provided for verification of the proposed injector drive circuit. Full article
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15 pages, 952 KiB  
Article
Path Planning for Highly Automated Driving on Embedded GPUs
by Jörg Fickenscher, Sandra Schmidt, Frank Hannig, Mohamed Essayed Bouzouraa and Jürgen Teich
J. Low Power Electron. Appl. 2018, 8(4), 35; https://doi.org/10.3390/jlpea8040035 - 2 Oct 2018
Cited by 11 | Viewed by 7621
Abstract
The sector of autonomous driving gains more and more importance for the car makers. A key enabler of such systems is the planning of the path the vehicle should take, but it can be very computationally burdensome finding a good one. Here, new [...] Read more.
The sector of autonomous driving gains more and more importance for the car makers. A key enabler of such systems is the planning of the path the vehicle should take, but it can be very computationally burdensome finding a good one. Here, new architectures in Electronic Control Units (ECUs) are required, such as Graphics Processing Units (GPUs), because standard processors struggle to provide enough computing power. In this work, we present a novel parallelization of a path planning algorithm. We show how many paths can be reasonably planned under real-time requirements and how they can be rated. As an evaluation platform, an Nvidia Jetson board equipped with a Tegra K1 System-on-Chip (SoC) was used, whose GPU is also employed in the zFAS ECU of the AUDI AG. Full article
(This article belongs to the Special Issue Automotive Low Power Technologies)
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24 pages, 2283 KiB  
Review
Towards Neuromorphic Learning Machines Using Emerging Memory Devices with Brain-Like Energy Efficiency
by Vishal Saxena, Xinyu Wu, Ira Srivastava and Kehan Zhu
J. Low Power Electron. Appl. 2018, 8(4), 34; https://doi.org/10.3390/jlpea8040034 - 2 Oct 2018
Cited by 25 | Viewed by 10117
Abstract
The ongoing revolution in Deep Learning is redefining the nature of computing that is driven by the increasing amount of pattern classification and cognitive tasks. Specialized digital hardware for deep learning still holds its predominance due to the flexibility offered by the software [...] Read more.
The ongoing revolution in Deep Learning is redefining the nature of computing that is driven by the increasing amount of pattern classification and cognitive tasks. Specialized digital hardware for deep learning still holds its predominance due to the flexibility offered by the software implementation and maturity of algorithms. However, it is being increasingly desired that cognitive computing occurs at the edge, i.e., on hand-held devices that are energy constrained, which is energy prohibitive when employing digital von Neumann architectures. Recent explorations in digital neuromorphic hardware have shown promise, but offer low neurosynaptic density needed for scaling to applications such as intelligent cognitive assistants (ICA). Large-scale integration of nanoscale emerging memory devices with Complementary Metal Oxide Semiconductor (CMOS) mixed-signal integrated circuits can herald a new generation of Neuromorphic computers that will transcend the von Neumann bottleneck for cognitive computing tasks. Such hybrid Neuromorphic System-on-a-chip (NeuSoC) architectures promise machine learning capability at chip-scale form factor, and several orders of magnitude improvement in energy efficiency. Practical demonstration of such architectures has been limited as performance of emerging memory devices falls short of the expected behavior from the idealized memristor-based analog synapses, or weights, and novel machine learning algorithms are needed to take advantage of the device behavior. In this article, we review the challenges involved and present a pathway to realize large-scale mixed-signal NeuSoCs, from device arrays and circuits to spike-based deep learning algorithms with ‘brain-like’ energy-efficiency. Full article
(This article belongs to the Special Issue CMOS Low Power Design)
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16 pages, 4403 KiB  
Article
An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits
by Anil Khatak, Manoj Kumar and Sanjeev Dhull
J. Low Power Electron. Appl. 2018, 8(4), 33; https://doi.org/10.3390/jlpea8040033 - 25 Sep 2018
Cited by 4 | Viewed by 8911
Abstract
A modified architecture of a comparator to achieve high slew rate and boosted gain with an improvement in gain design error is introduced and investigated in this manuscript. It employs the conventional architecture of common-mode current feedback with the modified gain booster topology [...] Read more.
A modified architecture of a comparator to achieve high slew rate and boosted gain with an improvement in gain design error is introduced and investigated in this manuscript. It employs the conventional architecture of common-mode current feedback with the modified gain booster topology to increase gain, slew rate, and reduced gain error from the conventional structure. Observation from the simulation results concludes that the modified structure using 24 transistors shows power dissipation of 362.29 μW in 90 nm CMOS technology by deploying a supply voltage of 0.7 V, which is a 70% reduction as compared to the usual common mode feedback (CMFD) structure. The symmetric slew rate of 839.99 V/µs for both charging and discharging is obtained, which is 173% more than the standard CMFD structure. A reduction of 0.61% in gain error is achieved through this architecture. A SPICE simulation tool based on 90 nm CMOS technology is employed for executing the Monte Carlo simulations. A brief comparison with earlier CMFD structures shows improved performance parameters in terms of power consumption and slew rate with the reduction in gain error. Full article
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