Journal of Low Power Electronics and Applications

19 pages, 98081 KiB

Open AccessArticle

Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems

by Maher Fakih, Kim Grüttner, Sören Schreiner, Razi Seyyedi, Mikel Azkarate-Askasua, Peio Onaindia, Tomaso Poggi, Nera González Romero, Elena Quesada Gonzalez, Timmy Sundström, Salvador Peiró Frasquet, Patricia Balbastre, Tage Mohammadat, Johnny Öberg, Yosab Bebawy, Roman Obermaisser, Adele Maleki, Alina Lenz and Duncan Graham

J. Low Power Electron. Appl. 2019, 9(1), 12; https://doi.org/10.3390/jlpea9010012 - 11 Mar 2019

Cited by 2 | Viewed by 7651

Abstract

With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway [...] Read more.

With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway and avionics, multicore processors are introduced, but under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such a System on Chip (SoC) is to enhance the way the SoC handles its power consumption. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC, which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power-saving methods in safety-critical domains yet. The EU project SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This article provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most important outcome of the project. Furthermore, the application of this reference architecture in novel railway interlocking and flight controller avionic systems was demonstrated, showing the capability to achieve power savings up to 37%, while still guaranteeing time-triggered task execution and time-triggered NoC-based communication. Full article

(This article belongs to the Special Issue Ultra-low Power Embedded Systems)

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18 pages, 3931 KiB

Open AccessArticle

Tolerating Permanent Faults in the Input Port of the Network on Chip Router

by Hala J. Mohammed, Wameedh N. Flayyih and Fakhrul Z. Rokhani

J. Low Power Electron. Appl. 2019, 9(1), 11; https://doi.org/10.3390/jlpea9010011 - 27 Feb 2019

Cited by 14 | Viewed by 7217

Abstract

Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing [...] Read more.

Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses on tolerating permanent faults in the router’s input buffer component, particularly the virtual channel state fields. These fields track packets from the moment they enter the input component until they leave to the next router. The hardware redundancy approach is used to tolerate the faults in these fields due to their crucial role in managing the router operation. A built-in self-test logic is integrated into the input port to periodically detect permanent faults without interrupting router operation. These approaches make the NoC router more reliable than the unprotected NoC router with a maximum of 17% and 16% area and power overheads, respectively. In addition, the hardware redundancy approach preserves the network performance in the presence of a single fault by avoiding the virtual channel closure. Full article

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20 pages, 3936 KiB

Open AccessArticle

Analytical Performance of the Threshold Voltage and Subthreshold Swing of CSDG MOSFET

by Uchechukwu A. Maduagwu and Viranjay M. Srivastava

J. Low Power Electron. Appl. 2019, 9(1), 10; https://doi.org/10.3390/jlpea9010010 - 26 Feb 2019

Cited by 21 | Viewed by 8726

Abstract

In this research work, the threshold voltage and subthreshold swing of cylindrical surrounding double-gate (CSDG) MOSFET have been analyzed. These analyses are based on the analytical solution of 2D Poisson equation using evanescent-mode analysis (EMA). This EMA provides the better approach in solving [...] Read more.

In this research work, the threshold voltage and subthreshold swing of cylindrical surrounding double-gate (CSDG) MOSFET have been analyzed. These analyses are based on the analytical solution of 2D Poisson equation using evanescent-mode analysis (EMA). This EMA provides the better approach in solving the 2D Poisson equation by considering the oxide and Silicon regions as a two-dimensional problem, to produce physically consistent results with device simulation for better device performance. Unlike other models such as polynomial exponential and parabolic potential approximation (PPA) which consider the oxide and silicon as one-dimensional problem. Using the EMA, the 2D Poisson equation is decoupled into 1D Poisson equation which represent the long channel potential and 2D Laplace equation describing the impacts of short channel effects (SCEs) in the channel potential. Furthermore, the derived channel potential close-form expression is extended to determine the threshold voltage and subthreshold behavior of the proposed CSDG MOSFET device. This model has been evaluated with various device parameters such as radii Silicon film thickness, gate oxide thickness, and the channel length to analyze the behavior of the short channel effects in the proposed CSDG MOSFET. The accuracy of the derived expressions have been validated with the mathematical and numerical simulation. Full article

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19 pages, 755 KiB

Open AccessArticle

A Fresh View on the Microarchitectural Design of FPGA-Based RISC CPUs in the IoT Era

by Giovanni Scotti and Davide Zoni

J. Low Power Electron. Appl. 2019, 9(1), 9; https://doi.org/10.3390/jlpea9010009 - 19 Feb 2019

Cited by 16 | Viewed by 9418

Abstract

The Internet-of-Things (IoT) revolution has shaped a new application domain where low-power RISC architectures constitute the standard computational backbone. The current de-facto design practice for such architectures is to extend the ISA and the corresponding microarchitecture with custom instructions to efficiently manage the [...] Read more.

The Internet-of-Things (IoT) revolution has shaped a new application domain where low-power RISC architectures constitute the standard computational backbone. The current de-facto design practice for such architectures is to extend the ISA and the corresponding microarchitecture with custom instructions to efficiently manage the complex tasks imposed by IoT applications, i.e., augmented reality, artificial intelligence and autonomous driving, within narrow energy and area budgets. However, the new IoT application domain also offers a unique opportunity to revisit and optimize the RISC microarchitectural design flow from a more communication- and memory-centric viewpoint. This manuscript critically explores and optimizes the design of a RISC CPU front-end for IoT delivering a two-fold objective: (i) provide an optimized CPU microarchitecture; and (ii) present a set of three design guidelines to steer the implementation of IoT CPUs. The exploration sits on a newly proposed Systems-on-Chip (SoC) and RISC CPU implementing the RISC-V/IMF ISA and accounting for area, timing, and performance design metrics. Such SoC offers a reference design to evaluate pros and cons of different microarchitectural solutions. A wide combination of microarchitectures considering different branch prediction schemes, cache design architectures and on-chip bus solutions have been evaluated. The entire exploration is focused on the FPGA-based implementation due to the renewed interest for this technology demonstrated by both the research community and companies. We note that ARM launched the DesignStart FPGA program to make available the Cortex-M microcontrollers on Xilinx FPGAs in the form of IP blocks. Full article

(This article belongs to the Special Issue Ultra-low Power Embedded Systems)

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8 pages, 2642 KiB

Open AccessArticle

A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm

by Jean-Frédéric Christmann, Florent Berthier, David Coriat, Ivan Miro-Panades, Eric Guthmuller, Sébastien Thuries, Yvain Thonnart, Adam Makosiej, Olivier Debicki, Frédéric Heitzmann, Alexandre Valentian, Pascal Vivet and Edith Beigné

J. Low Power Electron. Appl. 2019, 9(1), 8; https://doi.org/10.3390/jlpea9010008 - 14 Feb 2019

Cited by 3 | Viewed by 6947

Abstract

Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power supply, while dynamically turning [...] Read more.

Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power supply, while dynamically turning on components as the application needs it. As wake up sources may be diverse, simple controllers are integrated to handle smart wake up schemes. Therefore, to prevent overconsumption while transitioning to running mode, fast wake up sequences are required. An asynchronous 16-bit Reduced Instruction Set Computer (RISC) Wake-up Controller (WuC) is proposed demonstrating 50.5 [email protected] Million Instructions Per Second (MIPS)@0.6 V wake-up latency, drastically reducing the overall wake-up energy of IoT systems. A clockless implementation of the controller saves the booting time and the power consumption of a clock generator, while providing high robustness to environmental variations such as supply voltage level. The WuC is also able to run simple tasks with a reduced Instruction Set Architecture (ISA) and achieves as low as 11.2 pJ/inst @0.5 V in Fully Depleted Silicon On Insulator (FDSOI) 28 nm. Full article

(This article belongs to the Special Issue Selected Papers from the 24th IEEE International Symposium on Asynchronous Circuits and Systems - ASYNC 2018)

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20 pages, 1229 KiB

Open AccessArticle

DoS Attack Detection and Path Collision Localization in NoC-Based MPSoC Architectures

by Cesar Giovanni Chaves, Siavoosh Payandeh Azad, Thomas Hollstein and Johanna Sepúlveda

J. Low Power Electron. Appl. 2019, 9(1), 7; https://doi.org/10.3390/jlpea9010007 - 5 Feb 2019

Cited by 13 | Viewed by 7821

Abstract

Denial of Service (DoS) attacks are an increasing threat for Multiprocessor System-on-Chip (MPSoC) architectures. By exploiting the shared resources on the chip, an attacker is able to prevent completion or degrade the performance of a task. This is extremely dangerous for MPSoCs used [...] Read more.

Denial of Service (DoS) attacks are an increasing threat for Multiprocessor System-on-Chip (MPSoC) architectures. By exploiting the shared resources on the chip, an attacker is able to prevent completion or degrade the performance of a task. This is extremely dangerous for MPSoCs used in critical applications. The Network-on-Chip (NoC), as a central MPSoC infrastructure, is exposed to this attack. In order to maintain communication availability, NoCs should be enhanced with an effective and precise attack detection mechanism that allows the triggering of effective attack mitigation mechanisms. Previous research works demonstrate DoS attacks on NoCs and propose detection methods being implemented in NoC routers. These countermeasures typically led to a significantly increased router complexity and to a high degradation of the MPSoC’s performance. To this end, we present two contributions. First, we provide an analysis of information that helps to narrow down the location of the attacker in the MPSoC, achieving up to a 69% search space reduction for locating the attacker. Second, we propose a low cost mechanism for detecting the location and direction of the interference, by enhancing the communication packet structure and placing communication degradation monitors in the NoC routers. Our experiments show that our NoC router architecture detects single-source DoS attacks and determines, with high precision, the location and direction of the collision, while incurring a low area and power overhead. Full article

(This article belongs to the Special Issue Emerging Interconnection Networks Across Scales)

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15 pages, 3430 KiB

Open AccessArticle

High Level Current Modeling for Shaping Electromagnetic Emissions in Micropipeline Circuits

by Sophie Germain, Sylvain Engels and Laurent Fesquet

J. Low Power Electron. Appl. 2019, 9(1), 6; https://doi.org/10.3390/jlpea9010006 - 29 Jan 2019

Viewed by 6400

Abstract

In order to fit circuit electromagnetic emissions within a spectral mask, a design flow based on high level current modeling for micropipeline circuits is proposed. The model produces a quick and rough estimation of the circuit current, thanks to a Timed Petri Net [...] Read more.

In order to fit circuit electromagnetic emissions within a spectral mask, a design flow based on high level current modeling for micropipeline circuits is proposed. The model produces a quick and rough estimation of the circuit current, thanks to a Timed Petri Net determining the activation instants of the different micropipeline stages and an asymmetric Laplace distribution modeling the current peaks of the activated stages. The design flow exploits this current estimation for shaping the electromagnetic emissions by setting the controller delays of the micropipeline circuits. The delay adjustment is performed by a genetic algorithm, which iterates until the electromagnetic emissions match the targeted spectral mask. In order to evaluate the technique, an Advanced Encryption Standard (AES) circuit has been designed. We first observed that the obtained current curve fits well with a gate simulation. Then, after shaping the electromagnetic emissions, the simulation shows that the spectrum fits within the spectral mask. Full article

(This article belongs to the Special Issue Selected Papers from the 24th IEEE International Symposium on Asynchronous Circuits and Systems - ASYNC 2018)

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16 pages, 2924 KiB

Open AccessArticle

Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error Resilience

by Mini Jayakrishnan, Alan Chang and Tony Tae-Hyoung Kim

J. Low Power Electron. Appl. 2019, 9(1), 5; https://doi.org/10.3390/jlpea9010005 - 21 Jan 2019

Viewed by 6749

Abstract

Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not [...] Read more.

Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not cost effective due to the additional circuits involved. In this paper, we propose a design time resilience technique using a clock stretched flip-flop to redistribute the available slack in the processor pipeline to the critical paths. We use the opportunistic slack to redesign the critical fan in logic using logic reshaping, better than worst case sigma corner libraries and multi-bit flip-flops to achieve power and area savings. Experimental results prove that we can tune the logic and the library to get significant power and area savings of 69% and 15% in the execute pipeline stage of the processor compared to the traditional worst-case design. Whereas, existing run time resilience hardware results in 36% and 2% power and area overhead respectively. Full article

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38 pages, 1252 KiB

Open AccessArticle

Analog Architecture Complexity Theory Empowering Ultra-Low Power Configurable Analog and Mixed Mode SoC Systems

by Jennifer Hasler

J. Low Power Electron. Appl. 2019, 9(1), 4; https://doi.org/10.3390/jlpea9010004 - 21 Jan 2019

Cited by 19 | Viewed by 9049

Abstract

This discussion develops a theoretical analog architecture framework similar to the well developed digital architecture theory. Designing analog systems, whether small or large scale, must optimize their architectures for energy consumption. As in digital systems, a strong architecture theory, based on experimental results, [...] Read more.

This discussion develops a theoretical analog architecture framework similar to the well developed digital architecture theory. Designing analog systems, whether small or large scale, must optimize their architectures for energy consumption. As in digital systems, a strong architecture theory, based on experimental results, is essential for these opportunities. The recent availability of programmable and configurable analog technologies, as well as the start of analog numerical analysis, makes considering scaling of analog computation more than a purely theoretical interest. Although some aspects nicely parallel digital architecture concepts, analog architecture theory requires revisiting some of the foundations of parallel digital architectures, particularly revisiting structures where communication and memory access, instead of processor operations, that dominates complexity. This discussion shows multiple system examples from Analog-to-Digital Converters (ADC) to Vector-Matrix Multiplication (VMM), adaptive filters, image processing, sorting, and other computing directions. Full article

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9 pages, 2307 KiB

Open AccessArticle

A New Multi-Bit Flip-Flop Merging Mechanism for Power Consumption Reduction in the Physical Implementation Stage of ICs Conception

by Lekbir Cherif, Mohamed Chentouf, Jalal Benallal, Mohammed Darmi, Rachid Elgouri and Nabil Hmina

J. Low Power Electron. Appl. 2019, 9(1), 3; https://doi.org/10.3390/jlpea9010003 - 21 Jan 2019

Cited by 1 | Viewed by 7640

Abstract

Recently, the multi-bit flip-flop (MBFF) technique was introduced as a method for reducing the power consumption and chip area of integrated circuits (ICs) during the physical implementation stage of their development process. From the perspective of the consumer, the main requirements for such [...] Read more.

Recently, the multi-bit flip-flop (MBFF) technique was introduced as a method for reducing the power consumption and chip area of integrated circuits (ICs) during the physical implementation stage of their development process. From the perspective of the consumer, the main requirements for such an optimization method are high performance, low power usage and small area (PPA). Therefore, any new optimization technique should improve at least one, if not all, of these requirements. This paper proposes a new low-power methodology, applying a MBFF merging solution during the physical implementation of an IC to achieve better power consumption and area reduction. The aim of this study is to prove the benefit of this methodology on the power saving capability of the system while demonstrating that the proposed methodology does not have a negative impact on the circuit performance and design routability. The experimental results show that MBFF merging of 76% can be achieved and preserved throughout the entire physical implementation process, from cell placement to the final interconnection routing, without impacting the system’s performance or routability. Moreover, the clock wirelength, nets and buffers needed to balance the clock network were reduced by 11.98%, 3.82% and 9.16%, respectively. The reduction of the clock tree elements led to a reduction of the power consumption of the clock nets, registers and cells by 22.11%, 20.84% and 12.38%, respectively. The total power consumption of the design was reduced by 2.67%. Full article

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3 pages, 200 KiB

Open AccessEditorial

Acknowledgement to Reviewers of Journal of Low Power Electronics and Applications in 2018

by Journal of Low Power Electronics and Applications Editorial Office

J. Low Power Electron. Appl. 2019, 9(1), 2; https://doi.org/10.3390/jlpea9010002 - 16 Jan 2019

Viewed by 5516

Abstract

Rigorous peer-review is the corner-stone of high-quality academic publishing [...] Full article

11 pages, 5377 KiB

Open AccessCommunication

Modularity for Paralleling Different Rated Power Supplies Using Multi-Phase Switching Methods

by Ping-Hui Lee, Yi-Te Chiang and Fan-Ren Chang

J. Low Power Electron. Appl. 2019, 9(1), 1; https://doi.org/10.3390/jlpea9010001 - 16 Jan 2019

Cited by 1 | Viewed by 6371

Abstract

This paper proposes a modularity for paralleling different rated power supplies without adding a circuit in the feedback loop by using direct and overlapped switching methods. Unlike an isolated output diode, the use of an isolated output switch composed of two Metal-Oxide-Semiconductor Field-Effect [...] Read more.

This paper proposes a modularity for paralleling different rated power supplies without adding a circuit in the feedback loop by using direct and overlapped switching methods. Unlike an isolated output diode, the use of an isolated output switch composed of two Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) can reduce power dissipation. The control module includes switches and a micro-programmed controlled unit that realizes the modularity by using multi-phase switching methods. The proposed module was studied, and experiments of two rated power supplies (60 and 45 W) were conducted to verify the studied results. Full article

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J. Low Power Electron. Appl., Volume 9, Issue 1 (March 2019) – 12 articles

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