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18 pages, 4649 KiB

Open AccessArticle

Efficient Analysis of Noise Induced in Low-Voltage Installations Placed Inside Buildings with Lightning Protection Systems

by Artur Noga, Tomasz Topa and Tomasz P. Stefański

Electronics 2024, 13(22), 4472; https://doi.org/10.3390/electronics13224472 - 14 Nov 2024

Viewed by 327

Abstract

This paper describes an efficient approach to the broadband analysis of lightning protection systems (LPSs) using the method of moments (MoM) implemented in the frequency domain. The adaptive frequency sampling (AFS) algorithm, based on a rational interpolation of the relevant observable (e.g., voltage, [...] Read more.

This paper describes an efficient approach to the broadband analysis of lightning protection systems (LPSs) using the method of moments (MoM) implemented in the frequency domain. The adaptive frequency sampling (AFS) algorithm, based on a rational interpolation of the relevant observable (e.g., voltage, current, electric or magnetic field) which describes the properties of the LPS, is employed to reduce the number of samples computed by the full-wave MoM. This improvement is achieved by the quick comparison of two interpolants with the use of the Stöer–Bulirsch algorithm, which provides the frequency location of the next MoM samples for computations. This algorithm allows for the efficient localization of resonant frequencies while reducing the number of samples computed over the entire frequency range. In the instances when the induced noise is determined in low-voltage installations protected by various types of LPSs, reductions in computational overhead equal to 47.9× and 72.1× in broadband LPS simulations are obtained. Hence, the proposed approach allows for a significant reduction in computational overhead in comparison to standard, uniformly sampled simulations. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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22 pages, 5688 KiB

Open AccessArticle

Closing the Gap Between Electrical and Physical Design Steps with an Analog IC Placement Optimizer Enhanced with Machine-Learning-Based Post-Layout Performance Regressors

by Ricardo Martins

Electronics 2024, 13(22), 4360; https://doi.org/10.3390/electronics13224360 - 6 Nov 2024

Viewed by 415

Abstract

The design of integrated circuits in the analog spectrum is intricate due to the signals’ continuous nature. Additionally, it is strongly affected by the physical implementation of their devices and interconnections on the layout, a design task that has stubbornly defied all automation [...] Read more.

The design of integrated circuits in the analog spectrum is intricate due to the signals’ continuous nature. Additionally, it is strongly affected by the physical implementation of their devices and interconnections on the layout, a design task that has stubbornly defied all automation attempts. In this paper, one limitative factor is identified that must be addressed to finally push automation tools into the analog integrated circuit design flow: accurate assessment of post-layout performance degradation. For this purpose, a performance-driven placement generator highly integrated with off-the-shelf tools already adopted by circuit/layout designers, i.e., circuit simulator, verification tools (layout-versus-schematic) and layout extractor, is proposed. Toward maximum post-layout accuracy, this generator promotes an exhaustive simulation-based synthesis, extracting, simulating and verifying the post-layout functional behavior of every candidate floorplan. Additionally, to bypass the time-consuming extractions/simulations and accelerate synthesis, novel post-layout performance regressors based on different highly accurate machine learning techniques are also being developed. The data used to train them can be directly and conveniently acquired from previous precise post-placement simulations. Experimental results over two analog circuit structures show that a set of performance regressors based on tree-based models, while operating on compressed design spaces, allow for the speeding up of synthesis by more than 20×, which represents a step toward an efficient fully automatic performance-driven analog integrated circuit design flow. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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12 pages, 2930 KiB

Open AccessArticle

Ultrasonic A-Scan Signals Data Augmentation Using Electromechanical System Modelling to Enhance Cataract Classification Methods

by Mário J. Santos, Lorena I. Petrella, Fernando Perdigão and Jaime Santos

Electronics 2024, 13(21), 4144; https://doi.org/10.3390/electronics13214144 - 22 Oct 2024

Viewed by 497

Abstract

The use of artificial intelligence in diverse diagnosis areas has significantly increased in the past few years because of the advantages it represents in clinical routine. Among the diverse diagnostic techniques, the use of ultrasounds is often preferred because of their simplicity, low [...] Read more.

The use of artificial intelligence in diverse diagnosis areas has significantly increased in the past few years because of the advantages it represents in clinical routine. Among the diverse diagnostic techniques, the use of ultrasounds is often preferred because of their simplicity, low cost, non-invasiveness, and non-ionizing characteristic. However, obtaining an adequate number of patients and data for training and testing machine learning models is challenging. To overcome this limitation, a novel approach is proposed for simulating data produced by ultrasonic diagnostic devices. The implemented method was based on a clinical prototype for eye cataract diagnosis, although the method can be extended to other applications as well. The proposed model encompasses the electric-to-acoustic signal conversion in the ultrasonic transducer, the wave propagation through the biological medium, and the subsequent acoustic-to-electric signal conversion in the transducer. Electrical modelling of the transducer was performed using a two-port network approach, while the acoustic wave propagation was modelled by using the k-Wave MATLAB toolbox. It was verified that the holistic modelling approach enabled the generation of synthetic data augmentation, presenting high similarity with real data. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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16 pages, 5336 KiB

Open AccessArticle

A Control Strategy for Suppressing Zero-Crossing Current of Single-Phase Half-Bridge Active Neutral-Point-Clamped Three-Level Inverter

by Gi-Young Lee, Chul-Min Kim, Jungho Han and Jong-Soo Kim

Electronics 2024, 13(19), 3929; https://doi.org/10.3390/electronics13193929 - 4 Oct 2024

Viewed by 615

Abstract

Multi-level inverters have characteristics suitable for high-voltage and high-power applications through various topology configurations. These reduce harmonic distortion and improve the quality of the output waveform by generating a multi-level output voltage waveform. In particular, an active neutral-point-clamped topology is one of the [...] Read more.

Multi-level inverters have characteristics suitable for high-voltage and high-power applications through various topology configurations. These reduce harmonic distortion and improve the quality of the output waveform by generating a multi-level output voltage waveform. In particular, an active neutral-point-clamped topology is one of the multi-level inverters advantageous for high-power and medium-voltage applications. It has the advantage of controlling the output waveform more precisely by actively clamping the neutral point using an active switch and diode. However, it has a problem, which is that an unwanted zero-crossing current may occur if an inaccurate switching signal is applied at the time when the polarity of the output voltage changes. In this paper, a control strategy to suppress the zero-crossing current of a single-phase half-bridge three-level active neutral-point-clamped inverter is proposed. The operating principle of a single-phase half-bridge three-level active neutral-point-clamped inverter is identified through an operation mode analysis. In addition, how the switching signal is reflected in an actual digital signal processor is analyzed to determine the situation in which the zero-crossing current occurs. Through this, a control strategy capable of suppressing zero-crossing current is designed. The proposed method prevents a zero-crossing current by appropriately modifying the update timing of reference voltages at the point where the polarity of the output changes. The validity of the proposed method is verified through simulation and experiments. Based on the proposed method, the total harmonic distortion of the output current is significantly reduced from 12.15% to 4.59% in a full-load situation. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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12 pages, 570 KiB

Open AccessArticle

Toward Memory-Efficient Analog Design Using Precomputed Lookup Tables

by Hesham Omran

Electronics 2024, 13(18), 3776; https://doi.org/10.3390/electronics13183776 - 23 Sep 2024

Viewed by 1721

Abstract

Analog design productivity remains a challenge in the digitally driven semiconductor chip design field. Knowledge-based and simulation-based analog automation approaches have not achieved widespread acceptance in the analog design community. Systematic analog design using precomputed lookup tables (LUTs) is a promising approach that [...] Read more.

Analog design productivity remains a challenge in the digitally driven semiconductor chip design field. Knowledge-based and simulation-based analog automation approaches have not achieved widespread acceptance in the analog design community. Systematic analog design using precomputed lookup tables (LUTs) is a promising approach that can address the design productivity challenge. Although modern computing systems have powerful memory capabilities, which make the LUT approach viable, reducing the memory footprint of the LUTs remains a challenge. A memory-efficient design technique using LUTs is proposed by using an incomplete grid in the MOSFET degrees-of-freedom (DoFs) space. An efficient indexing technique for the incomplete grid is also proposed, using a precomputed offset array in various scenarios, such as two-sided constraints and three-dimensional LUTs. The results show that the proposed technique can achieve up to a 67% reduction in memory footprint, in addition to improving LUT generation time and query performance. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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21 pages, 11854 KiB

Open AccessArticle

Design of High-Reliability Low-Dropout Regulator Combined with Silicon Controlled Rectifier-Based Electrostatic Discharge Protection Circuit Using Dynamic Dual Buffer

by U-Yeol Seo, Sang-Wook Kwon, Dong-Hyeon Kim, Jae-Yoon Oh, Min-Seo Kim and Yong-Seo Koo

Electronics 2024, 13(15), 3016; https://doi.org/10.3390/electronics13153016 - 31 Jul 2024

Viewed by 856

Abstract

Overshoot and undershoot caused by the current load impact the accuracy of the required output voltage and circuit performance. The transient response issue in existing low-dropout (LDO) regulators is a dynamic specification that must be addressed at the design stage. This transient response [...] Read more.

Overshoot and undershoot caused by the current load impact the accuracy of the required output voltage and circuit performance. The transient response issue in existing low-dropout (LDO) regulators is a dynamic specification that must be addressed at the design stage. This transient response is influenced by system parameters such as stability and gain. The LDO regulator suggested in this study is designed to minimize the change in output voltage by considerably enhancing the gain using a dynamic dual buffer structure. A dynamic dual buffer is utilized to effectively control undershoot and overshoot. Under the conditions that the input voltage range is from 3.3 to 4.5 V, the maximum load current is 300 mA, the output voltage is 3 V, and the output of the proposed LDO regulator with the dynamic dual buffer structure has undershoot and overshoot voltages of 41 mV and 31 mV, respectively. That is, the output voltage of the proposed LDO regulator effectively provided and discharged an additional current suited for the undershoot/overshoot conditions to enhance the transient response characteristics. Furthermore, the electrostatic discharge (ESD) robustness characteristics of the proposed LDO regulator improved because of the silicon-controlled rectifier underlying the ESD protection device embedded in the output node and power line. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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13 pages, 5244 KiB

Open AccessFeature PaperArticle

Proposal of an External Remote Sensing Circuitry for Switching-Mode Power Supplies

by George Catalin Salavarin, Vlad-Mihai Placinta and Cristian Ravariu

Electronics 2024, 13(15), 2994; https://doi.org/10.3390/electronics13152994 - 29 Jul 2024

Viewed by 721

Abstract

This work proposes a low-cost and easy-to-implement solution for a remote voltage-sensing circuitry that can be used to ensure stability and good voltage regulation in applications with power supplies driving currents over long paths. The circuitry is implemented with general-purpose electronic components and [...] Read more.

This work proposes a low-cost and easy-to-implement solution for a remote voltage-sensing circuitry that can be used to ensure stability and good voltage regulation in applications with power supplies driving currents over long paths. The circuitry is implemented with general-purpose electronic components and is provided as an external feature to be attached to power supplies without remote sensing. To demonstrate its capabilities, a test bench was put together alongside a power supply module which has local sensing only. With the test bench, the output voltage from the power supply was delivered in various scenarios to an electronic load. Multiple parameters were monitored in order to assess the power supply performance to which the proposed remote voltage-sensing circuitry is attached. The measurements include stability and transient response tests, and the results were compared with the ones obtained with the standard local sensing. The tests reveal that the power supply module kept its output voltage stable with less than +/−10% voltage variation, and the average transient recovery time was less than 100 µs. The results are given for two different output voltage values of 1.2 V and 3.3 V and at high current capabilities of 3.5 A. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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32 pages, 12799 KiB

Open AccessArticle

Day/Night Power Generator Station: A New Power Generation Approach for Lunar and Martian Space Exploration

by Thomas F. Arciuolo, Miad Faezipour and Xingguo Xiong

Electronics 2024, 13(14), 2859; https://doi.org/10.3390/electronics13142859 - 19 Jul 2024

Viewed by 878

Abstract

In the not-too-distant future, humans will return to the Moon and step foot for the first time on Mars. Eventually, humanity will colonize these celestial bodies, where living and working will be commonplace. Energy is fundamental to all life. The energy that people [...] Read more.

In the not-too-distant future, humans will return to the Moon and step foot for the first time on Mars. Eventually, humanity will colonize these celestial bodies, where living and working will be commonplace. Energy is fundamental to all life. The energy that people use to sustain themselves on Earth, and in particular on these other worlds, is the integrated, safe production of electrical power, day and night. This paper proposes a radically new solution to this problem: Solar Tracking by day and a Solar Rechargeable Calcium Oxide Chemical Thermoelectric Reactor by night. Called the “Robotic End Effector for Lunar and Martian Geological Exploration of Space” (REEGES) Day/Night Power Generator Station, this form of thermoelectric power generation is mathematically modeled, simulation is performed, and a concept model design is demonstrated in this paper. The results of the presented simulation show the maximum total system output capability is 9.89 V, 6.66 A, and 65.9 W, with an operating time of up to 12 h, through a scalable design. This research provides instructions to the Space Research Community on a complete and novel development methodology for creating fully customized, configurable, safe, and reliable solar/thermoelectric day/night power generators, specifically meant for use on the Moon and Mars, using the Proportional-Integral-Derivative++ (PID++) Humanoid Motion Control Algorithm for its operation on a computationally lightweight microcontroller. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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13 pages, 409 KiB

Open AccessArticle

An Efficient Checkpoint Strategy for Federated Learning on Heterogeneous Fault-Prone Nodes

by Jeonghun Kim and Sunggu Lee

Electronics 2024, 13(6), 1007; https://doi.org/10.3390/electronics13061007 - 7 Mar 2024

Viewed by 1005

Abstract

Federated learning (FL) is a distributed machine learning method in which client nodes train deep neural network models locally using their own training data and then send that trained model to a server, which then aggregates all of the trained models into a [...] Read more.

Federated learning (FL) is a distributed machine learning method in which client nodes train deep neural network models locally using their own training data and then send that trained model to a server, which then aggregates all of the trained models into a globally trained model. This protects personal information while enabling machine learning with vast amounts of data through parallel learning. Nodes that train local models are typically mobile or edge devices from which data can be easily obtained. These devices typically run on batteries and use wireless communication, which limits their power, making their computing performance and reliability significantly lower than that of high-performance computing servers. Therefore, training takes a long time, and if something goes wrong, the client may have to start training again from the beginning. If this happens frequently, the training of the global model may slow down and the final performance may deteriorate. In a general computing system, a checkpointing method can be used to solve this problem, but applying an existing checkpointing method to FL may result in excessive overheads. This paper proposes a new FL method for situations with many fault-prone nodes that efficiently utilizes checkpoints. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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16 pages, 648 KiB

Open AccessArticle

A Low-Power Analog Integrated Euclidean Distance Radial Basis Function Classifier

by Vassilis Alimisis, Christos Dimas and Paul P. Sotiriadis

Electronics 2024, 13(5), 921; https://doi.org/10.3390/electronics13050921 - 28 Feb 2024

Cited by 2 | Viewed by 1291

Abstract

This study introduces a low-power analog integrated Euclidean distance radial basis function classifier. The high-level architecture is composed of several Manhattan distance circuits in connection with a current comparator circuit. Notably, each implementation was designed with modularity and scalability in mind, effectively accommodating [...] Read more.

This study introduces a low-power analog integrated Euclidean distance radial basis function classifier. The high-level architecture is composed of several Manhattan distance circuits in connection with a current comparator circuit. Notably, each implementation was designed with modularity and scalability in mind, effectively accommodating variations in the classification parameters. The proposed classifier’s operational principles are meticulously detailed, tailored for low-power, low-voltage, and fully tunable implementations, specifically targeting biomedical applications. This design methodology materialized within a 90 nm CMOS process, utilizing the Cadence IC Suite for the comprehensive management of both the schematic and layout design aspects. During the verification phase, post-layout simulation results were meticulously cross-referenced with software-based classifier implementations. Also, a comparison study with related analog classifiers is provided. Through the simulation results and comparative study, the design architecture’s accuracy and sensitivity were effectively validated and confirmed. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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20 pages, 1549 KiB

Open AccessArticle

A Tunable Foreground Self-Calibration Scheme for Split Successive-Approximation Register Analog-to-Digital Converter

by Joonsung Park, Jiwon Lee, Jacob A. Abraham and Byoungho Kim

Electronics 2024, 13(4), 755; https://doi.org/10.3390/electronics13040755 - 13 Feb 2024

Viewed by 1049

Abstract

The capacitor mismatch among diverse defects caused by variations in the manufacturing process significantly affects the linearity of the capacitor array used to implement the capacitive digital-to-analog converter (CDAC) in the successive-approximation register (SAR) analog-to-digital converter (ADC). Accordingly, the linearity of the SAR [...] Read more.

The capacitor mismatch among diverse defects caused by variations in the manufacturing process significantly affects the linearity of the capacitor array used to implement the capacitive digital-to-analog converter (CDAC) in the successive-approximation register (SAR) analog-to-digital converter (ADC). Accordingly, the linearity of the SAR ADC is limited by that of capacitor array, resulting in serious yield loss. This paper proposes an efficient foreground self-calibration technique to enhance the linearity of the SAR ADCs by mitigating the capacitor mismatch based on the split ADC architecture along with variable capacitors. In this work, two ADC channels (i.e., ADC1 and ADC2) for the split ADC architecture include their capacitive DACs (CDACs) whose binary-weighted capacitor arrays consist of variable capacitors. A charge-sharing SAR ADC is used for each ADC channel. In the normal operation mode, their digital outputs are averaged to be the final ADC output, as in a conventional split ADC. In the calibration mode, every single binary-weighted capacitor for the two ADCs is sequentially calibrated by making parallel or/and antiparallel connection among two or thee capacitors from the two channels. For instance, because the capacitors of the CDACs ideally exhibit the binary-weighted relation as

C_{n} = 2 \times C_{n - 1}

, the variable capacitor

C_{n}

of ADC1 can be updated to be closest to the sum of

C_{n - 1}

of ADC1 and

C_{n - 1}

of ADC2 for the calibration. For the process, the two capacitor arrays of the two ADCs can be reconfigured to be connected to each other, so that the

C_{n}

of ADC1 can be connected with two of the

C_{n - 1}

of ADC1 and ADC2 in antiparallel. The two voltages at the top and the bottom plates of the CDAC are compared by a comparator of ADC1, and the comparison results are used to update

C_{n}

. This process is iterated, until

C_{n}

is in agreement with the sum of two of

C_{n - 1}

. Finally, all the capacitors can be calibrated in this way to have the binary-weighted relation. The simulation results based on the proposed work with a split SAR ADC model verified that the proposed technique can be practically used, by showing that the total harmonic distortion and the signal-to-noise-and-distortion ratio were enhanced by

21.8

dB and

6.4

dB, respectively. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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16 pages, 5232 KiB

Open AccessFeature PaperArticle

An Integrated Charge Pump for Phase-Locked Loop Applications in Harsh Environments

by Marco Mestice, Gabriele Ciarpi, Daniele Rossi and Sergio Saponara

Electronics 2024, 13(4), 744; https://doi.org/10.3390/electronics13040744 - 13 Feb 2024

Cited by 1 | Viewed by 1262

Abstract

Among all the functions that electronics currently perform, clock synthesis has a backbone role. Charge pump phase-locked loops (CP-PLL) are widely used to accomplish clock synthesis thanks to their versatility. One of the most critical parts of CP-PLLs is the charge pump, which [...] Read more.

Among all the functions that electronics currently perform, clock synthesis has a backbone role. Charge pump phase-locked loops (CP-PLL) are widely used to accomplish clock synthesis thanks to their versatility. One of the most critical parts of CP-PLLs is the charge pump, which greatly influences the system’s performance. Even though several high-performance charge pumps have been proposed in the past, with the quick spread of electronics in all the engineering fields, the design of such electronic devices has encountered several additional challenges dictated by external environmental conditions. Examples of these engineering sectors are space, aerospace, industrial, and automotive applications, where the charge pump has to face high environmental temperatures and radiation effects. As a consequence, its design and experimental characterization have to be performed to ensure reliability when operating in harsh conditions. However, to the best of the authors’ knowledge, no works in the literature have ever presented a complete charge pump design and characterization in such harsh environments. Therefore, to fill this gap, this paper presents a charge pump for PLL applications specifically designed to reach operating temperatures up to 200 °C and total ionizing dose levels up to 100 Mrad. All design choices have been experimentally verified and are discussed throughout the paper in detail. With the proposed design, we obtained an output current variation of less than 8% at 200 °C and less than 2.5% at 100 Mrad. As opposed to the CPs that can be found in the literature, these results were measured on silicon. The performed measurements confirm that the current variation at 200 °C is better than that of the state-of-the-art CPs operating at lower temperatures, which, moreover, were only simulated. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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26 pages, 1290 KiB

Open AccessArticle

Body Biasing Techniques for Dynamic Comparators: A Systematic Survey

by Valerio Spinogatti, Riccardo Della Sala, Cristian Bocciarelli, Francesco Centurelli and Alessandro Trifiletti

Electronics 2024, 13(4), 711; https://doi.org/10.3390/electronics13040711 - 9 Feb 2024

Viewed by 1628

Abstract

Forward body biasing (FBB) has often been exploited in the literature for improving the performance of both analog and digital building blocks. Recent works have explored the application of FBB variants to mixed-signal electronics and in particular to dynamic comparators, where these techniques [...] Read more.

Forward body biasing (FBB) has often been exploited in the literature for improving the performance of both analog and digital building blocks. Recent works have explored the application of FBB variants to mixed-signal electronics and in particular to dynamic comparators, where these techniques can help to relax the trade-off between speed and power consumption at medium and low supply voltages. However, the literature lacks a structured analysis of the solutions that have been developed and of the trade-offs that affect them. This work attempts to fill the gap by providing a survey of the application of FBB techniques to dynamic comparators. The analysis focuses on the two most popular dynamic comparator topologies, the Strong Arm latch and Elzakker’s comparator. Several FBB variants are examined from a theoretical point of view. Moreover, the benefits and the limitations of the different approaches are assessed in terms of the main figures of merit through a systematic campaign of simulations in a 55 nm CMOS technology. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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17 pages, 8800 KiB

Open AccessArticle

A Linear Multi-Band Voltage-Controlled Oscillator with Process Compensation for SerDes Applications

by Panagiotis Bertsias, Andreas Tsimpos and George Souliotis

Electronics 2024, 13(3), 581; https://doi.org/10.3390/electronics13030581 - 31 Jan 2024

Viewed by 1300

Abstract

A new voltage-controlled oscillator (VCO) topology for serializer–deserializer (SerDes) applications is proposed in this paper. The topology is suitable for SATA, PCI Express, and USB 3 protocols. The VCO is based on two-ring oscillator cores and operates in several frequency bands, as required [...] Read more.

A new voltage-controlled oscillator (VCO) topology for serializer–deserializer (SerDes) applications is proposed in this paper. The topology is suitable for SATA, PCI Express, and USB 3 protocols. The VCO is based on two-ring oscillator cores and operates in several frequency bands, as required by the corresponding protocol specifications, with a constant VCO gain and improved linear control over the frequency tuning. Additionally, it is supported by an automatic digital compensation mechanism for process variations. The VCO has been designed to cover the several speeds of the SATA and PCI Express protocols, with optimized performance in all of them, including the current consumption, the phase noise, and the frequency tuning in each case. Designed in a CMOS 22 nm technology node with a 0.8 V supply voltage, it can achieve, at 3 GHz frequency, a phase noise better than −90 dBc/Hz at 1 MHz offset and an average power consumption equal to 3.84 mW. Extended digital control can set optimized configurations for phase noise, current consumption, and VCO gain vs. process variations. Extensive post-layout simulation results verify the superior performance. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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12 pages, 1763 KiB

Open AccessArticle

Issues and New Results on Bandpass Sampling

by Chiman Kwan

Electronics 2024, 13(2), 280; https://doi.org/10.3390/electronics13020280 - 8 Jan 2024

Cited by 3 | Viewed by 1055

Abstract

This study presents issues and new results on bandpass sampling. First, some issues on the relationships between the range of allowable sampling frequencies and the guard bands are highlighted. The root cause of these issues was determined. Second, given a specified sampling frequency [...] Read more.

This study presents issues and new results on bandpass sampling. First, some issues on the relationships between the range of allowable sampling frequencies and the guard bands are highlighted. The root cause of these issues was determined. Second, given a specified sampling frequency tolerance and the guard bands for carrier frequency tolerance, a new and simple formula for determining the maximum integer, which is a key number in determining the allowable range of sampling frequencies, has been derived. Two numerical examples were used to demonstrate the above issues and new results. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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16 pages, 969 KiB

Open AccessArticle

Scalable Data Concentrator with Baseline Interconnection Network for Triggerless Data Acquisition Systems

by Wojciech Marek Zabołotny

Electronics 2024, 13(1), 81; https://doi.org/10.3390/electronics13010081 - 23 Dec 2023

Viewed by 1345

Abstract

Triggerless data acquisition systems (DAQs) require that the data stream is transmitted from multiple links and into the processing node. The short input data words must be concentrated and packed into the longer bit vectors the output interface (e.g., PCI Express) uses. In [...] Read more.

Triggerless data acquisition systems (DAQs) require that the data stream is transmitted from multiple links and into the processing node. The short input data words must be concentrated and packed into the longer bit vectors the output interface (e.g., PCI Express) uses. In that process, the unneeded data must be eliminated, and a dense stream of useful DAQ data must be created. Additionally, the time order of the data should be preserved. This paper presents a new solution using the Baseline Network with Reversed Outputs (BNRO) for high-speed data routing. A thorough analysis of the network’s operation enabled increased scalability compared to the previously published concentrator based on an 8 × 8 network. The solution may be scaled by adding additional layers to the BNRO network while minimizing resource consumption. Simulations were performed for four and five layers (16 and 32 inputs). The FPGA implementation and tests in the actual hardware were successfully performed for 16 inputs. The pipeline registers may be added in each layer independently, shortening the critical path and increasing the maximum acceptable clock frequency. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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22 pages, 5219 KiB

Open AccessArticle

Real-Time Implementation of a Frequency Shifter for Enhancement of Heart Sounds Perception on VLIW DSP Platform

by Vincenzo Muto, Emilio Andreozzi, Carmela Cappelli, Jessica Centracchio, Gennaro Di Meo, Daniele Esposito, Paolo Bifulco and Davide De Caro

Electronics 2023, 12(20), 4359; https://doi.org/10.3390/electronics12204359 - 20 Oct 2023

Cited by 2 | Viewed by 1401

Abstract

Auscultation of heart sounds is important to perform cardiovascular assessment. External noises may limit heart sound perception. In addition, heart sound bandwidth is concentrated at very low frequencies, where the human ear has poor sensitivity. Therefore, the acoustic perception of the operator can [...] Read more.

Auscultation of heart sounds is important to perform cardiovascular assessment. External noises may limit heart sound perception. In addition, heart sound bandwidth is concentrated at very low frequencies, where the human ear has poor sensitivity. Therefore, the acoustic perception of the operator can be significantly improved by shifting the heart sound spectrum toward higher frequencies. This study proposes a real-time frequency shifter based on the Hilbert transform. Key system components are the Hilbert transformer implemented as a Finite Impulse Response (FIR) filter, and a Direct Digital Frequency Synthesizer (DDFS), which allows agile modification of the frequency shift. The frequency shifter has been implemented on a VLIW Digital Signal Processor (DSP) by devising a novel piecewise quadratic approximation technique for efficient DDFS implementation. The performance has been compared with other DDFS implementations both considering piecewise linear technique and sine/cosine standard library functions of the DSP. Piecewise techniques allow a more than 50% reduction in execution time compared to the DSP library. Piecewise quadratic technique also allows a more than 50% reduction in total required memory size in comparison to the piecewise linear. The theoretical analysis of the dynamic power dissipation exhibits a more than 20% reduction using piecewise techniques with respect to the DSP library. The real-time operation has been also verified on the DSK6713 rapid prototyping board by Texas Instruments C6713 DSP. Audiologic tests have also been performed to assess the actual improvement of heart sound perception. To this aim, heart sound recordings were corrupted by additive white Gaussian noise, crowded street noise, and helicopter noise, with different signal-to-noise ratios. All recordings were collected from public databases. Statistical analyses of the audiological test results confirm that the proposed approach provides a clear improvement in heartbeat perception in noisy environments. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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28 pages, 1185 KiB

Open AccessArticle

General Methodology for the Design of Bell-Shaped Analog-Hardware Classifiers

by Vassilis Alimisis, Nikolaos P. Eleftheriou, Argyro Kamperi, Georgios Gennis, Christos Dimas and Paul P. Sotiriadis

Electronics 2023, 12(20), 4211; https://doi.org/10.3390/electronics12204211 - 11 Oct 2023

Cited by 5 | Viewed by 1186

Abstract

This study introduces a general methodology for the design of analog integrated bell-shaped classifiers. Each high-level architecture is composed of several Gaussian function circuits in conjunction with a Winner-Take-All circuit. Notably, each implementation is designed with modularity and scalability in mind, effectively accommodating [...] Read more.

This study introduces a general methodology for the design of analog integrated bell-shaped classifiers. Each high-level architecture is composed of several Gaussian function circuits in conjunction with a Winner-Take-All circuit. Notably, each implementation is designed with modularity and scalability in mind, effectively accommodating variations in classification parameters. The operating principles of each classifier are illustrated in detail and are used in low-power, low-voltage, and fully tunable implementations targeting biomedical applications. The realization of this design methodology occurred within a 90 nm CMOS process, leveraging the Cadence IC suite for both electrical and layout design aspects. In the verification phase, post-layout simulation outcomes were meticulously compared against software-based implementations of each classifier. Through the simulation results and comparison study, the design methodology is confirmed in terms of accuracy and sensitivity. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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13 pages, 4668 KiB

Open AccessArticle

A Universal-Verification-Methodology-Based Testbench for the Coverage-Driven Functional Verification of an Instruction Cache Controller

by Cong Liu, Xinyu Xu, Zhenjiao Chen and Binghao Wang

Electronics 2023, 12(18), 3821; https://doi.org/10.3390/electronics12183821 - 9 Sep 2023

Cited by 1 | Viewed by 2551

Abstract

The Cache plays an important role in computer architecture by reducing the access time of the processor and improving its performance. The hardware design of the Cache is complex and it is challenging to verify its functions, so the traditional Verilog-based verification method [...] Read more.

The Cache plays an important role in computer architecture by reducing the access time of the processor and improving its performance. The hardware design of the Cache is complex and it is challenging to verify its functions, so the traditional Verilog-based verification method is no longer applicable. This paper proposes a comprehensive and efficient verification testbench based on the SystemVerilog language and universal verification methodology (UVM) for an instruction Cache (I-Cache) controller. Corresponding testcases are designed for each feature of the I-Cache controller and automatically executed using a python script on an electronic design automation (EDA) tool. After simulating a large number of testcases, the statistics reveal that the module’s code coverage is 99.13%. Additionally, both the function coverage and the assertion coverage of the module reach 100%. Our results demonstrate that these coverage metrics meet the requirements and ensure the thoroughness of function verification. Furthermore, the established verification testbench exhibits excellent scalability and reusability, making it easily applicable to higher-level verification scenarios. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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16 pages, 4974 KiB

Open AccessArticle

A Master Multi-Slave System Based on Structural Modal Frequencies

by Alfiero Leoni, Gianluca Barile, Paolo Esposito, Romina Paolucci, Vincenzo Stornelli and Giuseppe Ferri

Electronics 2023, 12(15), 3260; https://doi.org/10.3390/electronics12153260 - 29 Jul 2023

Viewed by 1425

Abstract

Structural Health Monitoring (SHM) is a process where, through sensors-based electronic systems and output data analysis, the structural integrity of a building or an infrastructure is observed and determined through periodically sampled measurements for material and geometric variations, ensuring safety and minimizing risk [...] Read more.

Structural Health Monitoring (SHM) is a process where, through sensors-based electronic systems and output data analysis, the structural integrity of a building or an infrastructure is observed and determined through periodically sampled measurements for material and geometric variations, ensuring safety and minimizing risk factors. Over the years, the approach to this problem evolved both in terms of system technology, with the use of more accurate sensors, and the parameters used to determine the building status, i.e., the extraction of the damage index. In these terms, structural modal harmonics-based analysis is acquiring more and more relevance. In this paper, we propose a fully custom master multi-slave system used for SHM purposes, capable of acquiring data from six different channels coming from two independent accelerometers suitably configured as to synchronously produce spectrograms and static trim of the monitored structure. A test of the system has been performed on a modular structure subject to random perturbation. Time and frequency domain results were analyzed before and after structural alterations. Their effects were studied in a 500 Hz bandwidth, showing a drift in the resonant frequency of the structure from 145 Hz to 152 Hz, and, additionally, a harmonic displacement: medium-frequency components experienced a 50 Hz drift, while low-frequency components collapsed into two harmonics at 60 Hz and 90 Hz. These tests proved the system’s functionality and the feasibility of this method for structural integrity analysis and, eventually, damage evaluation. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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20 pages, 658 KiB

Open AccessArticle

Simple and Accurate Model for the Propagation Delay in MCML Gates

by Gianluca Giustolisi, Giuseppe Scotti and Gaetano Palumbo

Electronics 2023, 12(12), 2680; https://doi.org/10.3390/electronics12122680 - 15 Jun 2023

Viewed by 1702

Abstract

In this article, we develop a simple and accurate model for evaluating the propagation delay in MOS Current-Mode Logic (MCML) gates. The model describes the behavior of MCML gates in a linear fashion despite the circuits themselves being non-linear. Indeed, we demonstrate that [...] Read more.

In this article, we develop a simple and accurate model for evaluating the propagation delay in MOS Current-Mode Logic (MCML) gates. The model describes the behavior of MCML gates in a linear fashion despite the circuits themselves being non-linear. Indeed, we demonstrate that a linear model can be used, provided that, for each small-signal parameter, its average value calculated between the two different switching logic states is used. The proposed model is validated through simulations of MCML universal gates designed using modern nanometer processes. The model forecasts simulated values with an error lower than 4% and 20% in 65-nm standard CMOS and 28-nm Fully-Depleted Silicon-On-Insulator (FD-SOI), respectively. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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14 pages, 1419 KiB

Open AccessArticle

A Wireless, Battery-Powered Probe Based on a Dual-Tier CMOS SPAD Array for Charged Particle Sensing

by Joana Minga, Paolo Brogi, Gianmaria Collazuol, Gian-Franco Dalla Betta, Pier Simone Marrocchesi, Fabio Morsani, Lucio Pancheri, Lodovico Ratti, Gianmarco Torilla and Carla Vacchi

Electronics 2023, 12(11), 2549; https://doi.org/10.3390/electronics12112549 - 5 Jun 2023

Cited by 3 | Viewed by 1731

Abstract

A compact probe for charged particle imaging, with potential applications in source activity mapping and radio-guided surgery was designed and tested. The development of this technology holds significant implications for medical imaging, offering healthcare professionals accurate and efficient tools for diagnoses and treatments. [...] Read more.

A compact probe for charged particle imaging, with potential applications in source activity mapping and radio-guided surgery was designed and tested. The development of this technology holds significant implications for medical imaging, offering healthcare professionals accurate and efficient tools for diagnoses and treatments. To fulfill the portability requirements of these applications, the probe was designed for battery operation and wireless communication with a PC. The core sensor is a dual-layer CMOS SPAD detector, fabricated using 150 nm technology, which uses overlapping cells to produce a coincidence signal and reduce the dark count rate (DCR). The sensor is managed and interfaced with a microcontroller, and custom firmware was developed to facilitate communication with the sensor. The performance of the probe was evaluated by characterizing the on-board SPAD detector in terms of the DCR, and the results were consistent with the characterization measurements taken on the same chip samples using a purposely developed benchtop setup. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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18 pages, 10546 KiB

Open AccessFeature PaperArticle

Elucidation of Response and Electrochemical Mechanisms of Bio-Inspired Rubber Sensors with Supercapacitor Paradigm

by Kunio Shimada

Electronics 2023, 12(10), 2304; https://doi.org/10.3390/electronics12102304 - 19 May 2023

Cited by 1 | Viewed by 1361

Abstract

The electrochemical paradigm of a supercapacitor (SC) is effective for investigating cutting-edge deformable and haptic materials made of magnetic compound fluid (MCF) rubber in order to advance the production of bio-inspired sensors as artificial haptic sensors mimicking human tissues. In the present study, [...] Read more.

The electrochemical paradigm of a supercapacitor (SC) is effective for investigating cutting-edge deformable and haptic materials made of magnetic compound fluid (MCF) rubber in order to advance the production of bio-inspired sensors as artificial haptic sensors mimicking human tissues. In the present study, we measure the cyclic voltammetry (CV) profiles and electric properties with electrochemical impedance spectroscopy (EIS) to morphologically evaluate the intrinsic structure of MCF rubber containing fillers and agents. In addition, the electrochemical mechanisms of molecule and particle behavior are theorized using the SC physical framework. The solid-doped fillers in the MCF rubber characterized the behavior of the electrical double-layer capacitor (EDLC). Meanwhile, the liquid agents showed the characteristics of a pseudocapacitor (PC) due to the redox response among the molecules and particles. The potential responses to extraneous stimuli relevant to the EIS properties, categorized as slow adaption (SA), fast adaption (FA), and other type (OT), were also analyzed in terms of the sensory response of the bio-inspired sensor. The categories were based on how the response was induced from the EIS properties. By controlling the EIS properties with different types of doping agents, sensors with various sensory responses become feasible. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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13 pages, 1895 KiB

Open AccessArticle

Analysis of Doherty Power Amplifier Matching Assisted by Physics-Based Device Modelling

by Simona Donati Guerrieri, Eva Catoggio and Fabrizio Bonani

Electronics 2023, 12(9), 2101; https://doi.org/10.3390/electronics12092101 - 4 May 2023

Cited by 2 | Viewed by 1829

Abstract

The Doherty Power Amplifier represents one of the most promising solutions for the design of high-efficiency power stages. In the widely adopted ABC scheme, the Doherty Amplifier design critically depends on the accuracy of the device model in different operating conditions, ranging from [...] Read more.

The Doherty Power Amplifier represents one of the most promising solutions for the design of high-efficiency power stages. In the widely adopted ABC scheme, the Doherty Amplifier design critically depends on the accuracy of the device model in different operating conditions, ranging from class AB to class C. For the class C case, library models are often inaccurate, while experimental characterization is difficult since it must be carried out in large signal conditions and with varying gate bias. In this paper, we propose an alternative approach, based on physics-based Technological CAD (TCAD) simulations of the complete Doherty amplifier along with the analysis of its individual MAIN (class AB) and AUXILIARY (class C) stages. TCAD simulations seamlessly provide an accurate modelling of the device behavior in all operation classes, including the device turn-on and the nonlinear capacitances, and easily account for the cross-loading effects of the MAIN and AUXILIARY devices through the output network and the effect of the device feedback (gate-drain) capacitance on the input matching. Analyzing a GaAs Doherty stage at 12 GHz, we show that the input phase of the auxiliary stage can be exploited for the Doherty power amplifier optimization in terms of gain, linearity and efficiency, showing a 9 dB gain with less than 1 dB gain variation from back-off to peak power with a power-added efficiency exceeding 45% over a Doherty region extending to a more than 6 dB output power back-off. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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17 pages, 4065 KiB

Open AccessArticle

Parameter Identification of Li-ion Batteries: A Comparative Study

by Shahenda M. Abdelhafiz, Mohammed E. Fouda and Ahmed G. Radwan

Electronics 2023, 12(6), 1478; https://doi.org/10.3390/electronics12061478 - 21 Mar 2023

Cited by 4 | Viewed by 2439

Abstract

Lithium-ion batteries are crucial building stones in many applications. Therefore, modeling their behavior has become necessary in numerous fields, including heavyweight ones such as electric vehicles and plug-in hybrid electric vehicles, as well as lightweight ones like sensors and actuators. Generic models are [...] Read more.

Lithium-ion batteries are crucial building stones in many applications. Therefore, modeling their behavior has become necessary in numerous fields, including heavyweight ones such as electric vehicles and plug-in hybrid electric vehicles, as well as lightweight ones like sensors and actuators. Generic models are in great demand for modeling the current change over time in real-time applications. This paper proposes seven dynamic models to simulate the behavior of lithium-ion batteries discharging. This was achieved using NASA room temperature random walk discharging datasets. The efficacy of these models in fitting different time-domain responses was tested through parameter identification with the Marine Predator Algorithm (MPA). In addition, each model’s term’s impact was analyzed to understand its effect on the fitted curve. The proposed models show an average absolute normalized error as low as

0.0057

. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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11 pages, 8567 KiB

Open AccessCommunication

An Encryption Application and FPGA Realization of a Fractional Memristive Chaotic System

by Sara M. Mohamed, Wafaa S. Sayed, Ahmed H. Madian, Ahmed G. Radwan and Lobna A. Said

Electronics 2023, 12(5), 1219; https://doi.org/10.3390/electronics12051219 - 3 Mar 2023

Cited by 27 | Viewed by 2216

Abstract

The work in this paper extends a memristive chaotic system with transcendental nonlinearities to the fractional-order domain. The extended system’s chaotic properties were validated through bifurcation analysis and spectral entropy. The presented system was employed in the substitution stage of an image encryption [...] Read more.

The work in this paper extends a memristive chaotic system with transcendental nonlinearities to the fractional-order domain. The extended system’s chaotic properties were validated through bifurcation analysis and spectral entropy. The presented system was employed in the substitution stage of an image encryption algorithm, including a generalized Arnold map for the permutation. The encryption scheme demonstrated its efficiency through statistical tests, key sensitivity analysis and resistance to brute force and differential attacks. The fractional-order memristive system includes a reconfigurable coordinate rotation digital computer (CORDIC) and Grünwald–Letnikov (GL) architectures, which are essential for trigonometric and hyperbolic functions and fractional-order operator implementations, respectively. The proposed system was implemented on the Artix-7 FPGA board, achieving a throughput of 0.396 Gbit/s. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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31 pages, 481 KiB

Open AccessArticle

Improving the Spatial Characteristics of Three-Level LUT-Based Mealy FSM Circuits

by Alexander Barkalov, Larysa Titarenko, Małgorzata Mazurkiewicz and Kazimierz Krzywicki

Electronics 2023, 12(5), 1133; https://doi.org/10.3390/electronics12051133 - 26 Feb 2023

Viewed by 1580

Abstract

The main purpose of the method proposed in this article is to reduce the number of look-up-table (LUT) elements in logic circuits of sequential devices. The devices are represented by models of Mealy finite state machines (FSMs). Thesee are so-called MPY FSMs based [...] Read more.

The main purpose of the method proposed in this article is to reduce the number of look-up-table (LUT) elements in logic circuits of sequential devices. The devices are represented by models of Mealy finite state machines (FSMs). Thesee are so-called MPY FSMs based on two methods of structural decomposition (the replacement of inputs and encoding of output collections). The main idea is to use two types of state codes for implementing systems of partial Boolean functions. Some functions are based on maximum binary codes; other functions depend on extended state codes. The reduction in LUT counts is based on using the method of twofold state assignment. The proposed method makes it possible to obtain FPGA-based FSM circuits with four logic levels. Only one LUT is required to implement the circuit corresponding to any partial function. An example of FSM synthesis using the proposed method is shown. The results of the conducted experiments show that the proposed approach produces LUT-based FSM circuits with better area-temporal characteristics than for circuits produced using such methods as Auto and One-hot of Vivado, JEDI, and MPY FSMs. Compared to MPY FSMs, the values of LUT counts are improved. On average, this improvement is 8.98%, but the gain reaches 13.65% for fairly complex FSMs. The maximum operating frequency is slightly improved as compared with the circuits of MPY FSMs (up to 0.64%). For both LUT counts and frequency, the gain increases together with the growth for the numbers of FSM inputs, outputs and states. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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11 pages, 3708 KiB

Open AccessFeature PaperArticle

MWIRGAN: Unsupervised Visible-to-MWIR Image Translation with Generative Adversarial Network

by Mohammad Shahab Uddin, Chiman Kwan and Jiang Li

Electronics 2023, 12(4), 1039; https://doi.org/10.3390/electronics12041039 - 20 Feb 2023

Cited by 4 | Viewed by 2864

Abstract

Unsupervised image-to-image translation techniques have been used in many applications, including visible-to-Long-Wave Infrared (visible-to-LWIR) image translation, but very few papers have explored visible-to-Mid-Wave Infrared (visible-to-MWIR) image translation. In this paper, we investigated unsupervised visible-to-MWIR image translation using generative adversarial networks (GANs). We proposed [...] Read more.

Unsupervised image-to-image translation techniques have been used in many applications, including visible-to-Long-Wave Infrared (visible-to-LWIR) image translation, but very few papers have explored visible-to-Mid-Wave Infrared (visible-to-MWIR) image translation. In this paper, we investigated unsupervised visible-to-MWIR image translation using generative adversarial networks (GANs). We proposed a new model named MWIRGAN for visible-to-MWIR image translation in a fully unsupervised manner. We utilized a perceptual loss to leverage shape identification and location changes of the objects in the translation. The experimental results showed that MWIRGAN was capable of visible-to-MWIR image translation while preserving the object’s shape with proper enhancement in the translated images and outperformed several competing state-of-the-art models. In addition, we customized the proposed model to convert game-engine-generated (a commercial software) images to MWIR images. The quantitative results showed that our proposed method could effectively generate MWIR images from game-engine-generated images, greatly benefiting MWIR data augmentation. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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21 pages, 4932 KiB

Open AccessFeature PaperArticle

PSO-Based Target Localization and Tracking in Wireless Sensor Networks

by Shu-Hung Lee, Chia-Hsin Cheng, Chien-Chih Lin and Yung-Fa Huang

Electronics 2023, 12(4), 905; https://doi.org/10.3390/electronics12040905 - 10 Feb 2023

Cited by 22 | Viewed by 3344

Abstract

Research of target localization and tracking is always a remarkable problem in the application of wireless sensor networks (WSNs) technology. There are many kinds of research and applications of target localization and tracking, such as Angle of Arrival (AOA), Time of Arrival (TOA), [...] Read more.

Research of target localization and tracking is always a remarkable problem in the application of wireless sensor networks (WSNs) technology. There are many kinds of research and applications of target localization and tracking, such as Angle of Arrival (AOA), Time of Arrival (TOA), and Time Difference of Arrival (TDOA). The target localization accuracy for TOA, TDOA, and AOA is better than RSS. However, the required devices in the TOA, TDOA, and AOA are more expensive than RSS. In addition, the computational complexity of TOA, TDOA, and AOA is also more complicated than RSS. This paper uses a particle swarm optimization (PSO) algorithm with the received signal strength index (RSSI) channel model for indoor target localization and tracking. The performance of eight different method combinations of random or regular points, fixed or adaptive weights, and the region segmentation method (RSM) proposed in this paper for target localization and tracking is investigated for the number of particles in the PSO algorithm with 12, 24, 52, 72, and 100. The simulation results show that the proposed RSM method can reduce the number of particles used in the PSO algorithm and improve the speed of positioning and tracking without affecting the accuracy of target localization and tracking. The total average localization time for target localization and tracking with the RSM method can be reduced by 48.95% and 34.14%, respectively, and the average accuracy of target tracking reaches up to 93.09%. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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12 pages, 2142 KiB

Open AccessCommunication

High-Throughput Bit-Pattern Matching under Heavy Interference on FPGA

by Dimitris Nikolaidis, Panos Groumas, Christos Kouloumentas and Hercules Avramopoulos

Electronics 2023, 12(4), 803; https://doi.org/10.3390/electronics12040803 - 6 Feb 2023

Cited by 1 | Viewed by 1762

Abstract

Bit-pattern matching is an important technological capability, used in many fields such as network intrusion detection (NID) and packet classification systems. Essentially, it involves the matching of an input bit pattern to a bit-pattern entry of a memory structure inside the system. Contemporary [...] Read more.

Bit-pattern matching is an important technological capability, used in many fields such as network intrusion detection (NID) and packet classification systems. Essentially, it involves the matching of an input bit pattern to a bit-pattern entry of a memory structure inside the system. Contemporary methods focus on the decomposition of the input bit pattern into smaller and more manageable parts, with the subsequent parallel processing of these elements. This fragmentation promotes the use of advanced pipeline techniques and hardware optimizations, enabling these methods to achieve very high throughputs and reasonable efficiency. However, the functionality of their respective circuits is limited to only performing pattern matching when there is no interference. In this article, we intend to present a circuit that performs pattern matching under heavy interference; instead of fragmentation, a more holistic approach will be adopted. To improve the throughput of the circuit, long bit sequences will be directly compared to many memory entries simultaneously. The minimization of hardware consumption and maximization of efficiency in these comparisons will be achieved with the use of novel hardware architecture that is based on pipelined adder trees and comparators. The platform of implementation is an FPGA (Field-Programmable Gate Array). Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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14 pages, 13274 KiB

Open AccessArticle

Asymmetric 5.5 GHz Three-Stage Voltage-Controlled Ring-Oscillator in 65 nm CMOS Technology

by Gabriele Ciarpi, Danilo Monda, Marco Mestice, Daniele Rossi and Sergio Saponara

Electronics 2023, 12(3), 778; https://doi.org/10.3390/electronics12030778 - 3 Feb 2023

Cited by 2 | Viewed by 2701

Abstract

The current trend of increasing the complexity of hardware accelerators to improve their functionality is highlighting the problem of sharing a high-frequency clock signal for all integrated modules. As the clock itself is becoming the main limitation to the performance of accelerators, in [...] Read more.

The current trend of increasing the complexity of hardware accelerators to improve their functionality is highlighting the problem of sharing a high-frequency clock signal for all integrated modules. As the clock itself is becoming the main limitation to the performance of accelerators, in this manuscript, we present the design of an asymmetric Ring Oscillator-Voltage-Controlled Oscillator (RO-VCO) based on the Current Mode Logic architecture. The RO-VCO was designed on commercial-grade 65 nm CMOS technology, and it is capable of driving large capacitance loads, avoiding the need for additional buffers for clock-trees, reducing the silicon area and power consumption. The proposed RO-VCO is composed of three closed-loop differential and asymmetrical stages, and it is able to tune the working frequency in the range from 4.72 GHz to 6.12 GHz. The phase noise and a figure of merit of −103.2 dBc/Hz and −186 dBc/Hz were obtained at 1 MHz offset from the 5.5 GHz carrier. In this article, the analytical model, full custom schematic, and layout of the proposed RO-VCO are presented and discussed in detail together with the experimental electrical and thermal characterization of the fabricated device. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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12 pages, 1695 KiB

Open AccessFeature PaperArticle

Supervised Contrastive Learning for Voice Activity Detection

by Youngjun Heo and Sunggu Lee

Electronics 2023, 12(3), 705; https://doi.org/10.3390/electronics12030705 - 31 Jan 2023

Cited by 3 | Viewed by 2602

Abstract

The noise robustness of voice activity detection (VAD) tasks, which are used to identify the human speech portions of a continuous audio signal, is important for subsequent downstream applications such as keyword spotting and automatic speech recognition. Although various aspects of VAD have [...] Read more.

The noise robustness of voice activity detection (VAD) tasks, which are used to identify the human speech portions of a continuous audio signal, is important for subsequent downstream applications such as keyword spotting and automatic speech recognition. Although various aspects of VAD have been recently studied by researchers, a proper training strategy for VAD has not received sufficient attention. Thus, a training strategy for VAD using supervised contrastive learning is proposed for the first time in this paper. The proposed method is used in conjunction with audio-specific data augmentation methods. The proposed supervised contrastive learning-based VAD (SCLVAD) method is trained using two common speech datasets and then evaluated using a third dataset. The experimental results show that the SCLVAD method is particularly effective in improving VAD performance in noisy environments. For clean environments, data augmentation improves VAD accuracy by 8.0 to 8.6%, but there is no improvement due to the use of supervised contrastive learning. On the other hand, for noisy environments, the SCLVAD method results in VAD accuracy improvements of 2.9% and 4.6% for “speech with noise” and “speech with music”, respectively, with only a negligible increase in processing overhead during training. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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15 pages, 4997 KiB

Open AccessArticle

FPGA-Based Tactile Sensory Platform with Optical Fiber Data Link for Feedback Systems in Prosthetics

by Guido Di Patrizio Stanchieri, Moustafa Saleh, Andrea De Marcellis, Ali Ibrahim, Marco Faccio, Maurizio Valle and Elia Palange

Electronics 2023, 12(3), 627; https://doi.org/10.3390/electronics12030627 - 27 Jan 2023

Cited by 3 | Viewed by 1763

Abstract

In this paper, we propose and validate a tactile sensory feedback system for prosthetic applications based on an optical communication link. The optical link features a low power and wide transmission bandwidth, which makes the feedback system suitable for a large number and [...] Read more.

In this paper, we propose and validate a tactile sensory feedback system for prosthetic applications based on an optical communication link. The optical link features a low power and wide transmission bandwidth, which makes the feedback system suitable for a large number and variety of tactile sensors. The low-power transmission is derived from the employed UWB-based optical modulation technique. A system prototype, consisting of digital transmitter and receiver boards and acquisition circuits to interface 32 piezoelectric sensors, was implemented and experimentally tested. The system functionality was demonstrated by processing and transmitting data from the piezoelectric sensor at a 100 Mbps data rate through the optical link, measuring a communication energy consumption of 50 pJ/bit. The reported experimental results validate the functionality of the proposed sensory feedback system and demonstrate its real-time operation capabilities. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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22 pages, 5664 KiB

Open AccessArticle

Software Engineering of Resistive Elements Electrophysical Parameters Simulation in the Process of Laser Trimming

by Vladimir V. Kondrashov, Oleg S. Seredin, Vyacheslav V. Chapkin, Evgeny V. Zemlyakov and Ilya K. Topalov

Electronics 2023, 12(3), 589; https://doi.org/10.3390/electronics12030589 - 25 Jan 2023

Viewed by 1651

Abstract

This study continues a series of papers covering the R&D of circuit simulators embedded into manufacturing equipment for the laser trimming of film and foil resistors intended to improve the final product’s performance and reduce process costs. Our paper describes the development of [...] Read more.

This study continues a series of papers covering the R&D of circuit simulators embedded into manufacturing equipment for the laser trimming of film and foil resistors intended to improve the final product’s performance and reduce process costs. Our paper describes the development of the ResModel laser trimming simulation software. Various types of trims and their features are presented for a circuit with a dynamic measurement DC source, and the optimal trim configurations are identified. The software can be used to estimate and display resistive element properties during the trimming such as its electrophysical parameters and their trends. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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15 pages, 646 KiB

Open AccessArticle

Improving Performance of Hardware Accelerators by Optimizing Data Movement: A Bioinformatics Case Study

by Peter Knoben and Nikolaos Alachiotis

Electronics 2023, 12(3), 586; https://doi.org/10.3390/electronics12030586 - 24 Jan 2023

Cited by 1 | Viewed by 1718

Abstract

Modern hardware accelerator cards create an accessible platform for developers to reduce execution times for computationally expensive algorithms. The most widely used systems, however, have dedicated memory spaces, resulting in the processor having to transfer data to the accelerator-card memory space before the [...] Read more.

Modern hardware accelerator cards create an accessible platform for developers to reduce execution times for computationally expensive algorithms. The most widely used systems, however, have dedicated memory spaces, resulting in the processor having to transfer data to the accelerator-card memory space before the computation can be executed. Currently, the performance increase from using an accelerator card for data-intensive algorithms is limited by the data movement. To this end, this work aims to reduce the effect of data movement and improve overall performance by systematically caching data on the accelerator card. We designed a software-controlled split cache where data are cached on the accelerator and assessed its efficacy using a data-intensive Bioinformatics application that infers the evolutionary history of a set of organisms by constructing phylogenetic trees. Our results revealed that software-controlled data caching on a datacenter-grade FPGA accelerator card reduced the overhead of data movement by 90%. This resulted in a reduction of the total execution time between 32% and 40% for the entire application when phylogenetic trees of various sizes were constructed. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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14 pages, 4377 KiB

Open AccessFeature PaperArticle

Dynamical Analysis and Synchronization of a New Memristive Chialvo Neuron Model

by Gayathri Vivekanandhan, Hayder Natiq, Yaser Merrikhi, Karthikeyan Rajagopal and Sajad Jafari

Electronics 2023, 12(3), 545; https://doi.org/10.3390/electronics12030545 - 20 Jan 2023

Cited by 22 | Viewed by 1972

Abstract

Chialvo is one of the two-dimensional map-based neural models. In this paper, a memristor is added to this model to consider the electromagnetic induction’s effects. The memristor is defined based on a hyperbolic tangent function. The dynamical variations are analyzed by obtaining the [...] Read more.

Chialvo is one of the two-dimensional map-based neural models. In this paper, a memristor is added to this model to consider the electromagnetic induction’s effects. The memristor is defined based on a hyperbolic tangent function. The dynamical variations are analyzed by obtaining the bifurcation diagrams and Lyapunov spectra. It is shown that the most effective parameters on the dynamics are the magnetic strength and the injected current. The memristive Chialvo can exhibit different neural behaviors. It is also proven that, like the primary Chialvo model, the memristive version has coexisting attractors; an oscillating state coexists with a fixed point. In addition, to understand how memristive neurons behave in a network, two memristive Chialvo models are coupled with electrochemical synapses. By connecting two neurons and calculating the synchronization error, we can determine the system’s synchronizability. It is indicated that the electrical coupling is essential for the occurrence of complete synchronization in the network of memristive Chialvo, and the sole chemical coupling does not lead to synchronization. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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21 pages, 6117 KiB

Open AccessArticle

Design of Generalized Enhanced Static Segment Multiplier with Minimum Mean Square Error for Uniform and Nonuniform Input Distributions

by Gennaro Di Meo, Gerardo Saggese, Antonio G. M. Strollo and Davide De Caro

Electronics 2023, 12(2), 446; https://doi.org/10.3390/electronics12020446 - 15 Jan 2023

Cited by 2 | Viewed by 1660

Abstract

In this paper, we analyze the performances of an Enhanced Static Segment Multiplier (ESSM) when the inputs have both uniform and non-uniform distribution. The enhanced segmentation divides the multiplicands into a lower, a middle, and an upper segment. While the middle segment is [...] Read more.

In this paper, we analyze the performances of an Enhanced Static Segment Multiplier (ESSM) when the inputs have both uniform and non-uniform distribution. The enhanced segmentation divides the multiplicands into a lower, a middle, and an upper segment. While the middle segment is placed at the center of the inputs in other implementations, we seek the optimal position able to minimize the approximation error. To this aim, two design parameters are exploited: m, defining the size and the accuracy of the multiplier, and q, defining the position of the middle segment for further accuracy tuning. A hardware implementation is proposed for our generalized ESSM (gESSM), and an analytical model is described, able to find m and q which minimize the mean square approximation error. With uniform inputs, the error slightly improves by increasing q, whereas a large error decrease is observed by properly choosing q when the inputs are half-normal (with a NoEB up to 18.5 bits for a 16-bit multiplier). Implementation results in 28 nm CMOS technology are also satisfactory, with area and power reductions up to 71% and 83%. We report image and audio processing applications, showing that gESSM is a suitable candidate in applications with non-uniform inputs. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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14 pages, 4427 KiB

Open AccessArticle

Implementation and Experimental Verification of Resistorless Fractional-Order Basic Filters

by Dimitrios Patrinos, Georgios Tsirmpas, Panagiotis Bertsias, Costas Psychalinos and Ahmed S. Elwakil

Electronics 2022, 11(23), 3988; https://doi.org/10.3390/electronics11233988 - 1 Dec 2022

Cited by 1 | Viewed by 1452

Abstract

Novel structures of fractional-order differentiation and integration stages are presented in this work, where passive resistors are not required for their implementation. This has been achieved by considering the inherent resistive behavior of fractional-order capacitors. The implementation of the presented stages is performed [...] Read more.

Novel structures of fractional-order differentiation and integration stages are presented in this work, where passive resistors are not required for their implementation. This has been achieved by considering the inherent resistive behavior of fractional-order capacitors. The implementation of the presented stages is performed using a current feedback operational amplifier as active element and fractional-order capacitors based on multi-walled carbon nano-tubes. Basic filter and controller stages are realized using the introduced fundamental blocks, and their behavior is evaluated through experimental results. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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23 pages, 4616 KiB

Open AccessArticle

A Universal Electronically Controllable Memelement Emulator Based on VDCC with Variable Configuration

by Predrag B. Petrović

Electronics 2022, 11(23), 3957; https://doi.org/10.3390/electronics11233957 - 29 Nov 2022

Cited by 6 | Viewed by 1580

Abstract

In this paper, a universal fractional order memelement (FOME) emulator is proposed based on the use of a voltage differentiating current conveyor (VDCC) as active block. The emulation circuit was implemented without an analog voltage multiplier and with only one type of grounded [...] Read more.

In this paper, a universal fractional order memelement (FOME) emulator is proposed based on the use of a voltage differentiating current conveyor (VDCC) as active block. The emulation circuit was implemented without an analog voltage multiplier and with only one type of grounded passive element—capacitors. Specially designed switching networks allow controlling the type of memelement and the emulator mode—floating or/and grounded, electronically controlled (by changing the bias voltage of the VDCC) FOMEs. The proposed emulator was theoretically analyzed, and the influence of possible non-idealities and parasitic effects was also been analyzed to reduce the undesirable effects by selecting the passive circuit elements. The proposed designs are very simple compared to most of the designs available in the literature and can operate in a wide frequency range (up to 50 MHz) and also satisfy the non-volatility test. All realized memelements can be used in incremental and decremental modes as well as in inverse configuration. The performance of the circuit was verified by HSPICE simulations using 0.18 μm TSMC process parameters and ±0.9 V power supply. The proposal is also supported by experimental results with off-the-shelf components (LM13700 and one AD844) in order to confirm the proposed solution’s workability. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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14 pages, 510 KiB

Open AccessArticle

Knowledge Distillation for Image Signal Processing Using Only the Generator Portion of a GAN

by Youngjun Heo and Sunggu Lee

Electronics 2022, 11(22), 3815; https://doi.org/10.3390/electronics11223815 - 20 Nov 2022

Viewed by 1677

Abstract

Knowledge distillation, in which the parameter values learned in a large teacher network are transferred to a smaller student network, is a popular and effective network compression method. Recently, researchers have proposed methods to improve the performance of a student network by using [...] Read more.

Knowledge distillation, in which the parameter values learned in a large teacher network are transferred to a smaller student network, is a popular and effective network compression method. Recently, researchers have proposed methods to improve the performance of a student network by using a Generative Adverserial Network (GAN). However, because a GAN is an architecture that is ideally used to create realistic synthetic images, a pure GAN architecture may not be ideally suited for knowledge distillation. In knowledge distillation for image signal processing, synthetic images do not need to be realistic, but instead should include features that help the training of the student network. In the proposed Generative Image Processing (GIP) method, this is accomplished by using only the generator portion of a GAN and utilizing special techniques to capture the distinguishing feature capability of the teacher network. Experimental results show that the GIP method outperforms knowledge distillation using GANs as well as training using only knowledge distillation. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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20 pages, 698 KiB

Open AccessArticle

Hybrid Full Adders: Optimized Design, Critical Review and Comparison in the Energy-Delay Space

by Gianluca Giustolisi and Gaetano Palumbo

Electronics 2022, 11(19), 3220; https://doi.org/10.3390/electronics11193220 - 8 Oct 2022

Cited by 1 | Viewed by 2671

Abstract

In this paper, we design and compare seven meaningful hybrid one-bit full adders topologies that are optimized in terms of energy-delay trade-offs to operate in multibit ripple carry adders. The goal is to provide the designer with a simple and powerful approach for [...] Read more.

In this paper, we design and compare seven meaningful hybrid one-bit full adders topologies that are optimized in terms of energy-delay trade-offs to operate in multibit ripple carry adders. The goal is to provide the designer with a simple and powerful approach for choosing the best topology for a given power budget, speed performance, or any combination of both. The design and comparison deal with 4-bit and 8-bit ripple carry adders and exploit the derivation of the energy-efficient curves in the energy-delay space. To do so, first we define the procedures to obtain energy consumption and propagation delay by simulating a ripple carry adder designed at a transistor level. Then, we introduce a design methodology to optimize a ripple carry adder by minimizing some significant figures-of-merit in terms of energy-delay trade-offs. The comparison of the energy-efficient curves allows us to make a simple and effective comparison as well as to identify the best one-bit full adder topologies. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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14 pages, 46289 KiB

Open AccessArticle

On Unstable Spatial Modes and Patterns in Cellular and Graph Neural Circuits

by Liviu Goras

Electronics 2022, 11(19), 3033; https://doi.org/10.3390/electronics11193033 - 23 Sep 2022

Viewed by 1284

Abstract

The aim of this paper is to discuss several aspects regarding the dynamics and pattern formation in select cellular and graph neural circuit type architectures and to propose a new application. A unifying approach for these types of neural circuits based on unstable [...] Read more.

The aim of this paper is to discuss several aspects regarding the dynamics and pattern formation in select cellular and graph neural circuit type architectures and to propose a new application. A unifying approach for these types of neural circuits based on unstable spatial modes using the mode decoupling technique is presented. The main objective of this study is that of showing the way the dynamics can be prescribed by speculating the relationship between the extended graph Laplacian and nodal equations of a specific architecture. Based on the above, the possibility of designing a so-called spatial comparator that can extract the sign of a prescribed spatial mode contained in a spatial signal, using unstable circuits for which that mode is associated with a right half-plane eigenvalue, is analyzed and illustrated with simulations in CMOS technology. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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17 pages, 9306 KiB

Open AccessArticle

Bridging the Gap between Physical and Circuit Analysis for Variability-Aware Microwave Design: Power Amplifier Design

by Simona Donati Guerrieri, Chiara Ramella, Eva Catoggio and Fabrizio Bonani

Electronics 2022, 11(18), 2832; https://doi.org/10.3390/electronics11182832 - 8 Sep 2022

Cited by 2 | Viewed by 1814

Abstract

Process Induced Variability (PIV) stemming from fabrication tolerance can impact the performance of integrated circuits. This issue is particularly significant at high frequencies, since Monolithic Microwave Integrated Circuits (MMICs) rely on advanced semiconductor technologies exploiting device sizes at the nanoscale in conjunction with [...] Read more.

Process Induced Variability (PIV) stemming from fabrication tolerance can impact the performance of integrated circuits. This issue is particularly significant at high frequencies, since Monolithic Microwave Integrated Circuits (MMICs) rely on advanced semiconductor technologies exploiting device sizes at the nanoscale in conjunction with complex passive structures, featuring both distributed elements (transmission lines) and lumped components. Black-box (behavioral) models extracted from accurate physical simulations can be profitably exploited to incorporate PIV into circuit-level MMIC analysis. In this paper, these models are applied to the statistical analysis of a single and of a combined MMIC power amplifier designed in GaAs technology for X-band applications. The relative impact of the active device variability towards the passive matching networks one is evaluated, demonstrating the relevance of PIV. The significant spread found, with only two variable parameters, confirms the importance of a PIV-aware PA design approach, with suitable margins and careful network optimization. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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10 pages, 1767 KiB

Open AccessFeature PaperArticle

A Second Order 1.8–1.9 GHz Tunable Active Band-Pass Filter with Improved Noise Performances

by Davide Colaiuda, Alfiero Leoni, Giuseppe Ferri and Vincenzo Stornelli

Electronics 2022, 11(17), 2781; https://doi.org/10.3390/electronics11172781 - 3 Sep 2022

Cited by 2 | Viewed by 2184

Abstract

In this paper, a novel active tunable band-pass filter with improved noise performances is presented. This filter is based on a negative resistance circuit (or active capacitance), where the gain obtained with a transistor is used to compensate for inductor losses. Moreover, the [...] Read more.

In this paper, a novel active tunable band-pass filter with improved noise performances is presented. This filter is based on a negative resistance circuit (or active capacitance), where the gain obtained with a transistor is used to compensate for inductor losses. Moreover, the capacitance of the resonator is obtained through a voltage-controlled reverse-biased varactor, which allows for frequency tuning. Despite the active component, the proposed filter also has good noise performance. Measurements show a tunability range from 1.816 GHz to 1.886 GHz, with a bandwidth of 38 MHz. The insertion loss maximum value is 0.4 dB, while the noise figure value has a minimum value of 2.5 dB at the center frequency within the tunability range. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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10 pages, 2175 KiB

Open AccessArticle

0.4-V, 81.3-nA Bulk-Driven Single-Stage CMOS OTA with Enhanced Transconductance

by Andrea Ballo, Alfio Dario Grasso and Salvatore Pennisi

Electronics 2022, 11(17), 2704; https://doi.org/10.3390/electronics11172704 - 29 Aug 2022

Cited by 11 | Viewed by 2861

Abstract

The paper describes a single-stage operational transconductance amplifier suitable for very-low-voltage operation in power-constrained applications. The proposed circuit avoids the tail current generator in the differential pair while preventing pseudo-differential operation. Moreover, the adoption of positive feedback allows increasing the stage transconductance while [...] Read more.

The paper describes a single-stage operational transconductance amplifier suitable for very-low-voltage operation in power-constrained applications. The proposed circuit avoids the tail current generator in the differential pair while preventing pseudo-differential operation. Moreover, the adoption of positive feedback allows increasing the stage transconductance while minimizing the current consumption. Experimental measurements on prototypes implemented in a standard CMOS 180-nm technology, show superior performance as compared to the state of the art. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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11 pages, 3571 KiB

Open AccessArticle

High−Performance 4H−SiC UV p−i−n Photodiode: Numerical Simulations and Experimental Results

by Sandro Rao, Elisa D. Mallemace and Francesco G. Della Corte

Electronics 2022, 11(12), 1839; https://doi.org/10.3390/electronics11121839 - 9 Jun 2022

Cited by 6 | Viewed by 2359

Abstract

In this work, the optical response of a high−performance 4H−SiC−based p−i−n ultraviolet (UV) photodiode was studied by means of an ad hoc numerical model. The spectral responsivity and the corresponding external photodiode quantum efficiency were calculated under different reverse biases, up to 60 [...] Read more.

In this work, the optical response of a high−performance 4H−SiC−based p−i−n ultraviolet (UV) photodiode was studied by means of an ad hoc numerical model. The spectral responsivity and the corresponding external photodiode quantum efficiency were calculated under different reverse biases, up to 60 V, and in the wavelength range from λ = 190 to 400 nm. The responsivity peak is R = 0.168 A/W at λ = 292 nm at 0 V and improves as bias increases, reaching R = 0.212 A/W at 60 V and λ = 298 nm. The external quantum efficiency is about 71% and 88%. The good quality of the simulation setup was confirmed by comparison with experimental measurements performed on a p−i−n device fabricated starting from a commercial 4H−SiC wafer. The developed numerical model, together with the material electrical and optical parameters used in our simulations, can be therefore explored for the design of more complex 4H−SiC−based solid−state electronic and optoelectronic devices. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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10 pages, 575 KiB

Open AccessArticle

CNTFET-Based Ternary Multiply-and-Accumulate Unit

by Amr Mohammaden, Mohammed E. Fouda, Ihsen Alouani, Lobna A. Said and Ahmed G. Radwan

Electronics 2022, 11(9), 1455; https://doi.org/10.3390/electronics11091455 - 30 Apr 2022

Cited by 6 | Viewed by 2322

Abstract

Multiply-Accumulate (MAC) is one of the most commonly used operations in modern computing systems due to its use in matrix multiplication, signal processing, and in new applications such as machine learning and deep neural networks. Ternary number system offers higher information processing within [...] Read more.

Multiply-Accumulate (MAC) is one of the most commonly used operations in modern computing systems due to its use in matrix multiplication, signal processing, and in new applications such as machine learning and deep neural networks. Ternary number system offers higher information processing within the same number of digits when compared to binary systems. In this paper, a MAC is proposed using a CNTFET-based ternary logic number. Specifically, we build a 5-trit multiplier and 10-trit adder as building blocks of two ternary MAC unit designs. The first is a basic MAC which has two methods to implement, serial and pipeline. The second is an improved MAC design that optimizes the number of transistors, offers higher performance and lower power consumption. The designed MAC unit can operate up to 300 MHz. Finally, a comparative study in terms of power, delay, and area variations is conducted under different supply voltages and temperature levels. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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23 pages, 7418 KiB

Open AccessFeature PaperArticle

A Novel Low-Power High-Precision Implementation for Sign–Magnitude DLMS Adaptive Filters

by Gennaro Di Meo, Davide De Caro, Nicola Petra and Antonio G. M. Strollo

Electronics 2022, 11(7), 1007; https://doi.org/10.3390/electronics11071007 - 24 Mar 2022

Cited by 1 | Viewed by 1883

Abstract

This paper investigates the use of approximate fixed-width and static segment multipliers in the design of Delayed Least Mean Square (DLMS) adaptive filters based on the sign–magnitude representation for the error signal. The fixed-width approximation discards part of the partial product matrix and [...] Read more.

This paper investigates the use of approximate fixed-width and static segment multipliers in the design of Delayed Least Mean Square (DLMS) adaptive filters based on the sign–magnitude representation for the error signal. The fixed-width approximation discards part of the partial product matrix and introduces a compensation function for minimizing the approximation error, whereas the static segmented multipliers reduce the bit-width of the multiplicands at runtime. The use of sign–magnitude representation for the error signal reduces the switching activity in the filter learning section, minimizing power dissipation. Simulation results reveal that, by properly sizing the two approaches, a steady state mean square error practically unchanged with respect to the exact DLMS can be achieved. The hardware syntheses in a 28 nm CMOS technology reveal that the static segmented multipliers perform better in the learning section of the filter and are the most efficient approach to reduce area occupation, while the fixed-width multipliers offer the best performances in the finite impulse response section and provide the lowest power dissipation. The investigated adaptive filters overcome the state-of-the-art, exhibiting an area and power reduction with respect to the standard implementation up to −18.0% and −64.1%, respectively, while preserving the learning capabilities. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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12 pages, 895 KiB

Open AccessArticle

Novel Approach and Methods for Optimizing Highly Sensitive Low Noise Amplifier CMOS IC Design for Congested RF Environments

by Jooik Chung and Agis A. Iliadis

Electronics 2022, 11(7), 976; https://doi.org/10.3390/electronics11070976 - 22 Mar 2022

Cited by 3 | Viewed by 2419

Abstract

This work details the optimization and evaluation of a CMOS low-noise amplifier by developing a new algorithm for the

g_{m} / I_{D}

approach and combining with a modified figure of merit index method. The amplifier includes on-chip matching elements (such as [...] Read more.

This work details the optimization and evaluation of a CMOS low-noise amplifier by developing a new algorithm for the

g_{m} / I_{D}

approach and combining with a modified figure of merit index method. The amplifier includes on-chip matching elements (such as IC inductors) for resonance at the targeted frequencies. The simulation results of the optimized LNA model showed scattering parameter

S_{21}

= 19.91 dB, noise figure NF = 3.54 dB and excellent linearity for third-order intermodulation parameter IIP3 = 5.89 dBm for the targeted frequency of

f_{0}

= 2.4 GHz. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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29 pages, 7104 KiB

Open AccessArticle

Improving Characteristics of LUT-Based Three-Block Mealy FSMs’ Circuits

by Alexander Barkalov, Larysa Titarenko, Kazimierz Krzywicki and Svetlana Saburova

Electronics 2022, 11(6), 950; https://doi.org/10.3390/electronics11060950 - 18 Mar 2022

Cited by 3 | Viewed by 2303

Abstract

One of the very important problems connected with FPGA-based design is reducing the hardware amount in implemented circuits. In this paper, we discuss the implementation of Mealy finite state machines (FSMs) by circuits consisting of look-up tables (LUT). A method is proposed to [...] Read more.

One of the very important problems connected with FPGA-based design is reducing the hardware amount in implemented circuits. In this paper, we discuss the implementation of Mealy finite state machines (FSMs) by circuits consisting of look-up tables (LUT). A method is proposed to reduce the LUT count of three-block circuits of Mealy FSMs. The method is based on finding a partition of set of internal states by classes of compatible states. To reduce the LUT count, we propose a special kind of state code, named complex state codes. The complex codes include two parts. The first part includes the binary codes of a state as the element of some partition class. The second part consists of the code of corresponding partition class. Using complex state codes allows obtaining FPGA-based FSM circuits with exactly four logic blocks. If some conditions hold, then any FSM function from the first and second blocks is implemented by a single LUT. The third level is represented as a network of multiplexers. These multiplexers generate either additional variable encoding collections of outputs or input memory functions. The fourth level generates FSM outputs. An example of synthesis and experimental results is shown and discussed. The experiments prove that the proposed approach allows reducing hardware compared to such methods as auto and one-hot of Vivado, JEDI. Further, the proposed approach produces circuits with fewer LUTs than for three-level Mealy FSMs based on joint use of several methods of structural decomposition. The experiments show that our approach allows reducing the LUT counts on average from 11 to 77 percent. As the complexity of an FSM increases, the gain from the application of the proposed method grows; the same is true for both the FSM performance and power consumption. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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16 pages, 3660 KiB

Open AccessArticle

Low-Cost Data Acquisition System for Solar Thermal Collectors

by Orestis Panagopoulos and Athanassios A. Argiriou

Electronics 2022, 11(6), 934; https://doi.org/10.3390/electronics11060934 - 17 Mar 2022

Cited by 7 | Viewed by 3496

Abstract

Solar thermal collectors are among the most popular renewable energy research subjects. Automatic Data Acquisition Systems (ADAS) have greatly facilitated their experimental testing, but their high cost is a drawback. In this paper, we present the design and testing of a decentralized, low-cost [...] Read more.

Solar thermal collectors are among the most popular renewable energy research subjects. Automatic Data Acquisition Systems (ADAS) have greatly facilitated their experimental testing, but their high cost is a drawback. In this paper, we present the design and testing of a decentralized, low-cost alternative ADAS based on the ESP32 microcontroller and on open-source software. The proposed system can be used for the experimental characterization of water (or air) operated solar thermal collectors in accordance with the ISO 9806:2017 requirements, but it is also compatible with sensors with lower specifications. We present also its performance results when applied for the testing of a solar thermal collector. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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16 pages, 4683 KiB

Open AccessArticle

A New Fully Closed-Loop, High-Precision, Class-AB CCII for Differential Capacitive Sensor Interfaces

by Gianluca Barile, Francesco Centurelli, Giuseppe Ferri, Pietro Monsurrò, Leonardo Pantoli, Vincenzo Stornelli, Pasquale Tommasino and Alessandro Trifiletti

Electronics 2022, 11(6), 903; https://doi.org/10.3390/electronics11060903 - 15 Mar 2022

Cited by 1 | Viewed by 2005

Abstract

The use of capacitive sensors has advantages in different industrial applications due to their low cost and low-temperature dependence. In this sense, the current-mode approach by means of second-generation current conveyors (CCIIs) allows for improvements in key features, such as sensitivity and resolution. [...] Read more.

The use of capacitive sensors has advantages in different industrial applications due to their low cost and low-temperature dependence. In this sense, the current-mode approach by means of second-generation current conveyors (CCIIs) allows for improvements in key features, such as sensitivity and resolution. In this paper, a novel architecture of CCII for differential capacitive sensor interfaces is presented. The proposed topology shows a closed-loop configuration for both the voltage and the current buffer, thus leading to better interface impedances at terminals X and Z. Moreover, a low power consumption of 600 µW was obtained due to class-AB biasing of both buffers, and the inherent drawbacks in terms of linearity under the mismatch of class-AB buffering are overcome by its closed-loop configuration. The advantages of the novel architecture are demonstrated by circuit analysis and simulations; in particular, very good robustness under process, supply voltage and temperature variations and mismatches were obtained due to the closed-loop approach. The CCII was also used to design a capacitive sensor interface in integrated CMOS technology, where it was possible to achieve a sensitivity of 2.34 nA/fF, with a full-scale sensor variation of 8 pF and a minimum detectable capacitance difference of 40 fF. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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18 pages, 3317 KiB

Open AccessFeature PaperArticle

Bridging the Gap between Physical and Circuit Analysis for Variability-Aware Microwave Design: Modeling Approaches

by Simona Donati Guerrieri, Chiara Ramella, Eva Catoggio and Fabrizio Bonani

Electronics 2022, 11(6), 860; https://doi.org/10.3390/electronics11060860 - 9 Mar 2022

Cited by 9 | Viewed by 2758

Abstract

Process-induced variability is a growing concern in the design of analog circuits, and in particular for monolithic microwave integrated circuits (MMICs) targeting the 5G and 6G communication systems. The RF and microwave (MW) technologies developed for the deployment of these communication systems exploit [...] Read more.

Process-induced variability is a growing concern in the design of analog circuits, and in particular for monolithic microwave integrated circuits (MMICs) targeting the 5G and 6G communication systems. The RF and microwave (MW) technologies developed for the deployment of these communication systems exploit devices whose dimension is now well below 100 nm, featuring an increasing variability due to the fabrication process tolerances and the inherent statistical behavior of matter at the nanoscale. In this scenario, variability analysis must be incorporated into circuit design and optimization, with ad hoc models retaining a direct link to the fabrication process and addressing typical MMIC nonlinear applications like power amplification and frequency mixing. This paper presents a flexible procedure to extract black-box models from accurate physics-based simulations, namely TCAD analysis of the active devices and EM simulations for the passive structures, incorporating the dependence on the most relevant fabrication process parameters. We discuss several approaches to extract these models and compare them to highlight their features, both in terms of accuracy and of ease of extraction. We detail how these models can be implemented into EDA tools typically used for RF and MMIC design, allowing for fast and accurate statistical and yield analysis. We demonstrate the proposed approaches extracting the black-box models for the building blocks of a power amplifier in a GaAs technology for X-band applications. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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14 pages, 4495 KiB

Open AccessFeature PaperArticle

28-GHz CMOS Direct-Conversion RF Transmitter with Precise and Wide-Range Mismatch Calibration Techniques

by Yongho Lee, Byeonghyeon Kim and Hyunchol Shin

Electronics 2022, 11(6), 840; https://doi.org/10.3390/electronics11060840 - 8 Mar 2022

Cited by 5 | Viewed by 3647

Abstract

A millimeter-wave direct-conversion radio-frequency (RF) transmitter requires precise in-/quadrature-phase (I/Q) mismatch calibration and dc offset cancellation to minimize image rejection ratio (IRR) and LO feedthrough (LOFT) for ensuring satisfactory output spectral purity. We present a 28-GHz CMOS RF transmitter with an improved calibration [...] Read more.

A millimeter-wave direct-conversion radio-frequency (RF) transmitter requires precise in-/quadrature-phase (I/Q) mismatch calibration and dc offset cancellation to minimize image rejection ratio (IRR) and LO feedthrough (LOFT) for ensuring satisfactory output spectral purity. We present a 28-GHz CMOS RF transmitter with an improved calibration technique for fifth generation (5G) wireless communication applications. The RF transmitter comprises a baseband amplifier, quadrature up-conversion mixer, power amplifier driver, and quadrature LO generator. The I/Q amplitude mismatch is calibrated by tuning the gate biases of the switching stage FETs of the mixer, the I/Q phase mismatch is calibrated by tuning the varactor capacitances at the LC load of LO buffer, and the dc offset is cancelled by tuning the body voltages of the differential-pair FETs at the baseband amplifier. The proposed technique provides precise calibration accuracy by employing mV-resolution tuning voltage generation via 6-bit voltage digital-to-analog converters. It also covers wide calibration range while minimizing the impact on the circuit’s bias point and dissipated current during calibration. Implemented in a 65 nm CMOS process, the RF transmitter integrated circuit shows output-referred 1 dB compression power of +6.5 dBm, saturated output power of +12.6 dBm, and an operating band of 27.5–29.3 GHz while demonstrating satisfactory performances of −55.9 dBc of IRR and −36.8 dBc of LOFT. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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14 pages, 598 KiB

Open AccessArticle

Fast Design Space Exploration and Multi-Objective Optimization of Wide-Band Noise-Canceling LNAs

by Karim Elmeligy and Hesham Omran

Electronics 2022, 11(5), 816; https://doi.org/10.3390/electronics11050816 - 5 Mar 2022

Cited by 10 | Viewed by 3814

Abstract

Design optimization of RF low-noise amplifiers (LNAs) remains a time-consuming and complex process. Iterations are needed to adjust impedance matching, gain, and noise figure (NF) simultaneously. The process can involve more iterations to adjust the non-linear behavior of the circuit which can be [...] Read more.

Design optimization of RF low-noise amplifiers (LNAs) remains a time-consuming and complex process. Iterations are needed to adjust impedance matching, gain, and noise figure (NF) simultaneously. The process can involve more iterations to adjust the non-linear behavior of the circuit which can be represented by the input-referred third-order intercept (IIP3). In this work, we present a variation-aware automated design and optimization flow for a wide-band noise-canceling LNA. We include the circuit non-linearity in the optimization flow without using a simulator in the loop. By describing the transistors using precomputed lookup tables (LUTs), a design database that contains 200,000 design points is generated in 3 s only without non-linearity computation and 10 s when non-linearity is taken into account. Using a gm/ID-based correct-by-construction design procedure, the generated design points automatically satisfy proper biasing, input matching, and gain matching requirements. The generated database enables the designer to visualize the design space and explore the design trade-offs. Moreover, multi-objective optimization across corners for a given set of specifications is applied to find the Pareto-optimal fronts of the design figures-of-merit. We demonstrate the presented flow using two design examples in a 65 nm process and the results are verified using Cadence Spectre. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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18 pages, 14452 KiB

Open AccessFeature PaperArticle

A Tunable Microstrip Bandpass Filter with Two Concurrently Tuned Transmission Zeros

by Mirosław Magnuski, Dariusz Wójcik, Maciej Surma and Artur Noga

Electronics 2022, 11(5), 807; https://doi.org/10.3390/electronics11050807 - 4 Mar 2022

Cited by 1 | Viewed by 3434

Abstract

In this paper, an electrically small tunable microstrip bandpass filter with two concurrently tuned transmission zeros (TZs) is presented. The filter consists of two coupled resonators and varactors as tuning elements. An application of a multipath coupling network results in TZs on both [...] Read more.

In this paper, an electrically small tunable microstrip bandpass filter with two concurrently tuned transmission zeros (TZs) is presented. The filter consists of two coupled resonators and varactors as tuning elements. An application of a multipath coupling network results in TZs on both sides of the passband. The filter controlled by a single voltage has a wide tuning range from 370 MHz to 800 MHz and a low insertion loss ranging from 1.9 dB to 3.4 dB. To achieve high attenuation in the stopband, two sections of the designed filter were cascaded. Both one-section and two-section filters were validated by measurements. The obtained results are in a very good agreement with simulations. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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13 pages, 5853 KiB

Open AccessArticle

An Accurate Bandgap Voltage Reference Ready-Indicator

by Rafailia Malatesta, George Souliotis, Fotis Plessas and Spyridon Vlassis

Electronics 2022, 11(5), 723; https://doi.org/10.3390/electronics11050723 - 26 Feb 2022

Viewed by 4158

Abstract

An accurate indication that the bandgap voltage reference (BGR) circuit is settled on its nominal value is essential in analog or mixed signal systems. In this paper, a generic method for accurate bandgap voltage reference (BGR) Ready-Indication (RI) is proposed. A RI signal [...] Read more.

An accurate indication that the bandgap voltage reference (BGR) circuit is settled on its nominal value is essential in analog or mixed signal systems. In this paper, a generic method for accurate bandgap voltage reference (BGR) Ready-Indication (RI) is proposed. A RI signal shows that the BGR operates correctly but also is used to enable PoR circuits when those employ the bandgap voltage to generate the required thresholds. In many low power applications, several systems are periodically switched on and off to save power and to increase battery life. In such systems, most circuits must remain off, while BGR is not in ready mode, saving battery energy. In other critical applications, the Ready-Indicator can ensure that critical systems can be set on and the reference voltage is within the operating range. In this paper, the introduced methodology is applied to different reference voltage generators. Initially, a BGR with Ready-Indication is presented extensively, including post-layout simulations results in 22 nm, while thereafter, the study of this method is extended in other BGR topologies. The universality of the proposed method is proved by verifying the operation in all the BGR topologies under study covering designs in 22 nm and 65 nm and with supply voltages 1.8 V, 1 V, 0.55 V. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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20 pages, 2132 KiB

Open AccessArticle

Run-Time Thermal Management for Lifetime Optimization in Low-Power Designs

by Daniele Rossi and Vasileios Tenentes

Electronics 2022, 11(3), 411; https://doi.org/10.3390/electronics11030411 - 29 Jan 2022

Viewed by 2079

Abstract

In this paper, the magnitude of the temperature and stress variability of dynamic voltage and frequency scaling (DVFS) designs is analyzed, and their impact on the bias temperature instability (BTI) degradation and lifetime of DVFS designs is assessed. For this purpose, a design-time [...] Read more.

In this paper, the magnitude of the temperature and stress variability of dynamic voltage and frequency scaling (DVFS) designs is analyzed, and their impact on the bias temperature instability (BTI) degradation and lifetime of DVFS designs is assessed. For this purpose, a design-time evaluation framework for BTI degradation was developed, which considered the statistical workload and die temperature profiles of DVFS operating modes. The performed analysis showed that, together with high stress variability, DVFS designs exhibited even higher temperature variability, depending on the workload and utilized operating modes, and the impact of temperature variability on lifetime could be up to 2× higher than that due to stress. In order to account for temperature variability on aging detrimental effects, a thermal management run-time system is proposed that honors the desired lifetime constraints by properly selecting temperature constraints that govern the utilized operating modes. The proposed run-time system was applied on the largest benchmark circuit from the IWLS 2005 suite, Ethernet circuit, synthesized with the 32 nm CMOS technology. The proposed system was verified to obtain lifetime and performance estimation and the trade-off with up to 35.8% and 26.3% higher accuracy, respectively, when compared to a system that ignores temperature variability and accounts for average temperature only. The proposed framework can be suitably utilized for tuning run-time throttling policies of low-power designs, thus allowing designers to optimize lifetime–performance trade-offs, depending on the requirements mandated by specific applications and operating environments. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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15 pages, 4251 KiB

Open AccessFeature PaperArticle

Realization of an Electronically Tunable Resistor-Less Floating Inductance Simulator Using VCII

by Leila Safari, Gianluca Barile, Davide Colaiuda, Vincenzo Stornelli and Giuseppe Ferri

Electronics 2022, 11(3), 312; https://doi.org/10.3390/electronics11030312 - 19 Jan 2022

Cited by 10 | Viewed by 2022

Abstract

In this paper, a new implementation of an electronically tunable resistor-less floating inductance simulator using a second-generation voltage conveyor (VCII) is presented. The proposed circuit is resistor-free (benefiting from the intrinsic resistors at the Y terminals of the employed VCIIs) and composed of [...] Read more.

In this paper, a new implementation of an electronically tunable resistor-less floating inductance simulator using a second-generation voltage conveyor (VCII) is presented. The proposed circuit is resistor-free (benefiting from the intrinsic resistors at the Y terminals of the employed VCIIs) and composed of three VCIIs and a single grounded capacitor. Using a control current (I_con), the value of impedance at the Y terminal of the VCII is varied, whereby the value of the simulated inductance is tuned. The proposed circuit is designed at a transistor level using 0.18 µm TSMC CMOS parameters and ±0.9 V supply voltage. PSpice simulations are carried out to confirm the effectiveness of the proposed circuit. For a range of Icon from 0 µA to 50 µA, the value of the simulated L can be varied from −576 µH to −324 µH and from +316 µH to +576 µH for negative and positive simulators, respectively, in the frequency range of 100 kHz–3 MHz. Favorably, the value of the series resistance remains below 76 Ω. Simulation results show an error value below 4.8% and power consumption variation is from 1.64 mW to 1.92 mW. Moreover, application of the proposed circuit as a standard band-pass RLC filter is also included. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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11 pages, 3750 KiB

Open AccessArticle

A New Memristive Neuron Map Model and Its Network’s Dynamics under Electrochemical Coupling

by Balamurali Ramakrishnan, Mahtab Mehrabbeik, Fatemeh Parastesh, Karthikeyan Rajagopal and Sajad Jafari

Electronics 2022, 11(1), 153; https://doi.org/10.3390/electronics11010153 - 4 Jan 2022

Cited by 41 | Viewed by 2503

Abstract

A memristor is a vital circuit element that can mimic biological synapses. This paper proposes the memristive version of a recently proposed map neuron model based on the phase space. The dynamic of the memristive map model is investigated by using bifurcation and [...] Read more.

A memristor is a vital circuit element that can mimic biological synapses. This paper proposes the memristive version of a recently proposed map neuron model based on the phase space. The dynamic of the memristive map model is investigated by using bifurcation and Lyapunov exponents’ diagrams. The results prove that the memristive map can present different behaviors such as spiking, periodic bursting, and chaotic bursting. Then, a ring network is constructed by hybrid electrical and chemical synapses, and the memristive neuron models are used to describe the nodes. The collective behavior of the network is studied. It is observed that chemical coupling plays a crucial role in synchronization. Different kinds of synchronization, such as imperfect synchronization, complete synchronization, solitary state, two-cluster synchronization, chimera, and nonstationary chimera, are identified by varying the coupling strengths. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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12 pages, 5737 KiB

Open AccessFeature PaperArticle

Dual-Band, Dual-Output Power Amplifier Using Simplified Three-Port, Frequency-Dividing Matching Network

by Xiaopan Chen, Yongle Wu and Weimin Wang

Electronics 2022, 11(1), 144; https://doi.org/10.3390/electronics11010144 - 4 Jan 2022

Cited by 4 | Viewed by 3011

Abstract

This study presents a dual-band power amplifier (PA) with two output ports using a simplified three-port, frequency-dividing matching network. The dual-band, dual-output PA could amplify a dual-band signal with one transistor, and the diplexer-like output matching network (OMN) divided the two bands into [...] Read more.

This study presents a dual-band power amplifier (PA) with two output ports using a simplified three-port, frequency-dividing matching network. The dual-band, dual-output PA could amplify a dual-band signal with one transistor, and the diplexer-like output matching network (OMN) divided the two bands into different output ports. A structure consisting of a λ/4 open stub and a λ/4 transmission line was applied to restrain undesired signals, which made each branch equivalent to an open circuit at another frequency. A three-stub design reduced the complexity of the OMN. Second-order harmonic impedances were tuned for better efficiency. The PA was designed with a 10-W gallium nitride high electron mobility transistor (GaN HEMT). It achieved a drain efficiency (DE) of 55.84% and 53.77%, with the corresponding output power of 40.22 and 40.77 dBm at 3.5 and 5.0 GHz, respectively. The 40%-DE bandwidths were over 200 MHz in the two bands. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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9 pages, 5009 KiB

Open AccessArticle

Approximate Square Root Circuits with Low Latency and Power Dissipation

by Duhwan Kim and Sunggu Lee

Electronics 2022, 11(1), 46; https://doi.org/10.3390/electronics11010046 - 24 Dec 2021

Cited by 6 | Viewed by 2629

Abstract

This paper proposes a series of approximate square root circuit designs with high accuracy, low latency, low area, and low power dissipation requirements. The proposed designs are constructed using an array of controlled add–subtract cell elements with both exact and approximate versions. The [...] Read more.

This paper proposes a series of approximate square root circuit designs with high accuracy, low latency, low area, and low power dissipation requirements. The proposed designs are constructed using an array of controlled add–subtract cell elements with both exact and approximate versions. The utility of the proposed designs are evaluated by utilizing them in an example image contrast enhancement application with demonstrably satisfactory results and large peak signal-to-noise ratios and structural similarity values. The accuracy and hardware characteristics of the proposed square root designs are also analyzed and compared with previously proposed state-of-the-art approximate square root designs. When applied to a 16-bit radicand (the number under the square root symbol), the proposed designs have the lowest error rates, normalized mean error distances, and mean relative error distances by at least 1.8x when compared to all previous methods using the same number of approximate cells. When the designs were synthesized using Synopsys Design Compiler with a 28 nm bulk CMOS process, the delay, area, power, and power-delay-product characteristics outperform all previous designs in all but a few cases. These results demonstrate that the proposed designs permit the use of a flexible range of approximate designs with varying accuracy and hardware overhead characteristics, and a suitable design can be selected based on the user design requirements. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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23 pages, 1646 KiB

Open AccessEditor’s ChoiceArticle

On the Sizing of CMOS Operational Amplifiers by Applying Many-Objective Optimization Algorithms

by Martín Alejandro Valencia-Ponce, Esteban Tlelo-Cuautle and Luis Gerardo de la Fraga

Electronics 2021, 10(24), 3148; https://doi.org/10.3390/electronics10243148 - 17 Dec 2021

Cited by 19 | Viewed by 4775

Abstract

In CMOS integrated circuit (IC) design, operational amplifiers are one of the most useful active devices to enhance applications in analog signal processing, signal conditioning and so on. However, due to the CMOS technology downscaling, along the very large number of design variables [...] Read more.

In CMOS integrated circuit (IC) design, operational amplifiers are one of the most useful active devices to enhance applications in analog signal processing, signal conditioning and so on. However, due to the CMOS technology downscaling, along the very large number of design variables and their trade-offs, it results difficult to reach target specifications without the application of optimization methods. For this reason, this work shows the advantages of performing many-objective optimization and this algorithm is compared to the well-known mono- and multi-objective metaheuristics, which have demonstrated their usefulness in sizing CMOS ICs. Three CMOS operational transconductance amplifiers are the case study in this work; they were sized by applying mono-, multi- and many-objective algorithms. The well-known non-dominated sorting genetic algorithm version 3 (NSGA-III) and the many-objective metaheuristic-based on the R2 indicator (MOMBI-II) were applied to size CMOS amplifiers and their sized solutions were compared to mono- and multi-objective algorithms. The CMOS amplifiers were optimized considering five targets, associated to a figure of merit (FoM), differential gain, power consumption, common-mode rejection ratio and total silicon area. The designs were performed using UMC 180 nm CMOS technology. To show the advantage of applying many-objective optimization algorithms to size CMOS amplifiers, the amplifier with the best performance was used to design a fractional-order integrator based on OTA-C filters. A variation analysis considering the process, the voltage and temperature (PVT) and a Monte Carlo analysis were performed to verify design robustness. Finally, the OTA-based fractional-order integrator was used to design a fractional-order chaotic oscillator, showing good agreement between numerical and SPICE simulations. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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12 pages, 8434 KiB

Open AccessArticle

A 4 GHz Single-to-Differential Cross-Coupled Variable-Gain Transimpedance Amplifier for Optical Communication

by Samuel B. S. Lee and Kiat Seng Yeo

Electronics 2021, 10(23), 3042; https://doi.org/10.3390/electronics10233042 - 5 Dec 2021

Cited by 3 | Viewed by 3330

Abstract

This letter presents an inductorless transimpedance amplifier (TIA) for visible light communication, using the UMC 40 nm CMOS process. It consists of a single-to-differential input stage with a modified cross-coupled regulated cascode design, followed by a modified

f_{T}

-doubler mid-stage with a [...] Read more.

This letter presents an inductorless transimpedance amplifier (TIA) for visible light communication, using the UMC 40 nm CMOS process. It consists of a single-to-differential input stage with a modified cross-coupled regulated cascode design, followed by a modified

f_{T}

-doubler mid-stage with a combined active inductor and capacitive degeneration design for bandwidth-enhancement and differential output. The mid-stage also has an attached common-mode feedback (CMFB) circuit. Both the input and mid-stages have gain-varying and peaking-varying functions. It has a measured gain range of 37.5–58.7 dBΩ and 4.15 GHz bandwidth using a 0.5 pF capacitive load. The gain range results in an input dynamic range of 33.2 µA–1.46 mA. Its input referred noise current is 10.7 pA/

\sqrt{H z}

, core DC power consumption is 7.84 mW from a

V_{D D T I A}

of 1.6 V and core area is 39 µm × 26 µm. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Review

Jump to: Research

17 pages, 7099 KiB

Open AccessReview

A Survey of Ultra-Low-Power Amplifiers for Internet of Things Nodes

by Alfio Dario Grasso, Salvatore Pennisi and Chiara Venezia

Electronics 2023, 12(20), 4361; https://doi.org/10.3390/electronics12204361 - 20 Oct 2023

Cited by 1 | Viewed by 1533

Abstract

This paper investigates CMOS operational transconductance amplifier (OTA) design methodologies suitable for Internet of Things nodes. The use of MOS transistors in the subthreshold of the body terminal for signal input or bias, as well as newer inverter- and digital-based techniques, is considered. [...] Read more.

This paper investigates CMOS operational transconductance amplifier (OTA) design methodologies suitable for Internet of Things nodes. The use of MOS transistors in the subthreshold of the body terminal for signal input or bias, as well as newer inverter- and digital-based techniques, is considered. Solutions from the authors’ work are utilized as main case examples. State-of-the-art ultra-low-power OTAs are then thoroughly compared using a data-driven approach. According to the findings, digital- and inverter-based solutions have the lowest area occupation and superior small-signal performance but are inherently susceptible to process, supply, and temperature (PVT) variations. The only “analog” approach suitable for a sub-0.6 V supply is body driving in conjunction with subthreshold bias. It offers competitive large-signal performance and, more importantly, is less sensitive to PVT variations at the expense of silicon area. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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32 pages, 1797 KiB

Open AccessReview

Memristors in Cellular-Automata-Based Computing: A Review

by Rafailia-Eleni Karamani, Iosif-Angelos Fyrigos, Vasileios Ntinas, Ioannis Vourkas, Andrew Adamatzky and Georgios Ch. Sirakoulis

Electronics 2023, 12(16), 3523; https://doi.org/10.3390/electronics12163523 - 20 Aug 2023

Cited by 3 | Viewed by 4313

Abstract

The development of novel hardware computing systems and methods has been a topic of increased interest for researchers worldwide. New materials, devices, and architectures are being explored as a means to deliver more efficient solutions to contemporary issues. Along with the advancement of [...] Read more.

The development of novel hardware computing systems and methods has been a topic of increased interest for researchers worldwide. New materials, devices, and architectures are being explored as a means to deliver more efficient solutions to contemporary issues. Along with the advancement of technology, there is a continuous increase in methods available to address significant challenges. However, the increased needs to be fulfilled have also led to problems of increasing complexity that require better and faster computing and processing capabilities. Moreover, there is a wide range of problems in several applications that cannot be addressed using the currently available methods and tools. As a consequence, the need for emerging and more efficient computing methods is of utmost importance and constitutes a topic of active research. Among several proposed solutions, we distinguish the development of a novel nanoelectronic device, called a “memristor”, that can be utilized both for storing and processing, and thus it has emerged as a promising circuit element for the design of compact and energy-efficient circuits and systems. The memristor has been proposed for a wide range of applications. However, in this work, we focus on its use in computing architectures based on the concept of Cellular Automata. The combination of the memristor’s performance characteristics with Cellular Automata has boosted further the concept of processing and storing information on the same physical units of a system, which has been extensively studied in the literature as it provides a very good candidate for the implementation of Cellular Automata computing with increased potential and improved characteristics, compared to traditional hardware implementations. In this context, this paper reviews the most recent advancements toward the development of Cellular-Automata-based computing coupled with memristor devices. Several approaches for the design of such novel architectures, called “Memristive Cellular Automata”, exist in the literature. This extensive review provides a thorough insight into the most important developments so far, helping the reader to grasp all the necessary information, which is here presented in an organized and structured manner. Thus, this article aims to pave the way for further development in the field and to bring attention to technological aspects that require further investigation. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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